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From: Jeff Law <jeffreyalaw@gmail.com>
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>, gcc-patches@gcc.gnu.org
Cc: kito.cheng@sifive.com, palmer@rivosinc.com, rdapp.gcc@gmail.com
Subject: Re: [PATCH] RISC-V: Refactor the integer ternary autovec pattern
Date: Sat, 24 Jun 2023 08:03:47 -0600	[thread overview]
Message-ID: <18dffc14-01b4-ee87-d4a4-0423a4d9f727@gmail.com> (raw)
In-Reply-To: <20230621223842.259423-1-juzhe.zhong@rivai.ai>



On 6/21/23 16:38, Juzhe-Zhong wrote:
> Long time ago, I encounter ICE when trying to set clobber register as Pmode
> and I forgot the reason.
> 
> So, I clobber SI scratch and PUT_MODE to make it Pmode after reload which
> makes patterns look unreasonable.
> 
> According to Jeff's comments, I tried it again, it works now when we try to
> set clobber register as Pmode and the patterns look more reasonable now.
> 
> The tests are all passed, Ok for trunk.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/autovec.md (*fma<mode>): set clobber to Pmode in expand stage.
>          (*fma<VI:mode><P:mode>): Ditto.
>          (*fnma<mode>): Ditto.
>          (*fnma<VI:mode><P:mode>): Ditto.
OK
jeff

  parent reply	other threads:[~2023-06-24 14:03 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-21 22:38 Juzhe-Zhong
2023-06-24  1:32 ` 钟居哲
2023-06-24 14:03 ` Jeff Law [this message]
2023-06-24 14:43   ` Li, Pan2

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