From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29145 invoked by alias); 25 Oct 2009 07:09:48 -0000 Received: (qmail 29132 invoked by uid 22791); 25 Oct 2009 07:09:46 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from mail3.caviumnetworks.com (HELO mail3.caviumnetworks.com) (12.108.191.235) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 25 Oct 2009 07:09:42 +0000 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,5,4,7535) id ; Sun, 25 Oct 2009 00:09:29 -0700 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Sun, 25 Oct 2009 00:09:30 -0700 Received: from localhost ([76.191.141.226]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Sun, 25 Oct 2009 00:09:30 -0700 From: Adam Nemet MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-ID: <19171.63913.618530.372027@ropi.home> Date: Sun, 25 Oct 2009 10:49:00 -0000 To: Richard Sandiford Cc: gcc-patches@gcc.gnu.org, hutchinsonandy@gcc.gnu.org Subject: Re: [PATCH] Add MIPS64r2 support to mulsidi3_64bit In-Reply-To: <87hbtpt9w0.fsf@firetop.home> References: <19169.62748.654396.688151@ropi.home> <87hbtpt9w0.fsf@firetop.home> Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2009-10/txt/msg01519.txt.bz2 Richard Sandiford writes: > Very minor, but I find it more readable when the first part of the condition > exactly matches the associated define_insn, i.e.: > > "TARGET_64BIT && !TARGET_FIX_R4000 && ISA_HAS_EXT_INS && reload_completed" > > It seems a bit inconsistent to add hilo_operand while continuing to use > register_operand rather than d_operand for the rest. I'd prefer to use > register_operand for everything or specific operands for everything. > I suppose specific operands are better, so lets go with d_operand. > And sorry in advance if there are other examples of this. > > Same with the other split. > > OK for trunk with those changes, thanks. This is what I've checked in after retesting as before: Index: ChangeLog =================================================================== --- ChangeLog (revision 153537) +++ ChangeLog (working copy) @@ -1,4 +1,14 @@ - 2009-09-27 Andy Hutchinson +2009-10-24 Adam Nemet + + * config/mips/predicates.md (hilo_operand): New predicate. + * config/mips/mips.md (mulsidi3_64bit): Change it to a + define_insn. Correct !ISA_HAS_EXT_INS length from 24 to 28. Move + splitter part from here ...: + (mulsidi3_64bit splitter for !ISA_HAS_EXT_INS): ... to here. Swap + op0 and op4 to match the DINS case. + (mulsidi3_64bit splitter for ISA_HAS_EXT_INS): New splitter. + +2009-10-24 Andy Hutchinson PR middle-end/19154 * avr.md (QIDI): Add new mode iterator. Index: testsuite/ChangeLog =================================================================== --- testsuite/ChangeLog (revision 153537) +++ testsuite/ChangeLog (working copy) @@ -1,3 +1,7 @@ +2009-10-24 Adam Nemet + + * gcc.target/mips/mult-1.c: New test. + 2009-10-24 Janus Weil PR fortran/41784 Index: config/mips/predicates.md =================================================================== --- config/mips/predicates.md (revision 152466) +++ config/mips/predicates.md (working copy) @@ -119,6 +119,10 @@ (define_predicate "lo_operand" (and (match_code "reg") (match_test "REGNO (op) == LO_REGNUM"))) +(define_predicate "hilo_operand" + (and (match_code "reg") + (match_test "MD_REG_P (REGNO (op))"))) + (define_predicate "fcc_reload_operand" (and (match_code "reg,subreg") (match_test "ST_REG_P (true_regnum (op))"))) Index: config/mips/mips.md =================================================================== --- config/mips/mips.md (revision 152466) +++ config/mips/mips.md (working copy) @@ -1879,7 +1879,7 @@ (define_insn "mulsidi3_32bit_r4000" (set_attr "mode" "SI") (set_attr "length" "12")]) -(define_insn_and_split "mulsidi3_64bit" +(define_insn "mulsidi3_64bit" [(set (match_operand:DI 0 "register_operand" "=d") (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) @@ -1887,37 +1887,67 @@ (define_insn_and_split "mulsidi3_64bi (clobber (match_scratch:DI 4 "=d"))] "TARGET_64BIT && !TARGET_FIX_R4000" "#" - "&& reload_completed" + [(set_attr "type" "imul") + (set_attr "mode" "SI") + (set (attr "length") + (if_then_else (ne (symbol_ref "ISA_HAS_EXT_INS") (const_int 0)) + (const_int 16) + (const_int 28)))]) + +(define_split + [(set (match_operand:DI 0 "d_operand") + (mult:DI (any_extend:DI (match_operand:SI 1 "d_operand")) + (any_extend:DI (match_operand:SI 2 "d_operand")))) + (clobber (match_operand:TI 3 "hilo_operand")) + (clobber (match_operand:DI 4 "d_operand"))] + "TARGET_64BIT && !TARGET_FIX_R4000 && ISA_HAS_EXT_INS && reload_completed" [(set (match_dup 3) (unspec:TI [(mult:DI (any_extend:DI (match_dup 1)) (any_extend:DI (match_dup 2)))] UNSPEC_SET_HILO)) - ;; OP4 <- LO, OP0 <- HI - (set (match_dup 4) (match_dup 5)) - (set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI)) + ;; OP0 <- LO, OP4 <- HI + (set (match_dup 0) (match_dup 5)) + (set (match_dup 4) (unspec:DI [(match_dup 3)] UNSPEC_MFHI)) + + (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 32)) + (match_dup 4))] + { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); }) + +(define_split + [(set (match_operand:DI 0 "d_operand") + (mult:DI (any_extend:DI (match_operand:SI 1 "d_operand")) + (any_extend:DI (match_operand:SI 2 "d_operand")))) + (clobber (match_operand:TI 3 "hilo_operand")) + (clobber (match_operand:DI 4 "d_operand"))] + "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_EXT_INS && reload_completed" + [(set (match_dup 3) + (unspec:TI [(mult:DI (any_extend:DI (match_dup 1)) + (any_extend:DI (match_dup 2)))] + UNSPEC_SET_HILO)) + + ;; OP0 <- LO, OP4 <- HI + (set (match_dup 0) (match_dup 5)) + (set (match_dup 4) (unspec:DI [(match_dup 3)] UNSPEC_MFHI)) ;; Zero-extend OP4. - (set (match_dup 4) - (ashift:DI (match_dup 4) + (set (match_dup 0) + (ashift:DI (match_dup 0) (const_int 32))) - (set (match_dup 4) - (lshiftrt:DI (match_dup 4) + (set (match_dup 0) + (lshiftrt:DI (match_dup 0) (const_int 32))) ;; Shift OP0 into place. - (set (match_dup 0) - (ashift:DI (match_dup 0) + (set (match_dup 4) + (ashift:DI (match_dup 4) (const_int 32))) ;; OR the two halves together (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))] - { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); } - [(set_attr "type" "imul") - (set_attr "mode" "SI") - (set_attr "length" "24")]) + { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); }) (define_insn "mulsidi3_64bit_hilo" [(set (match_operand:TI 0 "register_operand" "=x") Index: testsuite/gcc.target/mips/mult-1.c =================================================================== --- testsuite/gcc.target/mips/mult-1.c (revision 0) +++ testsuite/gcc.target/mips/mult-1.c (revision 0) @@ -0,0 +1,14 @@ +/* For SI->DI widening multiplication we should use DINS to combine the two + halves. */ +/* { dg-options "-O -mgp64 isa_rev>=2" } */ +/* { dg-final { scan-assembler "\tdins\t" } } */ +/* { dg-final { scan-assembler-not "\tdsll\t" } } */ +/* { dg-final { scan-assembler-not "\tdsrl\t" } } */ +/* { dg-final { scan-assembler-not "\tor\t" } } */ + +NOMIPS16 unsigned long long +f (unsigned int i, unsigned int j) +{ + i++; + return (unsigned long long) i * j; +}