From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 33673 invoked by alias); 29 Aug 2019 15:32:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 33664 invoked by uid 89); 29 Aug 2019 15:32:23 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-17.5 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=6m, HContent-Transfer-Encoding:8bit X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 29 Aug 2019 15:32:22 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 50AAB28; Thu, 29 Aug 2019 08:32:20 -0700 (PDT) Received: from [10.2.206.47] (e120808-lin.cambridge.arm.com [10.2.206.47]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E5A493F718; Thu, 29 Aug 2019 08:32:19 -0700 (PDT) Subject: Re: [ARM/FDPIC v5 13/21] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture To: Christophe Lyon , "gcc-patches@gcc.gnu.org" References: <20190515124006.25840-1-christophe.lyon@st.com> <20190515124006.25840-14-christophe.lyon@st.com> From: Kyrill Tkachov Message-ID: <19a091e0-c1fe-c4f7-5eab-5e09ab1de3fd@foss.arm.com> Date: Thu, 29 Aug 2019 15:37:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 MIME-Version: 1.0 In-Reply-To: <20190515124006.25840-14-christophe.lyon@st.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-SW-Source: 2019-08/txt/msg01995.txt.bz2 Hi Christophe, On 5/15/19 1:39 PM, Christophe Lyon wrote: > Without this, when we are unwinding across a signal frame we can jump > to an even address which leads to an exception. > > This is needed in __gnu_persnality_sigframe_fdpic() when restoring the > PC from the signal frame since the PC saved by the kernel has the LSB > bit set to zero. > > 2019-XX-XX  Christophe Lyon  >         Mickaël Guêné > >         libgcc/ >         * config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle v7m >         architecture. > > Change-Id: Ie84de548226bcf1751e19a09e8f091fb3013ccea > > diff --git a/libgcc/config/arm/unwind-arm.c > b/libgcc/config/arm/unwind-arm.c > index 9ba73e7..ba47150 100644 > --- a/libgcc/config/arm/unwind-arm.c > +++ b/libgcc/config/arm/unwind-arm.c > @@ -199,6 +199,11 @@ _Unwind_VRS_Result _Unwind_VRS_Set > (_Unwind_Context *context, >          return _UVRSR_FAILED; > >        vrs->core.r[regno] = *(_uw *) valuep; > +#if defined(__ARM_ARCH_7M__) > +      /* Force LSB bit since we always run thumb code.  */ > +      if (regno == 15) > +       vrs->core.r[regno] |= 1; > +#endif Hmm, this looks quite specific. There are other architectures that are thumb-only too (6-M, 7E-M etc). Would checking for __thumb__ be better? Thanks, Kyrill >        return _UVRSR_OK; > >      case _UVRSC_VFP: > -- > 2.6.3 >