Re: Re: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -O0.

["juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>]

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Thanks for taking care of this issue.
Ok to backport GCC-13.



juzhe.zhong@rivai.ai
 
From: Li Xu
Date: 2023-08-28 10:33
To: xuli1; gcc-patches
CC: kito.cheng; palmer; juzhe.zhong
Subject: Re: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -O0.
This patch should be backported to releases/gcc-13 to address 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111076
 
--------------
Li Xu
>This issue happens is because the operand1 of scalar move can be
>REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
>not insert the vsetvl instruction correctly, and the compiler crashes.
>
>Consider this following case:
>int16_t foo1 (void *base, size_t vl)
>{
>    int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base, vl));
>    return maxVal;
>}
>
>Before this patch:
>bug.c:15:1: internal compiler error: Segmentation fault
>   15 | }
>      | ^
>0x145d723 crash_signal
>        ../.././riscv-gcc/gcc/toplev.cc:314
>0x22929dd const_csr_operand(rtx_def*, machine_mode)
>        ../.././riscv-gcc/gcc/config/riscv/predicates.md:44
>0x2292a21 csr_operand(rtx_def*, machine_mode)
>        ../.././riscv-gcc/gcc/config/riscv/predicates.md:46
>0x23dfbb0 recog_356
>        ../.././riscv-gcc/gcc/config/riscv/iterators.md:72
>0x23efecd recog(rtx_def*, rtx_insn*, int*)
>        ../.././riscv-gcc/gcc/config/riscv/iterators.md:89
>0xdddc15 recog_memoized(rtx_insn*)
>        ../.././riscv-gcc/gcc/recog.h:273
>
>After this patch:
> vsetivli zero,0,e16,m1,ta,ma
> vmv.x.s a5,v1
>
>gcc/ChangeLog:
>
>        * config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv.x.s intruction replace null avl with (const_int 0).
>
>gcc/testsuite/ChangeLog:
>
>        * gcc.target/riscv/rvv/base/scalar_move-10.c: New test.
>        * gcc.target/riscv/rvv/base/scalar_move-11.c: New test.
>---
> gcc/config/riscv/riscv-vsetvl.cc              |  5 +++
> .../riscv/rvv/base/scalar_move-10.c           | 31 +++++++++++++++++++
> .../riscv/rvv/base/scalar_move-11.c           | 20 ++++++++++++
> 3 files changed, 56 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
>
>diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
>index d4d6f336ef9..14ebae1f3f6 100644
>--- a/gcc/config/riscv/riscv-vsetvl.cc
>+++ b/gcc/config/riscv/riscv-vsetvl.cc
>@@ -618,6 +618,11 @@ static rtx
> gen_vsetvl_pat (enum vsetvl_type insn_type, const vl_vtype_info &info, rtx vl)
> {
>   rtx avl = info.get_avl ();
>+  /* if optimization == 0 and the instruction is vmv.x.s/vfmv.f.s,
>+     set the value of avl to (const_int 0) so that VSETVL PASS will
>+     insert vsetvl correctly.*/
>+  if (info.has_avl_no_reg ())
>+    avl = GEN_INT (0);
>   rtx sew = gen_int_mode (info.get_sew (), Pmode);
>   rtx vlmul = gen_int_mode (info.get_vlmul (), Pmode);
>   rtx ta = gen_int_mode (info.get_ta (), Pmode);
>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
>new file mode 100644
>index 00000000000..9760d77fb22
>--- /dev/null
>+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
>@@ -0,0 +1,31 @@
>+/* { dg-do compile } */
>+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
>+/* { dg-final { check-function-bodies "**" "" } } */
>+
>+#include "riscv_vector.h"
>+
>+/*
>+** foo1:
>+** ...
>+** vsetivli\tzero,0,e16,m1,t[au],m[au]
>+** vmv.x.s\t[a-x0-9]+,v[0-9]+
>+** ...
>+*/
>+int16_t foo1 (void *base, size_t vl)
>+{
>+    int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base, vl));
>+    return maxVal;
>+}
>+
>+/*
>+** foo2:
>+** ...
>+** vsetivli\tzero,0,e32,m1,t[au],m[au]
>+** vfmv.f.s\tf[a-x0-9]+,v[0-9]+
>+** ...
>+*/
>+float foo2 (void *base, size_t vl)
>+{
>+    float maxVal = __riscv_vfmv_f_s_f32m1_f32 (__riscv_vle32_v_f32m1 (base, vl));
>+    return maxVal;
>+}
>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
>new file mode 100644
>index 00000000000..8036acd0a52
>--- /dev/null
>+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
>@@ -0,0 +1,20 @@
>+/* { dg-do compile } */
>+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O0" } */
>+/* { dg-final { check-function-bodies "**" "" } } */
>+
>+#include "riscv_vector.h"
>+
>+/*
>+** foo:
>+** ...
>+** vsetivli\tzero,0,e64,m4,t[au],m[au]
>+** vmv.x.s\t[a-x0-9]+,v[0-9]+
>+** vsetivli\tzero,0,e64,m4,t[au],m[au]
>+** vmv.x.s\t[a-x0-9]+,v[0-9]+
>+** ...
>+*/
>+int16_t foo (void *base, size_t vl)
>+{
>+    int16_t maxVal = __riscv_vmv_x_s_i64m4_i64 (__riscv_vle64_v_i64m4 (base, vl));
>+    return maxVal;
>+}
>--
>2.17.1