From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 8BB8D3858C62 for ; Thu, 25 Jan 2024 07:50:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8BB8D3858C62 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8BB8D3858C62 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706169024; cv=none; b=S+JoxE0d0rZsYD0/BZMyiTDVnkHkblArGek2BlO4Hk6mq2XS19Y3Ch+bPgJPlNpphWGkrCDtP0n9Y+8QpbhMrFAefe/bmMm7IAxKBEtcROL/85ONXOZzmDTy4a+WZrLLTw8b0E8NCjHxiTLUi57wjjAClCednm9z68p48F4VjPQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706169024; c=relaxed/simple; bh=n9EBVWAd5kyP+st4AhoDMEh1WxNycz+C7cCcZ1iB5W4=; h=Subject:To:From:Message-ID:Date:MIME-Version; b=PhmKi/YgAyOGl+d6TfjW70eApGnEHTBLdOJYO5YVD5Ol4soDo/Sdopa5xo6XxK4GZxZm+OWLjB6UIJr4LqoZVpmf32X00BjTKan00zSfStlvH6EdiJ40/aEVkeNrnOJCOjKn6FbMUDCjz2ufvBoXcOAX5yAEtpi63XPICqthIeE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.105]) by gateway (Coremail) with SMTP id _____8BxSOi5ErJlznAFAA--.1067S3; Thu, 25 Jan 2024 15:50:17 +0800 (CST) Received: from [10.20.4.105] (unknown [10.20.4.105]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxdMy4ErJlR_EYAA--.60549S3; Thu, 25 Jan 2024 15:50:16 +0800 (CST) Subject: Re: [PATCH] Loongarch: Remove vec_concatz pattern To: chenglulu , gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn References: <20240124091913.38156-1-xujiahao@loongson.cn> From: Jiahao Xu Message-ID: <1b658daa-9f5f-6ad9-e184-1442f2a29106@loongson.cn> Date: Thu, 25 Jan 2024 15:50:16 +0800 User-Agent: Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-CM-TRANSID:AQAAf8DxdMy4ErJlR_EYAA--.60549S3 X-CM-SenderInfo: 50xmxthkdrqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBj93XoWxGF18Cw1UGryxXF18Aw1xtFc_yoW5Cw1UpF WkC3srGrWDJas3WF1kJ3yUXrW5Jry2g3ZrZF13XFy8Aw47uryj9r4UXr9I9F4DZw4rWry7 XF10kw13Za1UJrcCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUU9ab4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r106r15McIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41lc7I2V7IY0VAS07 AlzVAYIcxG8wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwCFI7km07C2 67AKxVWUAVWUtwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI 8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWU CwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r 1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsG vfC2KfnxnUUI43ZEXa7IU8j-e5UUUUU== X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,BODY_8BITS,GIT_PATCH_0,KAM_DMARC_STATUS,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: 在 2024/1/25 下午3:46, chenglulu 写道: > Jiahao: > >  Note that the LoongArch 'a' in the title needs to be capitalized. > >  I modified this patch and incorporated it first. > > Thanks, I'll pay attention next time. > 在 2024/1/24 下午5:19, Jiahao Xu 写道: >> It is incorrect to use vld/vori to implement the vec_concatz >> because when the LSX >> instruction is used to update the value of the vector register, the >> upper 128 bits of >> the vector register will not be zeroed. >> >> gcc/ChangeLog: >> >>     * config/loongarch/lasx.md (@vec_concatz): Remove this >> define_insn pattern. >>     * config/loongarch/loongarch.cc >> (loongarch_expand_vector_group_init): Use vec_concat. >> >> diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md >> index 90f66ee4d24..e2115ffb884 100644 >> --- a/gcc/config/loongarch/lasx.md >> +++ b/gcc/config/loongarch/lasx.md >> @@ -582,21 +582,6 @@ (define_insn "lasx_xvinsgr2vr_" >>     [(set_attr "type" "simd_insert") >>      (set_attr "mode" "")]) >>   -(define_insn "@vec_concatz" >> -  [(set (match_operand:LASX 0 "register_operand" "=f") >> -    (vec_concat:LASX >> -      (match_operand: 1 "nonimmediate_operand") >> -      (match_operand: 2 "const_0_operand")))] >> -  "ISA_HAS_LASX" >> -{ >> -  if (MEM_P (operands[1])) >> -    return "vld\t%w0,%1"; >> -  else >> -    return "vori.b\t%w0,%w1,0"; >> -} >> -  [(set_attr "type" "simd_splat") >> -   (set_attr "mode" "")]) >> - >>   (define_insn "vec_concat" >>     [(set (match_operand:LASX 0 "register_operand" "=f") >>       (vec_concat:LASX >> diff --git a/gcc/config/loongarch/loongarch.cc >> b/gcc/config/loongarch/loongarch.cc >> index 072c68d97e3..cd335827570 100644 >> --- a/gcc/config/loongarch/loongarch.cc >> +++ b/gcc/config/loongarch/loongarch.cc >> @@ -9917,17 +9917,12 @@ loongarch_expand_vector_group_init (rtx >> target, rtx vals) >>         gcc_unreachable (); >>       } >>   -  if (high == CONST0_RTX (half_mode)) >> -    emit_insn (gen_vec_concatz (vmode, target, low, high)); >> -  else >> -    { >> -      if (!register_operand (low, half_mode)) >> -    low = force_reg (half_mode, low); >> -      if (!register_operand (high, half_mode)) >> -    high = force_reg (half_mode, high); >> -      emit_insn (gen_rtx_SET (target, >> -                  gen_rtx_VEC_CONCAT (vmode, low, high))); >> -    } >> +  if (!register_operand (low, half_mode)) >> +    low = force_reg (half_mode, low); >> +  if (!register_operand (high, half_mode)) >> +    high = force_reg (half_mode, high); >> +  emit_insn (gen_rtx_SET (target, >> +              gen_rtx_VEC_CONCAT (vmode, low, high))); >>   } >>     /* Expand initialization of a vector which has all same >> elements.  */