From: Jim Wilson <jim.wilson@linaro.org>
To: Andrew Pinski <pinskia@gmail.com>, GCC Patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH/AARCH64] Improve ThunderX code generation slightly with load/store pair
Date: Fri, 05 Aug 2016 20:47:00 -0000 [thread overview]
Message-ID: <1c03b3fb-4070-2832-ff83-e778c6e9f7b5@linaro.org> (raw)
In-Reply-To: <CA+=Sn1mTJPVOke20gDmH=RrjEA-qvdg=b+CgSJReoi3rvzM25g@mail.gmail.com>
On 08/05/2016 12:18 AM, Andrew Pinski wrote:
> This patch disables the forming of the load/store pairs for SImode if
> we are tuning for ThunderX. I used the tuning flags route so it can
> be overridden if needed later on or if someone else wants to use the
> same method for their core.
+ if (mode == SImode
+ && AARCH64_EXTRA_TUNE_SLOW_LDPW
+ && !optimize_size)
+ return false;
AARCH64_EXTRA_TUNE_SLOW_LDPW is a non-zero bit-mask. That will always
be true. This is present in two places in the patch. You need
something more like
&& (aarch64_tune_params.extra_tuning_flags
& AARCH64_EXTRA_TUNE_SLOW_LDPW)
You should verify that the patch disables the optimization for ThunderX
but does not disable it for other targets.
Jim
next prev parent reply other threads:[~2016-08-05 20:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-05 7:18 Andrew Pinski
2016-08-05 20:47 ` Jim Wilson [this message]
2016-08-08 17:48 ` Andrew Pinski
2016-08-09 9:43 ` Richard Earnshaw (lists)
2016-09-12 21:29 ` Andrew Pinski
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