From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by sourceware.org (Postfix) with ESMTPS id 266F43858D28 for ; Sat, 17 Jun 2023 22:06:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 266F43858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-25bf7568f73so1555994a91.2 for ; Sat, 17 Jun 2023 15:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687039606; x=1689631606; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=/n1zEY92TmEyDbyevhpYACSqZ5t/m7oMUmDgAX3xtSI=; b=UT9DtQfDuDmj2KEsqjXP5FkBpQJAznCQCRa05O4HyXkQh82RlIQ0DxgR6jDxz2q1o7 m58mSHjaWIItNiuuWOsAz83I5hVzhaMFQN/tkBVc8c00S5Zd6XipyXuA2wfmzgew4px8 tkRJg6IF3rn2FjxA0a5+6g6zuAvmC3GKH6TnDbVWFdn8yBa4steEcDYIR/0nuwlDhX2g ykCcZ8R7DcZEdvufC6wE5P9kjQLiQ3T9oS5LWN8zhZa/buLGjDdY6GsYcCib8vdgpuS4 81H+6jQyVrgeeXAM2iVUG+6AL6bGEjqc4NLyYXggQ3yag6PT9eSMrPHXIZsF1G09SLnk Gqdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687039606; x=1689631606; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=/n1zEY92TmEyDbyevhpYACSqZ5t/m7oMUmDgAX3xtSI=; b=fdOS0aq0ADC96AvjopGyM6qQYS8F2m3/MxuwT5JWuIDbziM6K/tkiBG/Oz8mHGOfZY SoZKb4MpVAamaPBqKJ036uxZD+NCeUO42LSNr/ZVRZxl5ta8DBj93rRYRJhqKJ1KhDDW Bo3A8C3m9fUXoDFnWAL8fgTqnByAbIPmRQ1LZW4QPxbTTJ/DZ3dbA6/ZXWQ8FnY/7NC7 IhAWbyrDiklR/0VcQagq5a70t+bsE6QCn+Smoppi0oJ8N5FbOg8YiOQX8lGDZ/JrqrCz G6cpXKPAHqbOScHcsFQD3niD4kQDkRG8dfTzM6ByNliAL2SowfBV20jbQAmhEUUYxRqB KGMg== X-Gm-Message-State: AC+VfDweGLRduN9oEkBlMVRhPdQUUNBXx9AetulnNbJJTS5lE9y5SNAA zrc+vgqTb6Q+YG8PaqE9TTY= X-Google-Smtp-Source: ACHHUZ7A/+eES1BnAnmlIr00RDgTh8b7l3NOYWisIyR+YXfoWxbj1roO71l5ohR4pd2zHRJ/jxvDvw== X-Received: by 2002:a17:90a:6ac6:b0:25e:2348:6572 with SMTP id b6-20020a17090a6ac600b0025e23486572mr5971314pjm.43.1687039605736; Sat, 17 Jun 2023 15:06:45 -0700 (PDT) Received: from [172.31.0.109] ([136.36.130.248]) by smtp.gmail.com with ESMTPSA id go12-20020a17090b03cc00b00256a4d59bfasm3287737pjb.23.2023.06.17.15.06.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 17 Jun 2023 15:06:45 -0700 (PDT) Message-ID: <1c9281b7-b1ee-82e9-fbbb-9a7e00d475bf@gmail.com> Date: Sat, 17 Jun 2023 16:06:43 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks. Content-Language: en-US To: Robin Dapp , gcc-patches , palmer , Kito Cheng , "juzhe.zhong@rivai.ai" , vineetg@rivosinc.com, "Li, Pan2" References: From: Jeff Law In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_MANYTO,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 6/15/23 09:06, Robin Dapp wrote: > Hi, > > Changes from v1: > - Revamped the target selectors again. > - Fixed some syntax as well as caching errors that were still present. > - Adjusted some test cases I missed. > > The current situation with target selectors is improvable at best. > We definitely need to discern between being able to build a > test with the current configuration and running the test on the > current target which this patch attempts to do. There might > be a need for more fine-grained checks in the future that could > also go into our target-specific riscv.exp in the subdirectories > but for now I think we're good. > > A bit more detail is in the patch description below. The testsuite > is as clean as before for the configurations I tried: default, rv64gcv, > rv64gcv_zfhmin, rv64gc, rv64gc_zfh, rv64gc_zfhmin. I hope I didn't > overlook tests that appear unsupported now but shouldn't be. > > @Pan: No need to check the old version anymore, thanks. This patch > is preferred. > > Regards > Robin > > > This introduces new checks for run tests. Currently we have > riscv_vector as well as rv32 and rv64 which all check if GCC (with the > current configuration) can build the respective tests. > > Many tests specify e.g. a different -march for vector which > makes the check fail even though we could build as well as run > those tests. > > vector_hw now tries to compile, link and execute a simple vector example > file. If this succeeds the respective test can run. > > Similarly we introduce a zvfh_hw check which will be used in the > upcoming floating-point unop/binop tests as well as rv32_hw and > rv64_hw checks that are currently unused. > > To conclude: > - If we want a testcase to only compile when the current configuration > has vector support we use {riscv_vector}. > - If we want a testcase to run when the current target can supports > executing vector instructions we use {riscv_vector_hw}. > It still needs to be ensured that we can actually build the test > which can be achieved by either > (1) compiling with e.g. -march=rv64gcv or > (2) only enabling the test when the current configuration supports > vector via {riscsv_vector}. > > The same principle applies for zfh, zfhmin and zvfh but we do not yet > have all target selectors. In the meanwhile we need to make sure to > specify the proper -march flags like in (1). > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Use > riscv_vector_hw. > * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito. > * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito. > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Dito. > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Dito. > * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: > Dito. > * gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Dito. > * gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Dito. > * gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: > Dito. > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: > Dito. > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: > Dito. > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: > Dito. > * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: > Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Dito. > * gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Dito. > * gcc.target/riscv/rvv/autovec/series_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Dito. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Dito. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Dito. > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Dito. > * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Dito. > * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Dito. > * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: > Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: > Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: > Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Dito. > * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Dito. > * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Dito. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Use. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Use. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Use. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Use. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Use. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Use. > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Use. > * g++.target/riscv/rvv/base/bug-10.C: Use. > * g++.target/riscv/rvv/base/bug-11.C: Use. > * g++.target/riscv/rvv/base/bug-12.C: Use. > * g++.target/riscv/rvv/base/bug-13.C: Use. > * g++.target/riscv/rvv/base/bug-14.C: Use. > * g++.target/riscv/rvv/base/bug-15.C: Use. > * g++.target/riscv/rvv/base/bug-16.C: Use. > * g++.target/riscv/rvv/base/bug-17.C: Use. > * g++.target/riscv/rvv/base/bug-2.C: Use. > * g++.target/riscv/rvv/base/bug-23.C: Use. > * g++.target/riscv/rvv/base/bug-3.C: Use. > * g++.target/riscv/rvv/base/bug-4.C: Use. > * g++.target/riscv/rvv/base/bug-5.C: Use. > * g++.target/riscv/rvv/base/bug-6.C: Use. > * g++.target/riscv/rvv/base/bug-7.C: Use. > * g++.target/riscv/rvv/base/bug-8.C: Use. > * g++.target/riscv/rvv/base/bug-9.C: Use. > * lib/target-supports.exp: Add riscv_vect_hw, rv32_hw, rv64_hw > and zfh_hw, zfhmin_hw, zvfh_hw checks. I'm OK with the basic idea here and the dejagnu bits look reasonable. So I think the only question is whether or not others agree with the basic direction on the testsuite. So let's give the other RISC-V contributors a couple days to chime in. Jeff