From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id DEBA6385829B for ; Sun, 4 Feb 2024 03:20:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DEBA6385829B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DEBA6385829B Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707016832; cv=none; b=qx92OdcfBj891o8+2KtXzXB/xmTr3Slh8kyO/6ZxsXg33HbiwONA+rrTmVGyUUvZuI9iGgFPJCgckk7NuaXgDFmOa3El0sdgBzIxACmcp9Cg62xibQCJpbE1emw04FT/RtocXKUQyjwvo1LSo/SKvP9MqYjV1Ha+klpm0JHmH5g= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707016832; c=relaxed/simple; bh=NXqfbm2SL8GEL2YNgoWJo54DYk1hXC9Zf8RXl78vC0c=; h=Subject:To:From:Message-ID:Date:MIME-Version; b=UNjN0EkD92e9Gs5BpS9DjmFDJqtaJMKosRkW/7CBg6yimTnMDLePxtYwwd0AQVJaNGWyIPRXC8RfDJBpki8LYGB+Yqy4QmLL4NMa3sXUlavUjUewEZLX+yMJXxKvgRXb2OY4gwssbEMCm4qgt+p31XaibFkibo079sl1UHrbQfo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8BxC+l6Ar9lq4EKAA--.10364S3; Sun, 04 Feb 2024 11:20:26 +0800 (CST) Received: from [10.20.4.107] (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Ax3c55Ar9lViUvAA--.47116S3; Sun, 04 Feb 2024 11:20:25 +0800 (CST) Subject: Re: [PATCH] LoongArch: Fix wrong LSX FP vector negation To: Xi Ruoyao , gcc-patches@gcc.gnu.org Cc: i@xen0n.name, xuchenghua@loongson.cn References: <20240203085921.88049-1-xry111@xry111.site> From: chenglulu Message-ID: <1cd59522-8e76-36c4-d310-2edde394ccb9@loongson.cn> Date: Sun, 4 Feb 2024 11:20:25 +0800 User-Agent: Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20240203085921.88049-1-xry111@xry111.site> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-CM-TRANSID:AQAAf8Ax3c55Ar9lViUvAA--.47116S3 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoWxuF4kCw1fWF4UWryrGw4rWFX_yoWrZF17pr Z3u3Wakr48XrsFg3WkGay5Xw45KryxCF429FZxXrZFk34Duw18tryFkr9aqFyDX3yrXr4j va18K3WUXay5C3gCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUvIb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv 67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41lc7I2V7IY0VAS07 AlzVAYIcxG8wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02 F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw 1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7Cj xVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r 4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07jO b18UUUUU= X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,MIME_CHARSET_FARAWAY,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: ÔÚ 2024/2/3 ÏÂÎç4:58, Xi Ruoyao дµÀ: > We expanded (neg x) to (minus const0 x) for LSX FP vectors, this is > wrong because -0.0 is not 0 - 0.0. This causes some Python tests to > fail when Python is built with LSX enabled. > > Use the vbitrevi.{d/w} instructions to simply reverse the sign bit > instead. We are already doing this for LASX and now we can unify them > into simd.md. > > gcc/ChangeLog: > > * config/loongarch/lsx.md (neg2): Remove the > incorrect expand. > * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr. > (elmsgnbit): Likewise. > (neg2): New define_insn. > * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they > are now instantiated in simd.md. > --- > > Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk? LGTM! Thanks! > > gcc/config/loongarch/lasx.md | 16 ---------------- > gcc/config/loongarch/lsx.md | 11 ----------- > gcc/config/loongarch/simd.md | 18 ++++++++++++++++++ > 3 files changed, 18 insertions(+), 27 deletions(-) > > diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md > index e2115ffb884..ac84db7f0ce 100644 > --- a/gcc/config/loongarch/lasx.md > +++ b/gcc/config/loongarch/lasx.md > @@ -3028,22 +3028,6 @@ (define_insn "absv8sf2" > [(set_attr "type" "simd_logic") > (set_attr "mode" "V8SF")]) > > -(define_insn "negv4df2" > - [(set (match_operand:V4DF 0 "register_operand" "=f") > - (neg:V4DF (match_operand:V4DF 1 "register_operand" "f")))] > - "ISA_HAS_LASX" > - "xvbitrevi.d\t%u0,%u1,63" > - [(set_attr "type" "simd_logic") > - (set_attr "mode" "V4DF")]) > - > -(define_insn "negv8sf2" > - [(set (match_operand:V8SF 0 "register_operand" "=f") > - (neg:V8SF (match_operand:V8SF 1 "register_operand" "f")))] > - "ISA_HAS_LASX" > - "xvbitrevi.w\t%u0,%u1,31" > - [(set_attr "type" "simd_logic") > - (set_attr "mode" "V8SF")]) > - > (define_insn "xvfmadd4" > [(set (match_operand:FLASX 0 "register_operand" "=f") > (fma:FLASX (match_operand:FLASX 1 "register_operand" "f") > diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md > index 7002edae4d4..b9b94b9079c 100644 > --- a/gcc/config/loongarch/lsx.md > +++ b/gcc/config/loongarch/lsx.md > @@ -728,17 +728,6 @@ (define_expand "neg2" > DONE; > }) > > -(define_expand "neg2" > - [(set (match_operand:FLSX 0 "register_operand") > - (neg:FLSX (match_operand:FLSX 1 "register_operand")))] > - "ISA_HAS_LSX" > -{ > - rtx reg = gen_reg_rtx (mode); > - emit_move_insn (reg, CONST0_RTX (mode)); > - emit_insn (gen_sub3 (operands[0], reg, operands[1])); > - DONE; > -}) > - > (define_expand "lsx_vrepli" > [(match_operand:ILSX 0 "register_operand") > (match_operand 1 "const_imm10_operand")] > diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md > index cb0a19447a1..00ff2823a4e 100644 > --- a/gcc/config/loongarch/simd.md > +++ b/gcc/config/loongarch/simd.md > @@ -85,12 +85,21 @@ (define_mode_attr simdfmt [(V2DF "d") (V4DF "d") > (define_mode_attr simdifmt_for_f [(V2DF "l") (V4DF "l") > (V4SF "w") (V8SF "w")]) > > +;; Suffix for integer mode in LSX or LASX instructions to operating FP > +;; vectors using integer vector operations. > +(define_mode_attr simdfmt_as_i [(V2DF "d") (V4DF "d") > + (V4SF "w") (V8SF "w")]) > + > ;; Size of vector elements in bits. > (define_mode_attr elmbits [(V2DI "64") (V4DI "64") > (V4SI "32") (V8SI "32") > (V8HI "16") (V16HI "16") > (V16QI "8") (V32QI "8")]) > > +;; The index of sign bit in FP vector elements. > +(define_mode_attr elmsgnbit [(V2DF "63") (V4DF "63") > + (V4SF "31") (V8SF "31")]) > + > ;; This attribute is used to form an immediate operand constraint using > ;; "const__operand". > (define_mode_attr bitimm [(V16QI "uimm3") (V32QI "uimm3") > @@ -457,6 +466,15 @@ (define_expand "reduc__scal_" > DONE; > }) > > +;; FP negation. > +(define_insn "neg2" > + [(set (match_operand:FVEC 0 "register_operand" "=f") > + (neg:FVEC (match_operand:FVEC 1 "register_operand" "f")))] > + "" > + "vbitrevi.\t%0,%1," > + [(set_attr "type" "simd_logic") > + (set_attr "mode" "")]) > + > ; The LoongArch SX Instructions. > (include "lsx.md") >