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[149.172.150.237]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5ce59ecbc0sm234145366b.200.2024.05.17.08.27.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 May 2024 08:27:04 -0700 (PDT) Message-ID: <1d8f76e3-bc27-4802-823a-fe205ace590c@gmail.com> Date: Fri, 17 May 2024 17:27:03 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: rdapp.gcc@gmail.com Content-Language: en-US To: gcc-patches From: Robin Dapp Subject: [PATCH] RISC-V: Remove dead perm series code and document. Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, with the introduction of shuffle_series_patterns the explicit handler code for a perm series is dead. This patch removes it and also adds a function-level comment to shuffle_series_patterns. Regtested on rv64gcv_zvfh_zvbb. Regards Robin gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Document. (shuffle_extract_and_slide1up_patterns): Remove. --- gcc/config/riscv/riscv-v.cc | 26 ++++---------------------- 1 file changed, 4 insertions(+), 22 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 8b41b9c7774..93c2dcd04e4 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1485,28 +1485,6 @@ expand_const_vector (rtx target, rtx src) emit_vlmax_insn (code_for_pred_merge (mode), MERGE_OP, ops); } } - else if (npatterns == 1 && nelts_per_pattern == 3) - { - /* Generate the following CONST_VECTOR: - { base0, base1, base1 + step, base1 + step * 2, ... } */ - rtx base0 = builder.elt (0); - rtx base1 = builder.elt (1); - rtx base2 = builder.elt (2); - - rtx step = simplify_binary_operation (MINUS, builder.inner_mode (), - base2, base1); - - /* Step 1 - { base1, base1 + step, base1 + step * 2, ... } */ - rtx tmp = gen_reg_rtx (mode); - expand_vec_series (tmp, base1, step); - /* Step 2 - { base0, base1, base1 + step, base1 + step * 2, ... } */ - if (!rtx_equal_p (base0, const0_rtx)) - base0 = force_reg (builder.inner_mode (), base0); - - insn_code icode = optab_handler (vec_shl_insert_optab, mode); - gcc_assert (icode != CODE_FOR_nothing); - emit_insn (GEN_FCN (icode) (target, tmp, base0)); - } else /* TODO: We will enable more variable-length vector in the future. */ gcc_unreachable (); @@ -3580,6 +3558,10 @@ shuffle_extract_and_slide1up_patterns (struct expand_vec_perm_d *d) return true; } +/* This looks for a series pattern in the provided vector permute structure D. + If successful it emits a series insn as well as a gather to implement it. + Return true if successful, false otherwise. */ + static bool shuffle_series_patterns (struct expand_vec_perm_d *d) { -- 2.45.0