[PATCH 0/2][GCC][Arm]: MVE fixes for codegen and testsuite

[PATCH 0/2][GCC][Arm]: MVE fixes for codegen and testsuite

[Andre Vieira (lists)]

Hi,

I noticed some issues with the patches that landed on trunk and this 
patch series fixes them.  The first issue was revealed after I fixed the 
testisms (in patch 2/2).
Andre Vieira (2):
Fix MVE move from GPR -> GPR
Fix testisms for MVE testsuite

[PATCH 1/2][GCC][Arm]: Fix MVE move from GPR -> GPR

[Andre Vieira (lists)]

[-- Attachment #1: Type: text/plain, Size: 635 bytes --]

Hi,

This patch fixes the pattern mve_mov for the case where both MVE vectors 
are in R registers and the move does not get optimized away.  I use the 
same approach as we do for NEON, where we use four register moves.

Bootstrapped on arm-linux-gnueabihf and ran mve testsuite on arm-none-eabi.

Is this OK for trunk?

gcc/ChangeLog:
2020-03-20  Andre Vieira  <andre.simoesdiasvieira@arm.com>

         * config/arm/mve.md (mve_mov<mode>): Fix R->R case.

gcc/testsuite/ChangeLog:
2020-03-**  Andre Vieira  <andre.simoesdiasvieira@arm.com>

         * gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c: New test.

[-- Attachment #2: mve_r_to_r.patch.txt --]
[-- Type: text/plain, Size: 1621 bytes --]

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 3cdb2e71cf04d45d220f6667646d226c8015659a..3015df7a6af0ab50e0ae47894f63597ada8566c5 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -295,7 +295,7 @@ (define_insn "*mve_mov<mode>"
       else
 	return "vldrb.8 %q0, %E1";
     case 5:
-      return output_move_neon (operands);
+      return output_move_quad (operands);
     case 7:
       return "vstrb.8 %q1, %E0";
     default:
@@ -303,7 +303,7 @@ (define_insn "*mve_mov<mode>"
       return "";
     }
 }
-  [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,mve_move,mve_move,mve_store")
+  [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,multiple,mve_move,mve_store")
    (set_attr "length" "4,8,8,4,8,8,4,4")
    (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*")
    (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")])
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c
new file mode 100644
index 0000000000000000000000000000000000000000..791b8529a052dfca42e12648b6967eca3a2a985e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c
@@ -0,0 +1,18 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2 -mfloat-abi=softfp" } */
+
+#include "arm_mve.h"
+
+extern int bar (float16x8_t, float16_t);
+
+extern void foobar (float16_t);
+
+int
+foo (float16x8_t a, float16_t b)
+{
+  foobar (b);
+  return bar (a, b);
+}
+

[PATCH 2/2][GCC][Arm]: Fix testisms for MVE testsuite

[Andre Vieira (lists)]

[-- Attachment #1: Type: text/plain, Size: 1557 bytes --]

Hi,

This patch fixes some testism where -mfpu=auto was missing or where we 
could end up with -mfloat-abi=hard and soft on the same command-line.

Tested on arm-none-eabi.

Is this OK for trunk?

gcc/testsuite/ChangeLog:
2020-03-20  Andre Vieira  <andre.simoesdiasvieira@arm.com>

         * gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c: Fix testisms.
         * gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_fpu1.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_fpu2.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_fpu3.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_libcall1.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_libcall2.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_vector_float.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise.
         * gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise.
         * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c

[-- Attachment #2: testisms.patch --]
[-- Type: text/plain, Size: 12674 bytes --]

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c
index 17ba616c041378b88463cb7ef150b70b2e7b95ad..d552fbdffee2ac57092e20ce6a02ab3a4b4bd367 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb" } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb -mfpu=auto" } */
 
 #include "arm_mve.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c
index 7b877c4a90c506343d6b4edb750ba06ce3d7a68d..e40b82ec161ac4155c3e38fad1438c296db76486 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c
@@ -1,6 +1,6 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=softfp -mthumb" } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=softfp -mthumb -mfpu=auto" } */
 
 #include "arm_mve.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c
index 85fbb5767edc3c25ceb4d6da780d47afa1ee416c..e04cb61043859b2c5484f97d1450ef97076d6a2d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb -mfpu=auto" } */
 
 #include "arm_mve.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c
index 23b3683ae559b3f7bf6c3ad11c4070ad2ddb9387..f52c3627551750cbaaf54f0ac94020db7a92c6ca 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=softfp -mthumb" } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=softfp -mthumb -mfpu=auto" } */
 
 #include "arm_mve.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c
index 8f7fa348d130e8456d5300ac25821fd96f9d5a97..1f249ca885faeea58951a702d090d49af525eeed 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=soft -mthumb" } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=hard" } { "" } } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=soft -mthumb -mfpu=auto" } */
 
 int
 foo1 (int value)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c
index 7c38d3102d26d8d7f6358258018a993df8298b4d..03347d494b9a78c514316e560ee103fcd5ded8b8 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c
@@ -1,5 +1,6 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb -mfpu=auto" } */
 
 float
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c
index 773c8449edbe467dcdfcee260a9a04e2d4a5b0e7..f6291b7ccf7fd7320ceae5c86bc91c42a12fba78 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c
@@ -1,5 +1,6 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
 /* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb -mfpu=auto" } */
 
 double
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c
index ac51f7ff4be1d9a24c9a8657541b2d2273539d50..eac2c845972a828a9b8046c4c644afda8f4b5013 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb" } */
 
 #include "arm_mve.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c
index d41900c20ea533519bc0da729ef01bf0925083fa..d5319014d318f72b3b31961edd00a91ee96abb5c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb" } */
 
 #include "arm_mve.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c
index f02dd8b5f15e86356512d0f2c02d0f59a53c6d4b..bf39fc6837628c1ac0baef594cc824522ae052e2 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
-/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -mthumb" } */
 
 #include "arm_mve.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c
index dfe08b9c9f53db4ee3ae62e1a9eec863675fcba8..3a63b590fcba3984f84f8c9cbb8f62f8eb3d0459 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */
 
 #include "arm_mve.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c
index cb96eb8d3ab5ced754ebf12724c0b692be114fd3..e15b10bcbdc185a7fffafd3bba11ae720f9139fe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */
 
 #include "arm_mve.h"
 
@@ -10,7 +11,7 @@ int32x4_t value3;
 int64x2_t value4;
 
 int8x16_t
-foo8 ()
+foo8 (void)
 {
   int8x16_t b = value1;
   return b;
@@ -21,7 +22,7 @@ foo8 ()
 /* { dg-final { scan-assembler "vldrb.8*" }  } */
 
 int16x8_t
-foo16 ()
+foo16 (void)
 {
   int16x8_t b = value2;
   return b;
@@ -32,7 +33,7 @@ foo16 ()
 /* { dg-final { scan-assembler "vldrb.8*" }  } */
 
 int32x4_t
-foo32 ()
+foo32 (void)
 {
   int32x4_t b = value3;
   return b;
@@ -43,7 +44,7 @@ foo32 ()
 /* { dg-final { scan-assembler "vldrb.8" }  } */
 
 int64x2_t
-foo64 ()
+foo64 (void)
 {
   int64x2_t b = value4;
   return b;
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c
index 32f589aad528314b7f2bf4cb680ab70b66a19514..a7f66ce9bea88de7b967b693f51970784231f477 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */
 
 #include "arm_mve.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c
index 1957d384ca0b5a273d8182e77b592d732694690c..6e2e768146767b623de080f4025ed264678abf17 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */
 
 #include "arm_mve.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c
index 0561178a8d3b5c1f4952da62aa6a2c1692fea849..d6dba65167a6a69565b87a2172e9a14097ec4f40 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */
 
 #include "arm_mve.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c
index 8b4f4cbb8cde8372044fa39dba96fdf29fd9eeb8..70091970de8cc9f048a8f9526825789b9de38500 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
-/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=soft" } {""} } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -mthumb" } */
 
 #include "arm_mve.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
index 6c3eda56a17f034f362eb5b7302a8fac5312d2c5..2fe8c5f06977caa0b3ac6fad144a5cdc55ff5b62 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c
@@ -1,6 +1,7 @@
 /* { dg-do compile  } */
-/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2"  }  */
-/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
 
 #include "arm_mve.h"
 

RE: [PATCH 1/2][GCC][Arm]: Fix MVE move from GPR -> GPR

[Kyrylo Tkachov]

Hi Andre,

> -----Original Message-----
> From: Andre Vieira (lists) <andre.simoesdiasvieira@arm.com>
> Sent: 20 March 2020 08:48
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
> Subject: [PATCH 1/2][GCC][Arm]: Fix MVE move from GPR -> GPR
> 
> Hi,
> 
> This patch fixes the pattern mve_mov for the case where both MVE vectors
> are in R registers and the move does not get optimized away.  I use the same
> approach as we do for NEON, where we use four register moves.
> 
> Bootstrapped on arm-linux-gnueabihf and ran mve testsuite on arm-none-
> eabi.
> 
> Is this OK for trunk?

Ok.
Thanks,
Kyrill

> 
> gcc/ChangeLog:
> 2020-03-20  Andre Vieira  <andre.simoesdiasvieira@arm.com>
> 
>          * config/arm/mve.md (mve_mov<mode>): Fix R->R case.
> 
> gcc/testsuite/ChangeLog:
> 2020-03-**  Andre Vieira  <andre.simoesdiasvieira@arm.com>
> 
>          * gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c: New test.

RE: [PATCH 2/2][GCC][Arm]: Fix testisms for MVE testsuite

[Kyrylo Tkachov]

Hi Andre,

> -----Original Message-----
> From: Andre Vieira (lists) <andre.simoesdiasvieira@arm.com>
> Sent: 20 March 2020 08:50
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
> Subject: [PATCH 2/2][GCC][Arm]: Fix testisms for MVE testsuite
> 
> Hi,
> 
> This patch fixes some testism where -mfpu=auto was missing or where we
> could end up with -mfloat-abi=hard and soft on the same command-line.
> 
> Tested on arm-none-eabi.
> 
> Is this OK for trunk?

Ok.
Thanks,
Kyrill

> 
> gcc/testsuite/ChangeLog:
> 2020-03-20  Andre Vieira  <andre.simoesdiasvieira@arm.com>
> 
>          * gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c: Fix testisms.
>          * gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_fpu1.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_fpu2.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_fpu3.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_libcall1.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_libcall2.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_vector_float.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_vector_float2.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_vector_int.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_vector_uint.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_vector_uint1.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/mve_vector_uint2.c: Likewise.
>          * gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c