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Message-ID: <1e19f9ed89f6d61c36e3ee64c894cdb6d14c1e19.camel@xry111.site>
Subject: Re: [PATCH v3] loongarch: fix mulsidi3_64bit instruction
From: Xi Ruoyao <xry111@xry111.site>
To: Lulu Cheng <chenglulu@loongson.cn>, gcc-patches@gcc.gnu.org
Cc: Chenghua Xu <xuchenghua@loongson.cn>, Wang Xuerui <i@xen0n.name>
Date: Sun, 10 Jul 2022 11:43:18 +0800
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On Sun, 2022-07-10 at 09:45 +0800, Lulu Cheng wrote:
>=20
> =E5=9C=A8 2022/7/9 =E4=B8=8A=E5=8D=8810:56, Xi Ruoyao =E5=86=99=E9=81=93:
> > v3: Relax scan-assembler pattern in test case mulw_d_w.c.=C2=A0 It's
> > because
> > multiplication is Abelian and the compiler may switch the order of
> > operands in the future.
> > -- >8 --
> >=20
> > (mult (sign_extend:DI rj:SI) (sign_extend:DI rk:SI)) should be
> > "mulw.d.w", not "mul.d".
> >=20
> > gcc/ChangeLog:
> >=20
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* config/loongarch/loon=
garch.md (mulsidi3_64bit): Use
> > mulw.d.w
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0instead of mul.d.
> >=20
> > gcc/testsuite/ChangeLog:
> >=20
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* gcc.target/loongarch/=
mulw_d_w.c: New test.
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* gcc.c-torture/execute=
/mul-sext.c: New test.
> > ---
>=20
> I think there is no problem with this modification.
>=20
> Thankes!
>=20

Pushed r13-1591 and r12-8562.

--=20
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University