From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7004 invoked by alias); 22 Sep 2014 12:07:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 6992 invoked by uid 89); 22 Sep 2014 12:07:09 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 X-HELO: na01-bl2-obe.outbound.protection.outlook.com Received: from mail-bl2on0061.outbound.protection.outlook.com (HELO na01-bl2-obe.outbound.protection.outlook.com) (65.55.169.61) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Mon, 22 Sep 2014 12:07:07 +0000 Received: from BN1BFFO11FD017.protection.gbl (10.58.144.30) by BN1BFFO11HUB049.protection.gbl (10.58.144.196) with Microsoft SMTP Server (TLS) id 15.0.1029.15; Mon, 22 Sep 2014 12:07:04 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BN1BFFO11FD017.mail.protection.outlook.com (10.58.144.80) with Microsoft SMTP Server (TLS) id 15.0.1029.15 via Frontend Transport; Mon, 22 Sep 2014 12:07:03 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-smtp1) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1XW2Og-0008Uf-Ak; Mon, 22 Sep 2014 05:07:14 -0700 From: Ajit Kumar Agarwal To: Richard Sandiford CC: Jeff Law , "gcc-patches@gcc.gnu.org" Subject: RE: [PATCH 0/5] Fix handling of word subregs of wide registers Date: Mon, 22 Sep 2014 12:07:00 -0000 References: <87ppetnsxd.fsf@e105548-lin.cambridge.arm.com> <541BC9A2.2030309@redhat.com> <87zjdwm5td.fsf@e105548-lin.cambridge.arm.com> <541C646E.8020505@redhat.com> <87ppeom83m.fsf@e105548-lin.cambridge.arm.com> <72631d17-c273-4813-95b4-720cd50fc4c3@BL2FFO11FD023.protection.gbl> <87vboflwv6.fsf@e105548-lin.cambridge.arm.com> In-Reply-To: <87vboflwv6.fsf@e105548-lin.cambridge.arm.com> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-RCIS-Action: ALLOW Message-ID: <1ede66b2-8e73-43be-96a1-44a76829b279@BN1BFFO11FD017.protection.gbl> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(438002)(189002)(51704005)(479174003)(377454003)(164054003)(24454002)(13464003)(199003)(104016003)(31966008)(70736001)(6806004)(64706001)(85306004)(44976005)(81542003)(80022003)(46406003)(81342003)(110136001)(93886004)(79102003)(19580395003)(53416004)(120916001)(33646002)(19580405001)(50466002)(47776003)(2656002)(85852003)(15975445006)(83322001)(83072002)(77096002)(92726001)(86362001)(20776003)(87936001)(23726002)(76176999)(54356999)(50986999)(21056001)(76482002)(106466001)(31696002)(74662003)(4396001)(74502003)(77982003)(95666004)(92566001)(107046002)(74316001)(46102003)(106116001)(1496007)(97756001)(90102001)(99396002)(107986001)(23106004);DIR:OUT;SFP:1101;SCL:1;SRVR:BN1BFFO11HUB049;H:xsj-pvapsmtpgw01;FPR:;MLV:sfv;PTR:unknown-60-83.xilinx.com;MX:1;A:1;LANG:en; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 034215E98F Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=ajit.kumar.agarwal@xilinx.com; X-OriginatorOrg: xilinx.com X-SW-Source: 2014-09/txt/msg01808.txt.bz2 -----Original Message----- From: Richard Sandiford [mailto:richard.sandiford@arm.com]=20 Sent: Monday, September 22, 2014 4:56 PM To: Ajit Kumar Agarwal Cc: Jeff Law; gcc-patches@gcc.gnu.org Subject: Re: [PATCH 0/5] Fix handling of word subregs of wide registers Ajit Kumar Agarwal writes: > Jeff Law writes: >> On 09/19/14 01:23, Richard Sandiford wrote: >>> Jeff Law writes: >>>> On 09/18/14 04:07, Richard Sandiford wrote: >>>>> This series is a cleaned-up version of: >>>>> >>>>> https://gcc.gnu.org/ml/gcc/2014-03/msg00163.html >>>>> >>>>> The underlying problem is that the semantics of subregs depend on=20 >>>>> the word size. You can't have a subreg for byte 2 of a 4-byte=20 >>>>> word, say, but you can have a subreg for word 2 of a 4-word value=20 >>>>> (as well as lowpart subregs of that word, etc.). This causes=20 >>>>> problems when an architecture has wider-than-word registers, since=20 >>>>> the addressability of a word can then depend on which register=20 >>>>> class is used. >>>>> >>>>> The register allocators need to fix up cases where a subreg turns=20 >>>>> out to be invalid for a particular class. This is really an=20 >>>>> extension of what we need to do for CANNOT_CHANGE_MODE_CLASS. >>>>> >>>>> Tested on x86_64-linux-gnu, powerpc64-linux-gnu and aarch64_be-elf. >>>> I thought we fixed these problems long ago with the change to subreg_b= yte?!? >>> >>> No, that was fixing something else. (I'm just about old enough to=20 >>> remember that too!) The problem here is that (say): >>> >>> (subreg:SI (reg:DI X) 4) >>> >>> is independently addressable on little-endian AArch32 if X assigned=20 >>> to a GPR, but not if X is assigned to a vector register. We need to=20 >>> allow these kinds of subreg on pseudos in order to decompose=20 >>> multiword arithmetic. It's then up to the RA to realise that a=20 >>> reload would be needed if X were assigned to a vector register,=20 >>> since the upper half of a vector register cannot be independently acces= sed. >>> >>> Note that you could write this example even with the old word-style=20 >>> offsets and IIRC the effect would have been the same. >> OK. So I kept thinking in terms of the byte offset stuff. But what=20 >> you're tackling is related to the mess around the mode of the subreg=20 >> having a different meaning if its smaller than a word vs word-sized=20 >> or greater. >> >> Right? > >>>Yeah, that's right. Addressability is based on words, which is=20=20 >>>inconvenient when your registers are bigger than a word. > > If the architecture like Microblaze which doesn't support the 1 byte=20 > or > 2 byte registers. In this scenario what should be returned when=20 > SUBREG_WORD is used. >>I don't understand the question sorry. Subreg offsets are still represen= ted as bytes rather than words. The patch doesn't change the way that subr= egs are >>represented or the rules about which subregs are valid. >>Both before and after the patch, the semantics of subregs say that if you= have 4-byte words, only one of: >>(subreg:QI (reg:SI X) 0) >>(subreg:QI (reg:SI X) 1) >>(subreg:QI (reg:SI X) 2) >>(subreg:QI (reg:SI X) 3) >>is ever valid (0 for little-endian, 3 for big-endian). Writing to that o= ne valid subreg will change the whole of X, unless the subreg is wrapped in= a >>strict_lowpart. In other words, subregs are defined so that individua= l parts of a word are not independently addressable. >>However, individual words of a multiword register _are_ addressable. I.e= .: (subreg:SI (reg:DI Y) 0) (subreg:SI (reg:DI Y) 4) >>are both valid. Writing to one does not change the other. >>The problem the patch was trying to solve was that you can have targets w= ith 4-byte words but some 8-byte registers. In those cases, it's still pos= sible to >>form both of the Y subregs above if Y is allocated to a word-siz= ed register, but not if Y is allocated to a doubleword-sized register. Thanks Richard for the explanation.=20 Thanks, Richard