From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id B3EE8395BC36 for ; Fri, 13 May 2022 17:29:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B3EE8395BC36 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24DHH0VE010852; Fri, 13 May 2022 17:29:33 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3g1uk605u0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 May 2022 17:29:33 +0000 Received: from m0098413.ppops.net (m0098413.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 24DHKx0S024125; Fri, 13 May 2022 17:29:32 GMT Received: from ppma03dal.us.ibm.com (b.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.11]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3g1uk605tu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 May 2022 17:29:32 +0000 Received: from pps.filterd (ppma03dal.us.ibm.com [127.0.0.1]) by ppma03dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 24DHITuL022572; Fri, 13 May 2022 17:29:32 GMT Received: from b03cxnp08025.gho.boulder.ibm.com (b03cxnp08025.gho.boulder.ibm.com [9.17.130.17]) by ppma03dal.us.ibm.com with ESMTP id 3fwgdapmse-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 May 2022 17:29:32 +0000 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 24DHTUdC27197702 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 May 2022 17:29:30 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B925EC6057; Fri, 13 May 2022 17:29:30 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F339AC6059; Fri, 13 May 2022 17:29:29 +0000 (GMT) Received: from lexx (unknown [9.160.59.210]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Fri, 13 May 2022 17:29:29 +0000 (GMT) Message-ID: <1f73a5822cd96e8f940d0212496562d6e49470f4.camel@vnet.ibm.com> Subject: Re: [PATCH] Replace UNSPEC with RTL code for extendditi2. From: will schmidt To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner Date: Fri, 13 May 2022 12:29:29 -0500 In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: u7flZIEvcHlngkLBxr5yAHozmYQKDYKn X-Proofpoint-GUID: NX28hPLzDglTS13Bsgzj46wE_TcDBrPw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-13_09,2022-05-13_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 clxscore=1015 lowpriorityscore=0 phishscore=0 malwarescore=0 spamscore=0 mlxscore=0 priorityscore=1501 adultscore=0 bulkscore=0 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2205130073 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 May 2022 17:29:35 -0000 On Fri, 2022-05-13 at 10:52 -0400, Michael Meissner wrote: > Replace UNSPEC with RTL code for extendditi2. > Hi, > When I submitted my patch on March 12th for extendditi2, Segher > wished I > had removed the use of the UNSPEC for the vextsd2q instruction. This > patch rewrites extendditi2_vector to use VEC_SELECT rather than > UNSPEC. I'd suggest a paragraph break between the two sentences. > > 2022-05-13 Michael Meissner > > gcc/ > * config/rs6000/vsx.md (UNSPEC_EXTENDDITI2): Delete. > (extendditi2_vector): Rewrite to use VEC_SELECT as a > define_expand. > (extendditi2_vector2): New insn. Ok, so per my interpretation of the patch below, it converts the define_insn extendditi2_vector into a define_expand, and creates a new extendditi2_vector2 instruction. Content below seems reasonable, I've not reviewed it extensively. Thanks -Will > --- > gcc/config/rs6000/vsx.md | 22 ++++++++++++++++++---- > 1 file changed, 18 insertions(+), 4 deletions(-) > > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index a1a1ce95195..c091e5e2f47 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -358,7 +358,6 @@ (define_c_enum "unspec" > UNSPEC_VSX_FIRST_MISMATCH_EOS_INDEX > UNSPEC_XXGENPCV > UNSPEC_MTVSBM > - UNSPEC_EXTENDDITI2 > UNSPEC_VCNTMB > UNSPEC_VEXPAND > UNSPEC_VEXTRACT > @@ -5083,10 +5082,25 @@ (define_insn_and_split "extendditi2" > (set_attr "type" "shift,load,vecmove,vecperm,load")]) > > ;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in > TI reg > -(define_insn "extendditi2_vector" > +(define_expand "extendditi2_vector" > + [(use (match_operand:TI 0 "gpc_reg_operand")) > + (use (match_operand:TI 1 "gpc_reg_operand"))] > + "TARGET_POWER10" > +{ > + rtx dest = operands[0]; > + rtx src_v2di = gen_lowpart (V2DImode, operands[1]); > + rtx element = GEN_INT (VECTOR_ELEMENT_SCALAR_64BIT); > + > + emit_insn (gen_extendditi2_vector2 (dest, src_v2di, element)); > + DONE; > +}) > + > +(define_insn "extendditi2_vector2" > [(set (match_operand:TI 0 "gpc_reg_operand" "=v") > - (unspec:TI [(match_operand:TI 1 "gpc_reg_operand" "v")] > - UNSPEC_EXTENDDITI2))] > + (sign_extend:TI > + (vec_select:DI > + (match_operand:V2DI 1 "gpc_reg_operand" "v") > + (parallel [(match_operand 2 "vsx_scalar_64bit" "wD")]))))] > "TARGET_POWER10" > "vextsd2q %0,%1" > [(set_attr "type" "vecexts")]) > -- > 2.35.3 > >