From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31569 invoked by alias); 19 Feb 2002 11:08:10 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 31292 invoked from network); 19 Feb 2002 11:07:54 -0000 Received: from unknown (HELO fw-cam.cambridge.arm.com) (193.131.176.3) by sources.redhat.com with SMTP; 19 Feb 2002 11:07:54 -0000 Received: by fw-cam.cambridge.arm.com; id LAA11456; Tue, 19 Feb 2002 11:07:52 GMT Received: from unknown(172.16.1.2) by fw-cam.cambridge.arm.com via smap (V5.5) id xma010877; Tue, 19 Feb 02 11:07:22 GMT Received: from cam-mail2.cambridge.arm.com (localhost [127.0.0.1]) by cam-admin0.cambridge.arm.com (8.9.3/8.9.3) with ESMTP id LAA14560; Tue, 19 Feb 2002 11:07:21 GMT Received: from sun18.cambridge.arm.com (sun18.cambridge.arm.com [172.16.2.18]) by cam-mail2.cambridge.arm.com (8.9.3/8.9.3) with ESMTP id LAA21194; Tue, 19 Feb 2002 11:07:20 GMT Message-Id: <200202191107.LAA21194@cam-mail2.cambridge.arm.com> X-Mailer: exmh version 2.0.2 2/24/98 To: Jim Wilson cc: Geoffrey Keating , gcc-patches@gcc.gnu.org, Richard.Earnshaw@arm.com Reply-To: Richard.Earnshaw@arm.com Organization: ARM Ltd. X-Telephone: +44 1223 400569 (direct+voicemail), +44 1223 400400 (switchbd) X-Fax: +44 1223 400410 X-Address: ARM Ltd., 110 Fulbourn Road, Cherry Hinton, Cambridge CB1 9NJ. X-Url: http://www.arm.com/ Subject: Re: [PCH] constant pools rewrite In-reply-to: Your message of "18 Feb 2002 19:28:37 PST." Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Tue, 19 Feb 2002 03:52:00 -0000 From: Richard Earnshaw X-SW-Source: 2002-02/txt/msg01291.txt.bz2 > Some targets have limited register sets and limited addressing modes. Thumb > and mips16 are good examples of this. It is so difficult to reach a per > file constant pool that it is impractical. You have to use per function > constant pools, and you have to make sure that the constant pools go in the > same section as the function. In some cases, not even this is good enough, > because if the function is too big, you won't be able to reach it unless > it is inline. Again, thumb and mips16 have this problem. Since the generic > constant pool code doesn't support inline constant pools, the arm and mips > backends need their own code. I don't remember which came first, but I'm > pretty sure one was originally a copy of the other. They have probably > diverged since then. There may be other targets with a copy of this code > also. The SH code came first; the original implementation on the ARM was a copy I made of that. Since then the ARM variant has been re-written at least a couple of times. The current incarnation should be fairly MI and supports both forward and back-ward relative loads, merging of common entries, hiding of pools behind branches (when possible) and sorting of the entries to increase the degree of freedom of location of the pool when some instructions have a more limited range than others. It would be an interesting project to see if that code could be cleaned up and made into an completely MI file that was used by the other ports requiring this sort of constant pool. R.