From: Jan Hubicka <jh@suse.cz>
To: Richard Henderson <rth@redhat.com>, Jan Hubicka <jh@suse.cz>,
gcc-patches@gcc.gnu.org, patches@x86-64.org
Subject: Re: Fix attributes for SSE/MMX instructions
Date: Tue, 30 Apr 2002 10:29:00 -0000 [thread overview]
Message-ID: <20020430172739.GT18000@atrey.karlin.mff.cuni.cz> (raw)
In-Reply-To: <20020429151942.D11370@redhat.com>
> General idea looks fine. I didn't proofread all the lines.
Well, there is not much ideas, just boring work :(
> Worse, Bernd committed a bunch of sse2 stuff this past weekend,
> so you'll have to update the patch.
Good timing, Bernd.
>
> I'll go ahead and pre-approve the thing. If there are any
> typos, we should be able to work that out fairly quickly.
Thanks. The exact patch I've commited is:
Index: i386.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.md,v
retrieving revision 1.349
diff -c -3 -p -r1.349 i386.md
*** i386.md 29 Apr 2002 18:40:47 -0000 1.349
--- i386.md 30 Apr 2002 17:18:41 -0000
***************
*** 122,145 ****
;; A basic instruction type. Refinements due to arguments to be
;; provided in other attributes.
(define_attr "type"
! "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx,fistp"
(const_string "other"))
;; Main data type used by the insn
! (define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI"
(const_string "unknown"))
! ;; Set for i387 operations.
! (define_attr "i387" ""
! (if_then_else (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
! (const_int 1)
! (const_int 0)))
;; The (bounding maximum) length of an instruction immediate.
(define_attr "length_immediate" ""
! (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv,sse,mmx")
(const_int 0)
! (eq_attr "i387" "1")
(const_int 0)
(eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
(symbol_ref "ix86_attr_length_immediate_default(insn,1)")
--- 122,149 ----
;; A basic instruction type. Refinements due to arguments to be
;; provided in other attributes.
(define_attr "type"
! "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,sseadd,ssemul,ssediv,ssemov,ssecmp,ssecvt,sselog,sseiadd,sseishft,sseimul,mmx,mmxmov,mmxadd,mmxshft,mmxcmp,mmxcvt,mmxmul,fistp"
(const_string "other"))
;; Main data type used by the insn
! (define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI,V4SF,V2DF,V2SF"
(const_string "unknown"))
! ;; The CPU unit operations uses.
! (define_attr "unit" "integer,i387,sse,mmx,unknown"
! (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
! (const_string "i387")
! (eq_attr "type" "sse,sseadd,ssemul,ssediv,ssemov,ssecmp,ssecvt,sselog,sseiadd,sseishft,sseimul")
! (const_string "sse")
! (eq_attr "type" "mmx,mmxmov,mmxadd,mmxshft,mmxcmp,mmxcvt,mmxmul")
! (const_string "mmx")]
! (const_string "integer")))
;; The (bounding maximum) length of an instruction immediate.
(define_attr "length_immediate" ""
! (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv")
(const_int 0)
! (eq_attr "unit" "i387,sse,mmx")
(const_int 0)
(eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
(symbol_ref "ix86_attr_length_immediate_default(insn,1)")
***************
*** 178,193 ****
;; Set when length prefix is used.
(define_attr "prefix_data16" ""
! (if_then_else (eq_attr "mode" "HI")
(const_int 1)
(const_int 0)))
;; Set when string REP prefix is used.
! (define_attr "prefix_rep" "" (const_int 0))
;; Set when 0f opcode prefix is used.
(define_attr "prefix_0f" ""
! (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,mmx")
(const_int 1)
(const_int 0)))
--- 182,201 ----
;; Set when length prefix is used.
(define_attr "prefix_data16" ""
! (if_then_else (ior (eq_attr "mode" "HI")
! (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
(const_int 1)
(const_int 0)))
;; Set when string REP prefix is used.
! (define_attr "prefix_rep" ""
! (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
! (const_int 1)
! (const_int 0)))
;; Set when 0f opcode prefix is used.
(define_attr "prefix_0f" ""
! (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,sseadd,ssemul,ssediv,ssemov,ssecmp,ssecvt,sselog,sseiadd,sseishft,sseimul,mmx,mmxmov,mmxadd,mmxshft,mmxcmp,mmxcvt,mmxmul")
(const_int 1)
(const_int 0)))
***************
*** 195,201 ****
(define_attr "modrm" ""
(cond [(eq_attr "type" "str,cld")
(const_int 0)
! (eq_attr "i387" "1")
(const_int 0)
(and (eq_attr "type" "incdec")
(ior (match_operand:SI 1 "register_operand" "")
--- 203,209 ----
(define_attr "modrm" ""
(cond [(eq_attr "type" "str,cld")
(const_int 0)
! (eq_attr "unit" "i387")
(const_int 0)
(and (eq_attr "type" "incdec")
(ior (match_operand:SI 1 "register_operand" "")
***************
*** 220,230 ****
(define_attr "length" ""
(cond [(eq_attr "type" "other,multi,fistp")
(const_int 16)
! ]
(plus (plus (attr "modrm")
(plus (attr "prefix_0f")
! (plus (attr "i387")
! (const_int 1))))
(plus (attr "prefix_rep")
(plus (attr "prefix_data16")
(plus (attr "length_immediate")
--- 228,240 ----
(define_attr "length" ""
(cond [(eq_attr "type" "other,multi,fistp")
(const_int 16)
! (eq_attr "unit" "i387")
! (plus (const_int 2)
! (plus (attr "prefix_data16")
! (attr "length_address")))]
(plus (plus (attr "modrm")
(plus (attr "prefix_0f")
! (const_int 1)))
(plus (attr "prefix_rep")
(plus (attr "prefix_data16")
(plus (attr "length_immediate")
***************
*** 276,282 ****
(const_string "store")
(match_operand 1 "memory_operand" "")
(const_string "load")
! (and (eq_attr "type" "!icmp,test,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp,sse,mmx")
(match_operand 2 "memory_operand" ""))
(const_string "load")
(and (eq_attr "type" "icmov")
--- 286,292 ----
(const_string "store")
(match_operand 1 "memory_operand" "")
(const_string "load")
! (and (eq_attr "type" "!icmp,test,alu1,negnot,fsgn,imov,imovx,fmov,fcmp,sse,mmx,ssemov,mmxmov,ssecvt,mmxcvt")
(match_operand 2 "memory_operand" ""))
(const_string "load")
(and (eq_attr "type" "icmov")
***************
*** 524,532 ****
; integer instructions, because of the inpaired fxch instruction.
(define_function_unit "pent_np" 1 0
(and (eq_attr "cpu" "pentium")
! (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp,fistp"))
2 2
! [(eq_attr "type" "!fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp,fistp")])
(define_function_unit "fpu" 1 0
(and (eq_attr "cpu" "pentium")
--- 534,542 ----
; integer instructions, because of the inpaired fxch instruction.
(define_function_unit "pent_np" 1 0
(and (eq_attr "cpu" "pentium")
! (eq_attr "type" "fmov,fop,fsgn,fmul,fpspc,fcmov,fcmp,fistp"))
2 2
! [(eq_attr "type" "!fmov,fop,fsgn,fmul,fpspc,fcmov,fcmp,fistp")])
(define_function_unit "fpu" 1 0
(and (eq_attr "cpu" "pentium")
***************
*** 537,543 ****
; ??? Trivial fp operations such as fabs or fchs takes only one cycle.
(define_function_unit "fpu" 1 0
(and (eq_attr "cpu" "pentium")
! (eq_attr "type" "fop,fop1,fistp"))
3 1)
; Multiplication takes 3 cycles and is only half pipelined.
--- 547,553 ----
; ??? Trivial fp operations such as fabs or fchs takes only one cycle.
(define_function_unit "fpu" 1 0
(and (eq_attr "cpu" "pentium")
! (eq_attr "type" "fop,fistp"))
3 1)
; Multiplication takes 3 cycles and is only half pipelined.
***************
*** 635,641 ****
(define_function_unit "ppro_p0" 1 0
(and (eq_attr "cpu" "pentiumpro")
! (eq_attr "type" "fop,fop1,fsgn,fistp"))
3 1)
(define_function_unit "ppro_p0" 1 0
--- 645,651 ----
(define_function_unit "ppro_p0" 1 0
(and (eq_attr "cpu" "pentiumpro")
! (eq_attr "type" "fop,fsgn,fistp"))
3 1)
(define_function_unit "ppro_p0" 1 0
***************
*** 688,694 ****
(define_function_unit "fpu" 1 0
(and (eq_attr "cpu" "pentiumpro")
! (eq_attr "type" "fop,fop1,fsgn,fmov,fcmp,fcmov,fistp"))
1 1)
(define_function_unit "fpu" 1 0
--- 698,704 ----
(define_function_unit "fpu" 1 0
(and (eq_attr "cpu" "pentiumpro")
! (eq_attr "type" "fop,fsgn,fmov,fcmp,fcmov,fistp"))
1 1)
(define_function_unit "fpu" 1 0
***************
*** 791,797 ****
(define_function_unit "k6_fpu" 1 1
(and (eq_attr "cpu" "k6")
! (eq_attr "type" "fop,fop1,fmov,fcmp,fistp"))
2 2)
(define_function_unit "k6_fpu" 1 1
--- 801,807 ----
(define_function_unit "k6_fpu" 1 1
(and (eq_attr "cpu" "k6")
! (eq_attr "type" "fop,fmov,fcmp,fistp"))
2 2)
(define_function_unit "k6_fpu" 1 1
***************
*** 903,909 ****
42 42)
(define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
! (cond [(eq_attr "type" "fop,fop1,fcmp,fistp")
(const_string "add")
(eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
(const_string "mul")
--- 913,919 ----
42 42)
(define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
! (cond [(eq_attr "type" "fop,fcmp,fistp")
(const_string "add")
(eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
(const_string "mul")
***************
*** 938,944 ****
(define_function_unit "athlon_fp" 3 0
(and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fop,fop1,fmul,fistp"))
4 1)
;; XFmode loads are slow.
--- 948,954 ----
(define_function_unit "athlon_fp" 3 0
(and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fop,fmul,fistp"))
4 1)
;; XFmode loads are slow.
***************
*** 1558,1564 ****
"fnstsw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "SI")
! (set_attr "i387" "1")
(set_attr "ppro_uops" "few")])
;; FP compares, step 3
--- 1568,1574 ----
"fnstsw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "SI")
! (set_attr "unit" "i387")
(set_attr "ppro_uops" "few")])
;; FP compares, step 3
***************
*** 1597,1603 ****
&& SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[0])"
"* return output_fp_compare (insn, operands, 1, 0);"
! [(set_attr "type" "fcmp,sse")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
--- 1607,1613 ----
&& SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[0])"
"* return output_fp_compare (insn, operands, 1, 0);"
! [(set_attr "type" "fcmp,ssecmp")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
***************
*** 1608,1614 ****
"SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[0])"
"* return output_fp_compare (insn, operands, 1, 0);"
! [(set_attr "type" "sse")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
--- 1618,1624 ----
"SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[0])"
"* return output_fp_compare (insn, operands, 1, 0);"
! [(set_attr "type" "ssecmp")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
***************
*** 1633,1639 ****
&& SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 1);"
! [(set_attr "type" "fcmp,sse")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
--- 1643,1649 ----
&& SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 1);"
! [(set_attr "type" "fcmp,ssecmp")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
***************
*** 1644,1650 ****
"SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 1);"
! [(set_attr "type" "sse")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
\f
--- 1654,1660 ----
"SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 1);"
! [(set_attr "type" "ssecmp")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
\f
***************
*** 1772,1780 ****
}
[(set (attr "type")
(cond [(eq_attr "alternative" "4,5,6")
! (const_string "mmx")
(eq_attr "alternative" "7,8,9")
! (const_string "sse")
(and (ne (symbol_ref "flag_pic") (const_int 0))
(match_operand:SI 1 "symbolic_operand" ""))
(const_string "lea")
--- 1782,1790 ----
}
[(set (attr "type")
(cond [(eq_attr "alternative" "4,5,6")
! (const_string "mmxmov")
(eq_attr "alternative" "7,8,9")
! (const_string "ssemov")
(and (ne (symbol_ref "flag_pic") (const_int 0))
(match_operand:SI 1 "symbolic_operand" ""))
(const_string "lea")
***************
*** 2490,2496 ****
movq\t{%1, %0|%0, %1}
movdqa\t{%1, %0|%0, %1}
movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "*,*,mmx,mmx,sse,sse,sse")
(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
(define_split
--- 2500,2506 ----
movq\t{%1, %0|%0, %1}
movdqa\t{%1, %0|%0, %1}
movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
(define_split
***************
*** 2543,2551 ****
}
[(set (attr "type")
(cond [(eq_attr "alternative" "5,6")
! (const_string "mmx")
(eq_attr "alternative" "7,8")
! (const_string "sse")
(eq_attr "alternative" "4")
(const_string "multi")
(and (ne (symbol_ref "flag_pic") (const_int 0))
--- 2553,2561 ----
}
[(set (attr "type")
(cond [(eq_attr "alternative" "5,6")
! (const_string "mmxmov")
(eq_attr "alternative" "7,8")
! (const_string "ssemov")
(eq_attr "alternative" "4")
(const_string "multi")
(and (ne (symbol_ref "flag_pic") (const_int 0))
***************
*** 2794,2800 ****
abort();
}
}
! [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse,mmx,mmx,mmx")
(set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI,DI")])
(define_insn "*swapsf"
--- 2804,2810 ----
abort();
}
}
! [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
(set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI,DI")])
(define_insn "*swapsf"
***************
*** 2970,2976 ****
abort();
}
}
! [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
(set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
(define_insn "*movdf_integer"
--- 2980,2986 ----
abort();
}
}
! [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
(set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
(define_insn "*movdf_integer"
***************
*** 3029,3035 ****
abort();
}
}
! [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
(set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
(define_split
--- 3039,3045 ----
abort();
}
}
! [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
(set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
(define_split
***************
*** 4093,4099 ****
abort ();
}
}
! [(set_attr "type" "fmov,fmov,sse")
(set_attr "mode" "SF,XF,DF")])
(define_insn "*extendsfdf2_1_sse_only"
--- 4103,4109 ----
abort ();
}
}
! [(set_attr "type" "fmov,fmov,ssecvt")
(set_attr "mode" "SF,XF,DF")])
(define_insn "*extendsfdf2_1_sse_only"
***************
*** 4102,4108 ****
"!TARGET_80387 && TARGET_SSE2
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"cvtss2sd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
(set_attr "mode" "DF")])
(define_expand "extendsfxf2"
--- 4112,4118 ----
"!TARGET_80387 && TARGET_SSE2
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"cvtss2sd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
(set_attr "mode" "DF")])
(define_expand "extendsfxf2"
***************
*** 4332,4338 ****
abort ();
}
}
! [(set_attr "type" "fmov,multi,multi,multi,sse")
(set_attr "mode" "SF,SF,SF,SF,DF")])
(define_insn "*truncdfsf2_2"
--- 4342,4348 ----
abort ();
}
}
! [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
(set_attr "mode" "SF,SF,SF,SF,DF")])
(define_insn "*truncdfsf2_2"
***************
*** 4355,4361 ****
abort ();
}
}
! [(set_attr "type" "sse,fmov")
(set_attr "mode" "DF,SF")])
(define_insn "truncdfsf2_3"
--- 4365,4371 ----
abort ();
}
}
! [(set_attr "type" "ssecvt,fmov")
(set_attr "mode" "DF,SF")])
(define_insn "truncdfsf2_3"
***************
*** 4378,4384 ****
(match_operand:DF 1 "nonimmediate_operand" "mY")))]
"!TARGET_80387 && TARGET_SSE2"
"cvtsd2ss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
(set_attr "mode" "DF")])
(define_split
--- 4388,4394 ----
(match_operand:DF 1 "nonimmediate_operand" "mY")))]
"!TARGET_80387 && TARGET_SSE2"
"cvtsd2ss\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
(set_attr "mode" "DF")])
(define_split
***************
*** 4795,4808 ****
(fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
"TARGET_64BIT && TARGET_SSE"
"cvttss2si{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "fix_truncdfdi_sse"
[(set (match_operand:DI 0 "register_operand" "=r")
(fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
"TARGET_64BIT && TARGET_SSE2"
"cvttsd2si{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; Signed conversion to SImode.
--- 4805,4818 ----
(fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
"TARGET_64BIT && TARGET_SSE"
"cvttss2si{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")])
(define_insn "fix_truncdfdi_sse"
[(set (match_operand:DI 0 "register_operand" "=r")
(fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
"TARGET_64BIT && TARGET_SSE2"
"cvttsd2si{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")])
;; Signed conversion to SImode.
***************
*** 4903,4916 ****
(fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"cvttss2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "fix_truncdfsi_sse"
[(set (match_operand:SI 0 "register_operand" "=r")
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"cvttsd2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
--- 4913,4926 ----
(fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"cvttss2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")])
(define_insn "fix_truncdfsi_sse"
[(set (match_operand:SI 0 "register_operand" "=r")
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"cvttsd2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
***************
*** 5046,5052 ****
"fnstcw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "HI")
! (set_attr "i387" "1")
(set_attr "ppro_uops" "few")])
(define_insn "x86_fldcw_1"
--- 5056,5062 ----
"fnstcw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "HI")
! (set_attr "unit" "i387")
(set_attr "ppro_uops" "few")])
(define_insn "x86_fldcw_1"
***************
*** 5056,5062 ****
"fldcw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "HI")
! (set_attr "i387" "1")
(set_attr "athlon_decode" "vector")
(set_attr "ppro_uops" "few")])
\f
--- 5066,5072 ----
"fldcw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "HI")
! (set_attr "unit" "i387")
(set_attr "athlon_decode" "vector")
(set_attr "ppro_uops" "few")])
\f
***************
*** 5090,5096 ****
fild%z1\t%1
#
cvtsi2ss\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,sse")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
--- 5100,5106 ----
fild%z1\t%1
#
cvtsi2ss\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,ssecvt")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
***************
*** 5099,5105 ****
(float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE"
"cvtsi2ss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
--- 5109,5115 ----
(float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE"
"cvtsi2ss\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
***************
*** 5128,5134 ****
fild%z1\t%1
#
cvtsi2ss{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,sse")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
--- 5138,5144 ----
fild%z1\t%1
#
cvtsi2ss{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,ssecvt")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
***************
*** 5137,5143 ****
(float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
"TARGET_64BIT && TARGET_SSE"
"cvtsi2ss{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
--- 5147,5153 ----
(float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
"TARGET_64BIT && TARGET_SSE"
"cvtsi2ss{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
***************
*** 5166,5172 ****
fild%z1\t%1
#
cvtsi2sd\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,sse")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
--- 5176,5182 ----
fild%z1\t%1
#
cvtsi2sd\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,ssecvt")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
***************
*** 5175,5181 ****
(float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE2"
"cvtsi2sd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
--- 5185,5191 ----
(float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE2"
"cvtsi2sd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
***************
*** 5204,5210 ****
fild%z1\t%1
#
cvtsi2sd{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,sse")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
--- 5214,5220 ----
fild%z1\t%1
#
cvtsi2sd{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,ssecvt")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
***************
*** 5213,5219 ****
(float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE2"
"cvtsi2sd{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
--- 5223,5229 ----
(float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE2"
"cvtsi2sd{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
***************
*** 12788,12794 ****
(match_operand:SF 3 "nonimmediate_operand" "xm")]))]
"TARGET_SSE && reload_completed"
"cmp%D1ss\t{%3, %0|%0, %3}"
! [(set_attr "type" "sse")
(set_attr "mode" "SF")])
(define_insn "*sse_setccdf"
--- 12798,12804 ----
(match_operand:SF 3 "nonimmediate_operand" "xm")]))]
"TARGET_SSE && reload_completed"
"cmp%D1ss\t{%3, %0|%0, %3}"
! [(set_attr "type" "ssecmp")
(set_attr "mode" "SF")])
(define_insn "*sse_setccdf"
***************
*** 12798,12804 ****
(match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
"TARGET_SSE2 && reload_completed"
"cmp%D1sd\t{%3, %0|%0, %3}"
! [(set_attr "type" "sse")
(set_attr "mode" "DF")])
\f
;; Basic conditional jump instructions.
--- 12808,12814 ----
(match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
"TARGET_SSE2 && reload_completed"
"cmp%D1sd\t{%3, %0|%0, %3}"
! [(set_attr "type" "ssecmp")
(set_attr "mode" "DF")])
\f
;; Basic conditional jump instructions.
***************
*** 14030,14036 ****
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(if_then_else (eq_attr "alternative" "1")
! (const_string "sse")
(if_then_else (match_operand:SF 3 "mult_operator" "")
(const_string "fmul")
(const_string "fop"))))
--- 14040,14048 ----
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(if_then_else (eq_attr "alternative" "1")
! (if_then_else (match_operand:SF 3 "mult_operator" "")
! (const_string "ssemul")
! (const_string "sseadd"))
(if_then_else (match_operand:SF 3 "mult_operator" "")
(const_string "fmul")
(const_string "fop"))))
***************
*** 14044,14050 ****
"TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
! [(set_attr "type" "sse")
(set_attr "mode" "SF")])
(define_insn "*fop_df_comm_nosse"
--- 14056,14065 ----
"TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
! [(set (attr "type")
! (if_then_else (match_operand:SF 3 "mult_operator" "")
! (const_string "ssemul")
! (const_string "sseadd")))
(set_attr "mode" "SF")])
(define_insn "*fop_df_comm_nosse"
***************
*** 14073,14079 ****
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(if_then_else (eq_attr "alternative" "1")
! (const_string "sse")
(if_then_else (match_operand:SF 3 "mult_operator" "")
(const_string "fmul")
(const_string "fop"))))
--- 14088,14096 ----
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(if_then_else (eq_attr "alternative" "1")
! (if_then_else (match_operand:SF 3 "mult_operator" "")
! (const_string "ssemul")
! (const_string "sseadd"))
(if_then_else (match_operand:SF 3 "mult_operator" "")
(const_string "fmul")
(const_string "fop"))))
***************
*** 14088,14094 ****
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
! [(set_attr "type" "sse")
(set_attr "mode" "DF")])
(define_insn "*fop_xf_comm"
--- 14105,14114 ----
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
! [(set (attr "type")
! (if_then_else (match_operand:SF 3 "mult_operator" "")
! (const_string "ssemul")
! (const_string "sseadd")))
(set_attr "mode" "DF")])
(define_insn "*fop_xf_comm"
***************
*** 14146,14153 ****
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
! (cond [(eq_attr "alternative" "2")
! (const_string "sse")
(match_operand:SF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:SF 3 "div_operator" "")
--- 14166,14179 ----
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
! (cond [(and (eq_attr "alternative" "2")
! (match_operand:SF 3 "mult_operator" ""))
! (const_string "ssemul")
! (and (eq_attr "alternative" "2")
! (match_operand:SF 3 "div_operator" ""))
! (const_string "ssediv")
! (eq_attr "alternative" "2")
! (const_string "sseadd")
(match_operand:SF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:SF 3 "div_operator" "")
***************
*** 14164,14170 ****
"TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
! [(set_attr "type" "sse")
(set_attr "mode" "SF")])
;; ??? Add SSE splitters for these!
--- 14190,14202 ----
"TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
! [(set (attr "type")
! (cond [(match_operand:SF 3 "mult_operator" "")
! (const_string "ssemul")
! (match_operand:SF 3 "div_operator" "")
! (const_string "ssediv")
! ]
! (const_string "sseadd")))
(set_attr "mode" "SF")])
;; ??? Add SSE splitters for these!
***************
*** 14216,14222 ****
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
(const_string "fmul")
! (match_operand:DF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
--- 14248,14254 ----
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
(const_string "fmul")
! (match_operand:DF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
***************
*** 14233,14240 ****
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
! (cond [(eq_attr "alternative" "2")
! (const_string "sse")
(match_operand:DF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:DF 3 "div_operator" "")
--- 14265,14278 ----
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
! (cond [(and (eq_attr "alternative" "2")
! (match_operand:SF 3 "mult_operator" ""))
! (const_string "ssemul")
! (and (eq_attr "alternative" "2")
! (match_operand:SF 3 "div_operator" ""))
! (const_string "ssediv")
! (eq_attr "alternative" "2")
! (const_string "sseadd")
(match_operand:DF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:DF 3 "div_operator" "")
***************
*** 14251,14257 ****
"TARGET_SSE2 && TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
! [(set_attr "type" "sse")])
;; ??? Add SSE splitters for these!
(define_insn "*fop_df_2"
--- 14289,14302 ----
"TARGET_SSE2 && TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
! [(set_attr "mode" "DF")
! (set (attr "type")
! (cond [(match_operand:SF 3 "mult_operator" "")
! (const_string "ssemul")
! (match_operand:SF 3 "div_operator" "")
! (const_string "ssediv")
! ]
! (const_string "sseadd")))])
;; ??? Add SSE splitters for these!
(define_insn "*fop_df_2"
***************
*** 17852,17858 ****
"TARGET_SSE"
;; @@@ let's try to use movaps here.
"movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "movv4si_internal"
[(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
--- 17897,17904 ----
"TARGET_SSE"
;; @@@ let's try to use movaps here.
"movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "V4SF")])
(define_insn "movv4si_internal"
[(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
***************
*** 17860,17894 ****
"TARGET_SSE"
;; @@@ let's try to use movaps here.
"movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "movv8qi_internal"
[(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
(match_operand:V8QI 1 "nonimmediate_operand" "ym,y"))]
"TARGET_MMX"
"movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "movv4hi_internal"
[(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
(match_operand:V4HI 1 "nonimmediate_operand" "ym,y"))]
"TARGET_MMX"
"movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "movv2si_internal"
[(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
(match_operand:V2SI 1 "nonimmediate_operand" "ym,y"))]
"TARGET_MMX"
"movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "movv2sf_internal"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,m")
(match_operand:V2SF 1 "nonimmediate_operand" "ym,y"))]
"TARGET_3DNOW"
"movq\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_expand "movti"
[(set (match_operand:TI 0 "general_operand" "")
--- 17906,17945 ----
"TARGET_SSE"
;; @@@ let's try to use movaps here.
"movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "V4SF")])
(define_insn "movv8qi_internal"
[(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
(match_operand:V8QI 1 "nonimmediate_operand" "ym,y"))]
"TARGET_MMX"
"movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxmov")
! (set_attr "mode" "DI")])
(define_insn "movv4hi_internal"
[(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
(match_operand:V4HI 1 "nonimmediate_operand" "ym,y"))]
"TARGET_MMX"
"movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxmov")
! (set_attr "mode" "DI")])
(define_insn "movv2si_internal"
[(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
(match_operand:V2SI 1 "nonimmediate_operand" "ym,y"))]
"TARGET_MMX"
"movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "movv2sf_internal"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,m")
(match_operand:V2SF 1 "nonimmediate_operand" "ym,y"))]
"TARGET_3DNOW"
"movq\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_expand "movti"
[(set (match_operand:TI 0 "general_operand" "")
***************
*** 17908,17914 ****
"TARGET_SSE2"
;; @@@ let's try to use movaps here.
"movapd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "movv8hi_internal"
[(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m")
--- 17959,17966 ----
"TARGET_SSE2"
;; @@@ let's try to use movaps here.
"movapd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "V2DF")])
(define_insn "movv8hi_internal"
[(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m")
***************
*** 17916,17922 ****
"TARGET_SSE2"
;; @@@ let's try to use movaps here.
"movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "movv16qi_internal"
[(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
--- 17968,17975 ----
"TARGET_SSE2"
;; @@@ let's try to use movaps here.
"movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "V4SF")])
(define_insn "movv16qi_internal"
[(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
***************
*** 17924,17930 ****
"TARGET_SSE2"
;; @@@ let's try to use movaps here.
"movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_expand "movv2df"
[(set (match_operand:V2DF 0 "general_operand" "")
--- 17977,17984 ----
"TARGET_SSE2"
;; @@@ let's try to use movaps here.
"movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "V4SF")])
(define_expand "movv2df"
[(set (match_operand:V2DF 0 "general_operand" "")
***************
*** 18016,18022 ****
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:TI (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "sse")])
(define_insn_and_split "*pushv2df"
[(set (match_operand:V2DF 0 "push_operand" "=<")
--- 18070,18076 ----
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:TI (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "multi")])
(define_insn_and_split "*pushv2df"
[(set (match_operand:V2DF 0 "push_operand" "=<")
***************
*** 18027,18033 ****
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V2DF (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "sse")])
(define_insn_and_split "*pushv8hi"
[(set (match_operand:V8HI 0 "push_operand" "=<")
--- 18081,18087 ----
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V2DF (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "multi")])
(define_insn_and_split "*pushv8hi"
[(set (match_operand:V8HI 0 "push_operand" "=<")
***************
*** 18038,18044 ****
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V8HI (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "sse")])
(define_insn_and_split "*pushv16qi"
[(set (match_operand:V16QI 0 "push_operand" "=<")
--- 18092,18098 ----
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V8HI (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "multi")])
(define_insn_and_split "*pushv16qi"
[(set (match_operand:V16QI 0 "push_operand" "=<")
***************
*** 18049,18055 ****
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V16QI (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "sse")])
(define_insn_and_split "*pushv4sf"
[(set (match_operand:V4SF 0 "push_operand" "=<")
--- 18103,18109 ----
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V16QI (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "multi")])
(define_insn_and_split "*pushv4sf"
[(set (match_operand:V4SF 0 "push_operand" "=<")
***************
*** 18060,18066 ****
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V4SF (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "sse")])
(define_insn_and_split "*pushv4si"
[(set (match_operand:V4SI 0 "push_operand" "=<")
--- 18114,18120 ----
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V4SF (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "multi")])
(define_insn_and_split "*pushv4si"
[(set (match_operand:V4SI 0 "push_operand" "=<")
***************
*** 18071,18077 ****
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V4SI (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "sse")])
(define_insn_and_split "*pushv2si"
[(set (match_operand:V2SI 0 "push_operand" "=<")
--- 18125,18131 ----
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V4SI (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "multi")])
(define_insn_and_split "*pushv2si"
[(set (match_operand:V2SI 0 "push_operand" "=<")
***************
*** 18125,18131 ****
xorps\t%0, %0
movaps\t{%1, %0|%0, %1}
movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "*movti_rex64"
[(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,mx,x")
--- 18179,18186 ----
xorps\t%0, %0
movaps\t{%1, %0|%0, %1}
movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov,ssemov,ssemov")
! (set_attr "mode" "V4SF")])
(define_insn "*movti_rex64"
[(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,mx,x")
***************
*** 18138,18145 ****
xorps\t%0, %0
movaps\\t{%1, %0|%0, %1}
movaps\\t{%1, %0|%0, %1}"
! [(set_attr "type" "*,*,sse,sse,sse")
! (set_attr "mode" "TI")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
--- 18193,18200 ----
xorps\t%0, %0
movaps\\t{%1, %0|%0, %1}
movaps\\t{%1, %0|%0, %1}"
! [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
! (set_attr "mode" "V4SF")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
***************
*** 18159,18165 ****
"@
movaps\t{%1, %0|%0, %1}
movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse_movups"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
--- 18214,18221 ----
"@
movaps\t{%1, %0|%0, %1}
movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov,ssemov")
! (set_attr "mode" "V4SF")])
(define_insn "sse_movups"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
***************
*** 18169,18175 ****
"@
movups\t{%1, %0|%0, %1}
movups\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; SSE Strange Moves.
--- 18225,18232 ----
"@
movups\t{%1, %0|%0, %1}
movups\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt,ssecvt")
! (set_attr "mode" "V4SF")])
;; SSE Strange Moves.
***************
*** 18179,18192 ****
(unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
"TARGET_SSE"
"movmskps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "mmx_pmovmskb"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmovmskb\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "mmx_maskmovq"
[(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
--- 18236,18252 ----
(unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
"TARGET_SSE"
"movmskps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "mmx_pmovmskb"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmovmskb\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
!
(define_insn "mmx_maskmovq"
[(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
***************
*** 18195,18201 ****
"(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}"
! [(set_attr "type" "sse")])
(define_insn "mmx_maskmovq_rex"
[(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
--- 18255,18262 ----
"(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_maskmovq_rex"
[(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
***************
*** 18204,18224 ****
"(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_movntv4sf"
[(set (match_operand:V4SF 0 "memory_operand" "=m")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
"TARGET_SSE"
"movntps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse_movntdi"
[(set (match_operand:DI 0 "memory_operand" "=m")
(unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
"TARGET_SSE || TARGET_3DNOW_A"
"movntq\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse_movhlps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18265,18288 ----
"(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "sse_movntv4sf"
[(set (match_operand:V4SF 0 "memory_operand" "=m")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
"TARGET_SSE"
"movntps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "V4SF")])
(define_insn "sse_movntdi"
[(set (match_operand:DI 0 "memory_operand" "=m")
(unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
"TARGET_SSE || TARGET_3DNOW_A"
"movntq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxmov")
! (set_attr "mode" "DI")])
(define_insn "sse_movhlps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18232,18238 ****
(const_int 3)))]
"TARGET_SSE"
"movhlps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_movlhps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18296,18303 ----
(const_int 3)))]
"TARGET_SSE"
"movhlps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "sse_movlhps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18246,18252 ****
(const_int 12)))]
"TARGET_SSE"
"movlhps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_movhps"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
--- 18311,18318 ----
(const_int 12)))]
"TARGET_SSE"
"movlhps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "sse_movhps"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
***************
*** 18257,18263 ****
"TARGET_SSE
&& (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
"movhps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_movlps"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
--- 18323,18330 ----
"TARGET_SSE
&& (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
"movhps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "sse_movlps"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
***************
*** 18268,18274 ****
"TARGET_SSE
&& (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
"movlps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_loadss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18335,18342 ----
"TARGET_SSE
&& (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
"movlps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "sse_loadss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18278,18284 ****
(const_int 1)))]
"TARGET_SSE"
"movss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse_movss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18346,18353 ----
(const_int 1)))]
"TARGET_SSE"
"movss\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "SF")])
(define_insn "sse_movss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18288,18294 ****
(const_int 1)))]
"TARGET_SSE"
"movss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_storess"
[(set (match_operand:SF 0 "memory_operand" "=m")
--- 18357,18364 ----
(const_int 1)))]
"TARGET_SSE"
"movss\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "SF")])
(define_insn "sse_storess"
[(set (match_operand:SF 0 "memory_operand" "=m")
***************
*** 18297,18303 ****
(parallel [(const_int 0)])))]
"TARGET_SSE"
"movss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse_shufps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18367,18374 ----
(parallel [(const_int 0)])))]
"TARGET_SSE"
"movss\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "SF")])
(define_insn "sse_shufps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18307,18313 ****
"TARGET_SSE"
;; @@@ check operand order for intel/nonintel syntax
"shufps\t{%3, %2, %0|%0, %2, %3}"
! [(set_attr "type" "sse")])
;; SSE arithmetic
--- 18378,18385 ----
"TARGET_SSE"
;; @@@ check operand order for intel/nonintel syntax
"shufps\t{%3, %2, %0|%0, %2, %3}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
;; SSE arithmetic
***************
*** 18318,18324 ****
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"addps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmaddv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18390,18397 ----
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"addps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "V4SF")])
(define_insn "vmaddv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18329,18335 ****
(const_int 1)))]
"TARGET_SSE"
"addss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "subv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18402,18409 ----
(const_int 1)))]
"TARGET_SSE"
"addss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "SF")])
(define_insn "subv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18337,18343 ****
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"subps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmsubv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18411,18418 ----
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"subps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "V4SF")])
(define_insn "vmsubv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18348,18354 ****
(const_int 1)))]
"TARGET_SSE"
"subss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "mulv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18423,18430 ----
(const_int 1)))]
"TARGET_SSE"
"subss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "SF")])
(define_insn "mulv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18356,18362 ****
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"mulps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmmulv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18432,18439 ----
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"mulps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssemul")
! (set_attr "mode" "V4SF")])
(define_insn "vmmulv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18367,18373 ****
(const_int 1)))]
"TARGET_SSE"
"mulss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "divv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18444,18451 ----
(const_int 1)))]
"TARGET_SSE"
"mulss\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssemul")
! (set_attr "mode" "SF")])
(define_insn "divv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18375,18381 ****
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"divps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmdivv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18453,18460 ----
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"divps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssediv")
! (set_attr "mode" "V4SF")])
(define_insn "vmdivv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18386,18392 ****
(const_int 1)))]
"TARGET_SSE"
"divss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; SSE square root/reciprocal
--- 18465,18472 ----
(const_int 1)))]
"TARGET_SSE"
"divss\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssediv")
! (set_attr "mode" "SF")])
;; SSE square root/reciprocal
***************
*** 18397,18403 ****
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 42))]
"TARGET_SSE"
"rcpps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "vmrcpv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18477,18484 ----
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 42))]
"TARGET_SSE"
"rcpps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "V4SF")])
(define_insn "vmrcpv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18407,18413 ****
(const_int 1)))]
"TARGET_SSE"
"rcpss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "rsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18488,18495 ----
(const_int 1)))]
"TARGET_SSE"
"rcpss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "SF")])
(define_insn "rsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18415,18421 ****
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 43))]
"TARGET_SSE"
"rsqrtps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "vmrsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18497,18504 ----
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 43))]
"TARGET_SSE"
"rsqrtps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "V4SF")])
(define_insn "vmrsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18425,18438 ****
(const_int 1)))]
"TARGET_SSE"
"rsqrtss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"sqrtps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "vmsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18508,18523 ----
(const_int 1)))]
"TARGET_SSE"
"rsqrtss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "SF")])
(define_insn "sqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"sqrtps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "V4SF")])
(define_insn "vmsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18442,18448 ****
(const_int 1)))]
"TARGET_SSE"
"sqrtss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; SSE logical operations.
--- 18527,18534 ----
(const_int 1)))]
"TARGET_SSE"
"sqrtss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "SF")])
;; SSE logical operations.
***************
*** 18457,18463 ****
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
"andpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_andti3_df_2"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 18543,18550 ----
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
"andpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_andti3_df_2"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18465,18471 ****
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"andpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_andti3_sf_1"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 18552,18559 ----
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"andpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_andti3_sf_1"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18473,18479 ****
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
"andps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_andti3_sf_2"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 18561,18568 ----
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
"andps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "*sse_andti3_sf_2"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18481,18487 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"andps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_andti3"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 18570,18577 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"andps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "sse_andti3"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18490,18496 ****
"TARGET_SSE && !TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"andps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_andti3"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 18580,18587 ----
"TARGET_SSE && !TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"andps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "sse2_andti3"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18499,18505 ****
"TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"pand\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_nandti3_df"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 18590,18597 ----
"TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"pand\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "TI")])
(define_insn "*sse_nandti3_df"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18507,18513 ****
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"andnpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_nandti3_sf"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 18599,18606 ----
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"andnpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_nandti3_sf"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18515,18521 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"andnps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_nandti3"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 18608,18615 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"andnps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "sse_nandti3"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18523,18529 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
"andnps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_nandti3"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 18617,18624 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
"andnps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "sse2_nandti3"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18531,18537 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pandn\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_iorti3_df_1"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 18626,18632 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pandn\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")])
(define_insn "*sse_iorti3_df_1"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18539,18545 ****
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
"orpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_iorti3_df_2"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 18634,18641 ----
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
"orpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_iorti3_df_2"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18547,18553 ****
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"orpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_iorti3_sf_1"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 18643,18650 ----
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"orpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_iorti3_sf_1"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18555,18561 ****
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
"orps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_iorti3_sf_2"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 18652,18659 ----
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
"orps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "*sse_iorti3_sf_2"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18563,18569 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"orps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_iorti3"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 18661,18668 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"orps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "sse_iorti3"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18572,18578 ****
"TARGET_SSE && !TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"orps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_iorti3"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 18671,18678 ----
"TARGET_SSE && !TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"orps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "sse2_iorti3"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18581,18587 ****
"TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"por\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_xorti3_df_1"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 18681,18688 ----
"TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"por\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "TI")])
(define_insn "*sse_xorti3_df_1"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18589,18595 ****
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
"xorpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_xorti3_df_2"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 18690,18697 ----
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
"xorpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_xorti3_df_2"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18597,18603 ****
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"xorpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_xorti3_sf_1"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 18699,18706 ----
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"xorpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_xorti3_sf_1"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18605,18611 ****
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
"xorps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_xorti3_sf_2"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 18708,18715 ----
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
"xorps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "*sse_xorti3_sf_2"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18613,18619 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"xorps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_xorti3"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 18717,18724 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"xorps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "sse_xorti3"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18622,18628 ****
"TARGET_SSE && !TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"xorps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_xorti3"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 18727,18734 ----
"TARGET_SSE && !TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"xorps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "sse2_xorti3"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18631,18637 ****
"TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"pxor\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; Use xor, but don't show input operands so they aren't live before
;; this insn.
--- 18737,18744 ----
"TARGET_SSE2
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"pxor\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "TI")])
;; Use xor, but don't show input operands so they aren't live before
;; this insn.
***************
*** 18640,18647 ****
(unspec:V4SF [(const_int 0)] 45))]
"TARGET_SSE"
"xorps\t{%0, %0|%0, %0}"
! [(set_attr "type" "sse")
! (set_attr "memory" "none")])
;; SSE mask-generating compares
--- 18747,18754 ----
(unspec:V4SF [(const_int 0)] 45))]
"TARGET_SSE"
"xorps\t{%0, %0|%0, %0}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
;; SSE mask-generating compares
***************
*** 18652,18658 ****
(match_operand:V4SF 2 "register_operand" "x")]))]
"TARGET_SSE"
"cmp%D3ps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "maskncmpv4sf3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 18759,18766 ----
(match_operand:V4SF 2 "register_operand" "x")]))]
"TARGET_SSE"
"cmp%D3ps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "V4SF")])
(define_insn "maskncmpv4sf3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 18667,18673 ****
else
return "cmpn%D3ps\t{%2, %0|%0, %2}";
}
! [(set_attr "type" "sse")])
(define_insn "vmmaskcmpv4sf3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 18775,18782 ----
else
return "cmpn%D3ps\t{%2, %0|%0, %2}";
}
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "V4SF")])
(define_insn "vmmaskcmpv4sf3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 18679,18685 ****
(const_int 1)))]
"TARGET_SSE"
"cmp%D3ss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmmaskncmpv4sf3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 18788,18795 ----
(const_int 1)))]
"TARGET_SSE"
"cmp%D3ss\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "SF")])
(define_insn "vmmaskncmpv4sf3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 18697,18703 ****
else
return "cmpn%D3ss\t{%2, %0|%0, %2}";
}
! [(set_attr "type" "sse")])
(define_insn "sse_comi"
[(set (reg:CCFP 17)
--- 18807,18814 ----
else
return "cmpn%D3ss\t{%2, %0|%0, %2}";
}
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "SF")])
(define_insn "sse_comi"
[(set (reg:CCFP 17)
***************
*** 18710,18716 ****
(parallel [(const_int 0)]))]))]
"TARGET_SSE"
"comiss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse_ucomi"
[(set (reg:CCFPU 17)
--- 18821,18828 ----
(parallel [(const_int 0)]))]))]
"TARGET_SSE"
"comiss\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "SF")])
(define_insn "sse_ucomi"
[(set (reg:CCFPU 17)
***************
*** 18723,18729 ****
(parallel [(const_int 0)]))]))]
"TARGET_SSE"
"ucomiss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; SSE unpack
--- 18835,18842 ----
(parallel [(const_int 0)]))]))]
"TARGET_SSE"
"ucomiss\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "SF")])
;; SSE unpack
***************
*** 18744,18750 ****
(const_int 5)))]
"TARGET_SSE"
"unpckhps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_unpcklps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18857,18864 ----
(const_int 5)))]
"TARGET_SSE"
"unpckhps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "sse_unpcklps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18762,18768 ****
(const_int 5)))]
"TARGET_SSE"
"unpcklps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; SSE min/max
--- 18876,18883 ----
(const_int 5)))]
"TARGET_SSE"
"unpcklps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
;; SSE min/max
***************
*** 18773,18779 ****
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"maxps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmsmaxv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18888,18895 ----
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"maxps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")
! (set_attr "mode" "V4SF")])
(define_insn "vmsmaxv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18784,18790 ****
(const_int 1)))]
"TARGET_SSE"
"maxss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sminv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18900,18907 ----
(const_int 1)))]
"TARGET_SSE"
"maxss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")
! (set_attr "mode" "SF")])
(define_insn "sminv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18792,18798 ****
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"minps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmsminv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18909,18916 ----
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"minps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")
! (set_attr "mode" "V4SF")])
(define_insn "vmsminv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18803,18809 ****
(const_int 1)))]
"TARGET_SSE"
"minss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; SSE <-> integer/MMX conversions
--- 18921,18928 ----
(const_int 1)))]
"TARGET_SSE"
"minss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")
! (set_attr "mode" "SF")])
;; SSE <-> integer/MMX conversions
***************
*** 18817,18823 ****
(const_int 12)))]
"TARGET_SSE"
"cvtpi2ps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "cvtps2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 18936,18943 ----
(const_int 12)))]
"TARGET_SSE"
"cvtpi2ps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "cvtps2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 18826,18832 ****
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_SSE"
"cvtps2pi\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvttps2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 18946,18953 ----
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_SSE"
"cvtps2pi\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "cvttps2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 18835,18841 ****
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_SSE"
"cvttps2pi\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvtsi2ss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18956,18963 ----
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_SSE"
"cvttps2pi\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "SF")])
(define_insn "cvtsi2ss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18846,18852 ****
(const_int 14)))]
"TARGET_SSE"
"cvtsi2ss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "cvtss2si"
[(set (match_operand:SI 0 "register_operand" "=r")
--- 18968,18975 ----
(const_int 14)))]
"TARGET_SSE"
"cvtsi2ss\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "SF")])
(define_insn "cvtss2si"
[(set (match_operand:SI 0 "register_operand" "=r")
***************
*** 18855,18861 ****
(parallel [(const_int 0)])))]
"TARGET_SSE"
"cvtss2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvttss2si"
[(set (match_operand:SI 0 "register_operand" "=r")
--- 18978,18985 ----
(parallel [(const_int 0)])))]
"TARGET_SSE"
"cvtss2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "SF")])
(define_insn "cvttss2si"
[(set (match_operand:SI 0 "register_operand" "=r")
***************
*** 18864,18870 ****
(parallel [(const_int 0)])))]
"TARGET_SSE"
"cvttss2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; MMX insns
--- 18988,18995 ----
(parallel [(const_int 0)])))]
"TARGET_SSE"
"cvttss2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "SF")])
;; MMX insns
***************
*** 18877,18883 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "addv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19002,19009 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "addv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18885,18891 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "addv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19011,19018 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "addv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 18893,18899 ****
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ssaddv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19020,19027 ----
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "ssaddv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 18901,18907 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddsb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ssaddv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19029,19036 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddsb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "ssaddv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18909,18915 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "usaddv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19038,19045 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "usaddv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 18917,18923 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddusb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "usaddv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19047,19054 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddusb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "usaddv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18925,18931 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddusw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "subv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19056,19063 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddusw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "subv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 18933,18939 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "subv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19065,19072 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "subv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18941,18947 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "subv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19074,19081 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "subv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 18949,18955 ****
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "sssubv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19083,19090 ----
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "sssubv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 18957,18963 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubsb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "sssubv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19092,19099 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubsb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "sssubv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18965,18971 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ussubv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19101,19108 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "ussubv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 18973,18979 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubusb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ussubv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19110,19117 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubusb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "ussubv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18981,18987 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubusw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mulv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19119,19126 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubusw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "mulv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18989,18995 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pmullw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "smulv4hi3_highpart"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19128,19135 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pmullw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxmul")
! (set_attr "mode" "DI")])
(define_insn "smulv4hi3_highpart"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19002,19008 ****
(const_int 16))))]
"TARGET_MMX"
"pmulhw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "umulv4hi3_highpart"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19142,19149 ----
(const_int 16))))]
"TARGET_MMX"
"pmulhw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxmul")
! (set_attr "mode" "DI")])
(define_insn "umulv4hi3_highpart"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19015,19021 ****
(const_int 16))))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmulhuw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_pmaddwd"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19156,19163 ----
(const_int 16))))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmulhuw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxmul")
! (set_attr "mode" "DI")])
(define_insn "mmx_pmaddwd"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19036,19042 ****
(const_int 3)]))))))]
"TARGET_MMX"
"pmaddwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; MMX logical operations
--- 19178,19185 ----
(const_int 3)]))))))]
"TARGET_MMX"
"pmaddwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxmul")
! (set_attr "mode" "DI")])
;; MMX logical operations
***************
*** 19050,19056 ****
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"por\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_xordi3"
[(set (match_operand:DI 0 "register_operand" "=y")
--- 19193,19200 ----
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"por\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "mmx_xordi3"
[(set (match_operand:DI 0 "register_operand" "=y")
***************
*** 19059,19065 ****
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"pxor\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")
(set_attr "memory" "none")])
;; Same as pxor, but don't show input operands so that we don't think
--- 19203,19210 ----
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"pxor\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")
(set_attr "memory" "none")])
;; Same as pxor, but don't show input operands so that we don't think
***************
*** 19069,19075 ****
(unspec:DI [(const_int 0)] 45))]
"TARGET_MMX"
"pxor\t{%0, %0|%0, %0}"
! [(set_attr "type" "mmx")
(set_attr "memory" "none")])
(define_insn "mmx_anddi3"
--- 19214,19221 ----
(unspec:DI [(const_int 0)] 45))]
"TARGET_MMX"
"pxor\t{%0, %0|%0, %0}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")
(set_attr "memory" "none")])
(define_insn "mmx_anddi3"
***************
*** 19079,19085 ****
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"pand\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_nanddi3"
[(set (match_operand:DI 0 "register_operand" "=y")
--- 19225,19232 ----
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"pand\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "mmx_nanddi3"
[(set (match_operand:DI 0 "register_operand" "=y")
***************
*** 19088,19094 ****
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"pandn\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; MMX unsigned averages/sum of absolute differences
--- 19235,19242 ----
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"pandn\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
;; MMX unsigned averages/sum of absolute differences
***************
*** 19110,19116 ****
(const_int 1)))]
"TARGET_SSE || TARGET_3DNOW_A"
"pavgb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "mmx_uavgv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19258,19265 ----
(const_int 1)))]
"TARGET_SSE || TARGET_3DNOW_A"
"pavgb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "mmx_uavgv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19125,19131 ****
(const_int 1)))]
"TARGET_SSE || TARGET_3DNOW_A"
"pavgw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "mmx_psadbw"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19274,19281 ----
(const_int 1)))]
"TARGET_SSE || TARGET_3DNOW_A"
"pavgw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "mmx_psadbw"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 19133,19139 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
"TARGET_SSE || TARGET_3DNOW_A"
"psadbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; MMX insert/extract/shuffle
--- 19283,19290 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
"TARGET_SSE || TARGET_3DNOW_A"
"psadbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
;; MMX insert/extract/shuffle
***************
*** 19146,19152 ****
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pinsrw\t{%3, %2, %0|%0, %2, %3}"
! [(set_attr "type" "sse")])
(define_insn "mmx_pextrw"
[(set (match_operand:SI 0 "register_operand" "=r")
--- 19297,19304 ----
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pinsrw\t{%3, %2, %0|%0, %2, %3}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_pextrw"
[(set (match_operand:SI 0 "register_operand" "=r")
***************
*** 19155,19161 ****
[(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SSE || TARGET_3DNOW_A"
"pextrw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "sse")])
(define_insn "mmx_pshufw"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19307,19314 ----
[(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SSE || TARGET_3DNOW_A"
"pextrw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_pshufw"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19163,19169 ****
(match_operand:SI 2 "immediate_operand" "i")] 41))]
"TARGET_SSE || TARGET_3DNOW_A"
"pshufw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "sse")])
;; MMX mask-generating comparisons
--- 19316,19323 ----
(match_operand:SI 2 "immediate_operand" "i")] 41))]
"TARGET_SSE || TARGET_3DNOW_A"
"pshufw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
;; MMX mask-generating comparisons
***************
*** 19174,19180 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpeqb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "eqv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19328,19335 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpeqb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "DI")])
(define_insn "eqv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19182,19188 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpeqw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "eqv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19337,19344 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpeqw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "DI")])
(define_insn "eqv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19190,19196 ****
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpeqd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "gtv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19346,19353 ----
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpeqd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "DI")])
(define_insn "gtv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 19198,19204 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpgtb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "gtv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19355,19362 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpgtb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "DI")])
(define_insn "gtv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19206,19212 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpgtw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "gtv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19364,19371 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpgtw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "DI")])
(define_insn "gtv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19214,19220 ****
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpgtd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; MMX max/min insns
--- 19373,19380 ----
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpgtd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "DI")])
;; MMX max/min insns
***************
*** 19225,19231 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmaxub\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "smaxv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19385,19392 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmaxub\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "smaxv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19233,19239 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmaxsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "uminv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19394,19401 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmaxsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "uminv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 19241,19247 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pminub\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sminv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19403,19410 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pminub\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "sminv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19249,19255 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pminsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; MMX shifts
--- 19412,19419 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pminsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
;; MMX shifts
***************
*** 19260,19266 ****
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psraw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ashrv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19424,19431 ----
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psraw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "ashrv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19268,19274 ****
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psrad\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "lshrv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19433,19440 ----
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psrad\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "lshrv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19276,19282 ****
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psrlw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "lshrv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19442,19449 ----
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psrlw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "lshrv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19284,19290 ****
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psrld\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; See logical MMX insns.
(define_insn "mmx_lshrdi3"
--- 19451,19458 ----
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psrld\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
;; See logical MMX insns.
(define_insn "mmx_lshrdi3"
***************
*** 19294,19300 ****
(match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
"TARGET_MMX"
"psrlq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ashlv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19462,19469 ----
(match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
"TARGET_MMX"
"psrlq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "ashlv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19302,19308 ****
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psllw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ashlv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19471,19478 ----
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psllw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "ashlv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19310,19316 ****
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"pslld\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; See logical MMX insns.
(define_insn "mmx_ashldi3"
--- 19480,19487 ----
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"pslld\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
;; See logical MMX insns.
(define_insn "mmx_ashldi3"
***************
*** 19320,19326 ****
(match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
"TARGET_MMX"
"psllq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; MMX pack/unpack insns.
--- 19491,19498 ----
(match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
"TARGET_MMX"
"psllq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
;; MMX pack/unpack insns.
***************
*** 19332,19338 ****
(ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
"TARGET_MMX"
"packsswb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_packssdw"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19504,19511 ----
(ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
"TARGET_MMX"
"packsswb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "mmx_packssdw"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19341,19347 ****
(ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
"TARGET_MMX"
"packssdw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_packuswb"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19514,19521 ----
(ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
"TARGET_MMX"
"packssdw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "mmx_packuswb"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 19350,19356 ****
(us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
"TARGET_MMX"
"packuswb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_punpckhbw"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19524,19531 ----
(us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
"TARGET_MMX"
"packuswb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "mmx_punpckhbw"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 19376,19382 ****
(const_int 85)))]
"TARGET_MMX"
"punpckhbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_punpckhwd"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19551,19558 ----
(const_int 85)))]
"TARGET_MMX"
"punpckhbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_punpckhwd"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19394,19400 ****
(const_int 5)))]
"TARGET_MMX"
"punpckhwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_punpckhdq"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19570,19577 ----
(const_int 5)))]
"TARGET_MMX"
"punpckhwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_punpckhdq"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19408,19414 ****
(const_int 1)))]
"TARGET_MMX"
"punpckhdq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_punpcklbw"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19585,19592 ----
(const_int 1)))]
"TARGET_MMX"
"punpckhdq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_punpcklbw"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 19434,19440 ****
(const_int 85)))]
"TARGET_MMX"
"punpcklbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_punpcklwd"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19612,19619 ----
(const_int 85)))]
"TARGET_MMX"
"punpcklbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_punpcklwd"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19452,19458 ****
(const_int 5)))]
"TARGET_MMX"
"punpcklwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_punpckldq"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19631,19638 ----
(const_int 5)))]
"TARGET_MMX"
"punpcklwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_punpckldq"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19466,19472 ****
(const_int 1)))]
"TARGET_MMX"
"punpckldq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; Miscellaneous stuff
--- 19646,19653 ----
(const_int 1)))]
"TARGET_MMX"
"punpckldq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
;; Miscellaneous stuff
***************
*** 19595,19601 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfadd\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "subv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 19776,19783 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfadd\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "subv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19603,19609 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfsub\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "subrv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 19785,19792 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfsub\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "subrv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19611,19617 ****
(match_operand:V2SF 1 "register_operand" "0")))]
"TARGET_3DNOW"
"pfsubr\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "gtv2sf3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19794,19801 ----
(match_operand:V2SF 1 "register_operand" "0")))]
"TARGET_3DNOW"
"pfsubr\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "gtv2sf3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19619,19625 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfcmpgt\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "gev2sf3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19803,19810 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfcmpgt\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "V2SF")])
(define_insn "gev2sf3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19627,19633 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfcmpge\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "eqv2sf3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19812,19819 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfcmpge\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "V2SF")])
(define_insn "eqv2sf3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19635,19641 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfcmpeq\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pfmaxv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 19821,19828 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfcmpeq\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "V2SF")])
(define_insn "pfmaxv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19643,19649 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfmax\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pfminv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 19830,19837 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfmax\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "pfminv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19651,19657 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfmin\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mulv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 19839,19846 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfmin\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "mulv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19659,19665 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfmul\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "femms"
[(unspec_volatile [(const_int 0)] 46)
--- 19848,19855 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfmul\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxmul")
! (set_attr "mode" "V2SF")])
(define_insn "femms"
[(unspec_volatile [(const_int 0)] 46)
***************
*** 19688,19694 ****
(fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pf2id\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "pf2iw"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19878,19885 ----
(fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pf2id\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "V2SF")])
(define_insn "pf2iw"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19697,19703 ****
(fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
"TARGET_3DNOW_A"
"pf2iw\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "pfacc"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 19888,19895 ----
(fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
"TARGET_3DNOW_A"
"pf2iw\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "V2SF")])
(define_insn "pfacc"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19714,19720 ****
(parallel [(const_int 1)])))))]
"TARGET_3DNOW"
"pfacc\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pfnacc"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 19906,19913 ----
(parallel [(const_int 1)])))))]
"TARGET_3DNOW"
"pfacc\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "pfnacc"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19731,19737 ****
(parallel [(const_int 1)])))))]
"TARGET_3DNOW_A"
"pfnacc\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pfpnacc"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 19924,19931 ----
(parallel [(const_int 1)])))))]
"TARGET_3DNOW_A"
"pfnacc\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "pfpnacc"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19748,19754 ****
(parallel [(const_int 1)])))))]
"TARGET_3DNOW_A"
"pfpnacc\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pi2fw"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 19942,19949 ----
(parallel [(const_int 1)])))))]
"TARGET_3DNOW_A"
"pfpnacc\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "pi2fw"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19764,19777 ****
(parallel [(const_int 1)])))))))]
"TARGET_3DNOW_A"
"pi2fw\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "floatv2si2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pi2fd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
;; This insn is identical to pavgb in operation, but the opcode is
;; different. To avoid accidentally matching pavgb, use an unspec.
--- 19959,19974 ----
(parallel [(const_int 1)])))))))]
"TARGET_3DNOW_A"
"pi2fw\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "V2SF")])
(define_insn "floatv2si2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pi2fd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "V2SF")])
;; This insn is identical to pavgb in operation, but the opcode is
;; different. To avoid accidentally matching pavgb, use an unspec.
***************
*** 19783,19789 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")] 49))]
"TARGET_3DNOW"
"pavgusb\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; 3DNow reciprical and sqrt
--- 19980,19987 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")] 49))]
"TARGET_3DNOW"
"pavgusb\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "TI")])
;; 3DNow reciprical and sqrt
***************
*** 19792,19798 ****
(unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 50))]
"TARGET_3DNOW"
"pfrcp\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "pfrcpit1v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 19990,19997 ----
(unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 50))]
"TARGET_3DNOW"
"pfrcp\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")
! (set_attr "mode" "TI")])
(define_insn "pfrcpit1v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19800,19806 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 51))]
"TARGET_3DNOW"
"pfrcpit1\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pfrcpit2v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 19999,20006 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 51))]
"TARGET_3DNOW"
"pfrcpit1\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")
! (set_attr "mode" "TI")])
(define_insn "pfrcpit2v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19808,19821 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 52))]
"TARGET_3DNOW"
"pfrcpit2\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pfrsqrtv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 53))]
"TARGET_3DNOW"
! "pfrsqrt\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "pfrsqit1v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20008,20023 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 52))]
"TARGET_3DNOW"
"pfrcpit2\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")
! (set_attr "mode" "TI")])
(define_insn "pfrsqrtv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 53))]
"TARGET_3DNOW"
! "pfrsqrt\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")
! (set_attr "mode" "TI")])
(define_insn "pfrsqit1v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19823,19829 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 54))]
"TARGET_3DNOW"
"pfrsqit1\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pmulhrwv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 20025,20032 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 54))]
"TARGET_3DNOW"
"pfrsqit1\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")
! (set_attr "mode" "TI")])
(define_insn "pmulhrwv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19842,19848 ****
(const_int 16))))]
"TARGET_3DNOW"
"pmulhrw\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pswapdv2si2"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 20045,20052 ----
(const_int 16))))]
"TARGET_3DNOW"
"pmulhrw\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxmul")
! (set_attr "mode" "TI")])
(define_insn "pswapdv2si2"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19850,19856 ****
(parallel [(const_int 1) (const_int 0)])))]
"TARGET_3DNOW_A"
"pswapd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "pswapdv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20054,20061 ----
(parallel [(const_int 1) (const_int 0)])))]
"TARGET_3DNOW_A"
"pswapd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "TI")])
(define_insn "pswapdv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19858,19864 ****
(parallel [(const_int 1) (const_int 0)])))]
"TARGET_3DNOW_A"
"pswapd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_expand "prefetch"
[(prefetch (match_operand:SI 0 "address_operand" "")
--- 20063,20070 ----
(parallel [(const_int 1) (const_int 0)])))]
"TARGET_3DNOW_A"
"pswapd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "TI")])
(define_expand "prefetch"
[(prefetch (match_operand:SI 0 "address_operand" "")
***************
*** 19900,19906 ****
return patterns[locality];
}
! [(set_attr "type" "sse")])
(define_insn "*prefetch_3dnow"
[(prefetch (match_operand:SI 0 "address_operand" "p")
--- 20106,20113 ----
return patterns[locality];
}
! [(set_attr "type" "sse")
! (set_attr "memory" "none")])
(define_insn "*prefetch_3dnow"
[(prefetch (match_operand:SI 0 "address_operand" "p")
***************
*** 19913,19919 ****
else
return "prefetchw\t%a0";
}
! [(set_attr "type" "mmx")])
;; SSE2 support
--- 20120,20127 ----
else
return "prefetchw\t%a0";
}
! [(set_attr "type" "mmx")
! (set_attr "memory" "none")])
;; SSE2 support
***************
*** 19923,19929 ****
(match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"addpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmaddv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20131,20138 ----
(match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"addpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "V2DF")])
(define_insn "vmaddv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 19933,19939 ****
(const_int 1)))]
"TARGET_SSE2"
"addsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "subv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20142,20149 ----
(const_int 1)))]
"TARGET_SSE2"
"addsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "DF")])
(define_insn "subv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 19941,19947 ****
(match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"subpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmsubv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20151,20158 ----
(match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"subpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "V2DF")])
(define_insn "vmsubv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 19951,19957 ****
(const_int 1)))]
"TARGET_SSE2"
"subsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "mulv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20162,20169 ----
(const_int 1)))]
"TARGET_SSE2"
"subsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "DF")])
(define_insn "mulv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 19959,19965 ****
(match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"mulpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmmulv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20171,20178 ----
(match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"mulpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssemul")
! (set_attr "mode" "V2DF")])
(define_insn "vmmulv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 19969,19975 ****
(const_int 1)))]
"TARGET_SSE2"
"mulsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "divv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20182,20189 ----
(const_int 1)))]
"TARGET_SSE2"
"mulsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssemul")
! (set_attr "mode" "DF")])
(define_insn "divv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 19977,19983 ****
(match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"divpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmdivv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20191,20198 ----
(match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"divpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssediv")
! (set_attr "mode" "V2DF")])
(define_insn "vmdivv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 19987,19993 ****
(const_int 1)))]
"TARGET_SSE2"
"divsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; SSE min/max
--- 20202,20209 ----
(const_int 1)))]
"TARGET_SSE2"
"divsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssediv")
! (set_attr "mode" "DF")])
;; SSE min/max
***************
*** 19997,20003 ****
(match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"maxpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmsmaxv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20213,20220 ----
(match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"maxpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "V2DF")])
(define_insn "vmsmaxv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 20007,20013 ****
(const_int 1)))]
"TARGET_SSE2"
"maxsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sminv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20224,20231 ----
(const_int 1)))]
"TARGET_SSE2"
"maxsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "DF")])
(define_insn "sminv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 20015,20021 ****
(match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"minpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmsminv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20233,20240 ----
(match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"minpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "V2DF")])
(define_insn "vmsminv2df3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 20025,20031 ****
(const_int 1)))]
"TARGET_SSE2"
"minsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_anddf3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20244,20251 ----
(const_int 1)))]
"TARGET_SSE2"
"minsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "DF")])
(define_insn "sse2_anddf3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 20033,20039 ****
(subreg:TI (match_operand:TI 2 "nonimmediate_operand" "xm") 0)) 0))]
"TARGET_SSE2"
"andpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_nanddf3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20253,20260 ----
(subreg:TI (match_operand:TI 2 "nonimmediate_operand" "xm") 0)) 0))]
"TARGET_SSE2"
"andpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "sse2_nanddf3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 20041,20047 ****
(subreg:TI (match_operand:TI 2 "nonimmediate_operand" "xm") 0)) 0))]
"TARGET_SSE2"
"andnpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_iordf3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20262,20269 ----
(subreg:TI (match_operand:TI 2 "nonimmediate_operand" "xm") 0)) 0))]
"TARGET_SSE2"
"andnpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "sse2_iordf3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 20049,20055 ****
(subreg:TI (match_operand:TI 2 "nonimmediate_operand" "xm") 0)) 0))]
"TARGET_SSE2"
"orpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_xordf3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20271,20278 ----
(subreg:TI (match_operand:TI 2 "nonimmediate_operand" "xm") 0)) 0))]
"TARGET_SSE2"
"orpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "sse2_xordf3"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 20057,20063 ****
(subreg:TI (match_operand:TI 2 "nonimmediate_operand" "xm") 0)) 0))]
"TARGET_SSE2"
"xorpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; SSE2 square root. There doesn't appear to be an extension for the
;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
--- 20280,20287 ----
(subreg:TI (match_operand:TI 2 "nonimmediate_operand" "xm") 0)) 0))]
"TARGET_SSE2"
"xorpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
;; SSE2 square root. There doesn't appear to be an extension for the
;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
***************
*** 20066,20072 ****
(sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
"TARGET_SSE2"
"sqrtpd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "vmsqrtv2df2"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20290,20297 ----
(sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
"TARGET_SSE2"
"sqrtpd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "V2DF")])
(define_insn "vmsqrtv2df2"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 20075,20081 ****
(const_int 1)))]
"TARGET_SSE2"
"sqrtsd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; SSE mask-generating compares
--- 20300,20307 ----
(const_int 1)))]
"TARGET_SSE2"
"sqrtsd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "SF")])
;; SSE mask-generating compares
***************
*** 20086,20092 ****
(match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
"TARGET_SSE2"
"cmp%D3pd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "maskncmpv2df3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
--- 20312,20319 ----
(match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
"TARGET_SSE2"
"cmp%D3pd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "V2DF")])
(define_insn "maskncmpv2df3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
***************
*** 20096,20102 ****
(match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
"TARGET_SSE2"
"cmpn%D3pd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmmaskcmpv2df3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
--- 20323,20330 ----
(match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
"TARGET_SSE2"
"cmpn%D3pd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "V2DF")])
(define_insn "vmmaskcmpv2df3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
***************
*** 20108,20114 ****
(const_int 1)))]
"TARGET_SSE2"
"cmp%D3sd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmmaskncmpv2df3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
--- 20336,20343 ----
(const_int 1)))]
"TARGET_SSE2"
"cmp%D3sd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "DF")])
(define_insn "vmmaskncmpv2df3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
***************
*** 20121,20127 ****
(const_int 1)))]
"TARGET_SSE2"
"cmp%D3sd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_comi"
[(set (reg:CCFP 17)
--- 20350,20357 ----
(const_int 1)))]
"TARGET_SSE2"
"cmp%D3sd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "DF")])
(define_insn "sse2_comi"
[(set (reg:CCFP 17)
***************
*** 20134,20140 ****
(parallel [(const_int 0)]))]))]
"TARGET_SSE2"
"comisd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse2_ucomi"
[(set (reg:CCFPU 17)
--- 20364,20371 ----
(parallel [(const_int 0)]))]))]
"TARGET_SSE2"
"comisd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "DF")])
(define_insn "sse2_ucomi"
[(set (reg:CCFPU 17)
***************
*** 20147,20153 ****
(parallel [(const_int 0)]))]))]
"TARGET_SSE2"
"ucomisd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; SSE Strange Moves.
--- 20378,20385 ----
(parallel [(const_int 0)]))]))]
"TARGET_SSE2"
"ucomisd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "DF")])
;; SSE Strange Moves.
***************
*** 20156,20169 ****
(unspec:SI [(match_operand:V2DF 1 "register_operand" "x")] 33))]
"TARGET_SSE2"
"movmskpd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse2_pmovmskb"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:V16QI 1 "register_operand" "x")] 33))]
"TARGET_SSE2"
"pmovmskb\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse2_maskmovdqu"
[(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
--- 20388,20403 ----
(unspec:SI [(match_operand:V2DF 1 "register_operand" "x")] 33))]
"TARGET_SSE2"
"movmskpd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V2DF")])
(define_insn "sse2_pmovmskb"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:V16QI 1 "register_operand" "x")] 33))]
"TARGET_SSE2"
"pmovmskb\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V2DF")])
(define_insn "sse2_maskmovdqu"
[(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
***************
*** 20172,20199 ****
"TARGET_SSE2"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovdqu\t{%2, %1|%1, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_movntv2df"
[(set (match_operand:V2DF 0 "memory_operand" "=m")
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")] 34))]
"TARGET_SSE2"
"movntpd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse2_movntti"
[(set (match_operand:TI 0 "memory_operand" "=m")
(unspec:TI [(match_operand:TI 1 "register_operand" "x")] 34))]
"TARGET_SSE2"
"movntdq\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse2_movntsi"
[(set (match_operand:SI 0 "memory_operand" "=m")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")] 34))]
"TARGET_SSE2"
"movnti\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; SSE <-> integer/MMX conversions
--- 20406,20437 ----
"TARGET_SSE2"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovdqu\t{%2, %1|%1, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_movntv2df"
[(set (match_operand:V2DF 0 "memory_operand" "=m")
(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")] 34))]
"TARGET_SSE2"
"movntpd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V2DF")])
(define_insn "sse2_movntti"
[(set (match_operand:TI 0 "memory_operand" "=m")
(unspec:TI [(match_operand:TI 1 "register_operand" "x")] 34))]
"TARGET_SSE2"
"movntdq\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_movntsi"
[(set (match_operand:SI 0 "memory_operand" "=m")
(unspec:SI [(match_operand:SI 1 "register_operand" "r")] 34))]
"TARGET_SSE2"
"movnti\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V2DF")])
;; SSE <-> integer/MMX conversions
***************
*** 20204,20224 ****
(float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"cvtdq2ps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvtps2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"cvtps2dq\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvttps2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 30))]
"TARGET_SSE2"
"cvttps2dq\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; Conversions between SI and DF
--- 20442,20465 ----
(float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"cvtdq2ps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V2DF")])
(define_insn "cvtps2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"cvtps2dq\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "cvttps2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
(unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 30))]
"TARGET_SSE2"
"cvttps2dq\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
;; Conversions between SI and DF
***************
*** 20231,20237 ****
(const_int 1)]))))]
"TARGET_SSE2"
"cvtdq2pd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvtpd2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 20472,20479 ----
(const_int 1)]))))]
"TARGET_SSE2"
"cvtdq2pd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V2DF")])
(define_insn "cvtpd2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20240,20246 ****
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_SSE2"
"cvtpd2dq\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvttpd2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 20482,20489 ----
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_SSE2"
"cvtpd2dq\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "cvttpd2dq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20249,20276 ****
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_SSE2"
"cvttpd2dq\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvtpd2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"cvtpd2pi\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvttpd2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")] 30))]
"TARGET_SSE2"
"cvttpd2pi\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvtpi2pd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
(float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
"TARGET_SSE2"
"cvtpi2pd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; Conversions between SI and DF
--- 20492,20523 ----
(const_vector:V2SI [(const_int 0) (const_int 0)])))]
"TARGET_SSE2"
"cvttpd2dq\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "cvtpd2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"cvtpd2pi\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "cvttpd2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")] 30))]
"TARGET_SSE2"
"cvttpd2pi\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "cvtpi2pd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
(float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
"TARGET_SSE2"
"cvtpi2pd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
;; Conversions between SI and DF
***************
*** 20280,20286 ****
(parallel [(const_int 0)]))))]
"TARGET_SSE2"
"cvtsd2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvttsd2si"
[(set (match_operand:SI 0 "register_operand" "=r")
--- 20527,20534 ----
(parallel [(const_int 0)]))))]
"TARGET_SSE2"
"cvtsd2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "SI")])
(define_insn "cvttsd2si"
[(set (match_operand:SI 0 "register_operand" "=r")
***************
*** 20288,20294 ****
(parallel [(const_int 0)]))] 30))]
"TARGET_SSE2"
"cvttsd2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvtsi2sd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20536,20543 ----
(parallel [(const_int 0)]))] 30))]
"TARGET_SSE2"
"cvttsd2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "SI")])
(define_insn "cvtsi2sd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 20299,20305 ****
(const_int 2)))]
"TARGET_SSE2"
"cvtsd2si\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; Conversions between SF and DF
--- 20548,20555 ----
(const_int 2)))]
"TARGET_SSE2"
"cvtsd2si\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "DF")])
;; Conversions between SF and DF
***************
*** 20312,20318 ****
(const_int 14)))]
"TARGET_SSE2"
"cvtsd2ss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "cvtss2sd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20562,20569 ----
(const_int 14)))]
"TARGET_SSE2"
"cvtsd2ss\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "SF")])
(define_insn "cvtss2sd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 20325,20331 ****
(const_int 2)))]
"TARGET_SSE2"
"cvtss2sd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "cvtpd2ps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 20576,20583 ----
(const_int 2)))]
"TARGET_SSE2"
"cvtss2sd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "DF")])
(define_insn "cvtpd2ps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 20336,20342 ****
(const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
"TARGET_SSE2"
"cvtpd2ps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvtps2pd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 20588,20595 ----
(const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
"TARGET_SSE2"
"cvtpd2ps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "cvtps2pd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 20346,20352 ****
(const_int 1)]))))]
"TARGET_SSE2"
"cvtps2pd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; SSE2 variants of MMX insns
--- 20599,20606 ----
(const_int 1)]))))]
"TARGET_SSE2"
"cvtps2pd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V2DF")])
;; SSE2 variants of MMX insns
***************
*** 20358,20364 ****
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "addv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20612,20619 ----
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "addv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20366,20372 ****
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "addv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 20621,20628 ----
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "addv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20374,20380 ****
(match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "addv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
--- 20630,20637 ----
(match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "addv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
***************
*** 20382,20388 ****
(match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "ssaddv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
--- 20639,20646 ----
(match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "ssaddv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
***************
*** 20390,20396 ****
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddsb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "ssaddv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20648,20655 ----
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddsb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "ssaddv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20398,20404 ****
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "usaddv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
--- 20657,20664 ----
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "usaddv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
***************
*** 20406,20412 ****
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddusb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "usaddv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20666,20673 ----
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddusb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "usaddv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20414,20420 ****
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddusw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "subv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
--- 20675,20682 ----
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"paddusw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "subv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
***************
*** 20422,20428 ****
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "subv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20684,20691 ----
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "subv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20430,20436 ****
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "subv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 20693,20700 ----
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "subv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20438,20444 ****
(match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "subv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
--- 20702,20709 ----
(match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "subv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
***************
*** 20446,20452 ****
(match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sssubv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
--- 20711,20718 ----
(match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "sssubv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
***************
*** 20454,20460 ****
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubsb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sssubv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20720,20727 ----
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubsb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "sssubv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20462,20468 ****
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "ussubv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
--- 20729,20736 ----
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "ussubv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
***************
*** 20470,20476 ****
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubusb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "ussubv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20738,20745 ----
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubusb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "ussubv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20478,20484 ****
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubusw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "mulv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20747,20754 ----
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"psubusw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "mulv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20486,20492 ****
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pmullw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "smulv8hi3_highpart"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20756,20763 ----
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pmullw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseimul")
! (set_attr "mode" "TI")])
(define_insn "smulv8hi3_highpart"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20497,20503 ****
(const_int 16))))]
"TARGET_SSE2"
"pmulhw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "umulv8hi3_highpart"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20768,20775 ----
(const_int 16))))]
"TARGET_SSE2"
"pmulhw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseimul")
! (set_attr "mode" "TI")])
(define_insn "umulv8hi3_highpart"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20508,20514 ****
(const_int 16))))]
"TARGET_SSE2"
"pmulhuw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; See the MMX logical operations for the reason for the unspec
(define_insn "sse2_umulsidi3"
--- 20780,20787 ----
(const_int 16))))]
"TARGET_SSE2"
"pmulhuw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseimul")
! (set_attr "mode" "TI")])
;; See the MMX logical operations for the reason for the unspec
(define_insn "sse2_umulsidi3"
***************
*** 20517,20523 ****
(zero_extend:DI (match_operand:DI 2 "nonimmediate_operand" "ym")))] 45))]
"TARGET_SSE2"
"pmuludq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_umulv2siv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=y")
--- 20790,20797 ----
(zero_extend:DI (match_operand:DI 2 "nonimmediate_operand" "ym")))] 45))]
"TARGET_SSE2"
"pmuludq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseimul")
! (set_attr "mode" "TI")])
(define_insn "sse2_umulv2siv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=y")
***************
*** 20531,20537 ****
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE2"
"pmuludq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_pmaddwd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 20805,20812 ----
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE2"
"pmuludq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseimul")
! (set_attr "mode" "TI")])
(define_insn "sse2_pmaddwd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20560,20566 ****
(const_int 7)]))))))]
"TARGET_SSE2"
"pmaddwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; Same as pxor, but don't show input operands so that we don't think
;; they are live.
--- 20835,20842 ----
(const_int 7)]))))))]
"TARGET_SSE2"
"pmaddwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
;; Same as pxor, but don't show input operands so that we don't think
;; they are live.
***************
*** 20568,20574 ****
[(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
"TARGET_SSE2"
"pxor\t{%0, %0|%0, %0}"
! [(set_attr "type" "sse")])
;; MMX unsigned averages/sum of absolute differences
--- 20844,20851 ----
[(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
"TARGET_SSE2"
"pxor\t{%0, %0|%0, %0}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
;; MMX unsigned averages/sum of absolute differences
***************
*** 20589,20595 ****
(const_int 1)))]
"TARGET_SSE2"
"pavgb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_uavgv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20866,20873 ----
(const_int 1)))]
"TARGET_SSE2"
"pavgb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "sse2_uavgv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20604,20610 ****
(const_int 1)))]
"TARGET_SSE2"
"pavgw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; @@@ this isn't the right representation.
(define_insn "sse2_psadbw"
--- 20882,20889 ----
(const_int 1)))]
"TARGET_SSE2"
"pavgw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
;; @@@ this isn't the right representation.
(define_insn "sse2_psadbw"
***************
*** 20613,20619 ****
(match_operand:V16QI 2 "nonimmediate_operand" "ym"))))]
"TARGET_SSE2"
"psadbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; MMX insert/extract/shuffle
--- 20892,20899 ----
(match_operand:V16QI 2 "nonimmediate_operand" "ym"))))]
"TARGET_SSE2"
"psadbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
;; MMX insert/extract/shuffle
***************
*** 20626,20632 ****
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_SSE2"
"pinsrw\t{%3, %2, %0|%0, %2, %3}"
! [(set_attr "type" "sse")])
(define_insn "sse2_pextrw"
[(set (match_operand:SI 0 "register_operand" "=r")
--- 20906,20913 ----
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_SSE2"
"pinsrw\t{%3, %2, %0|%0, %2, %3}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_pextrw"
[(set (match_operand:SI 0 "register_operand" "=r")
***************
*** 20636,20642 ****
[(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SSE2"
"pextrw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_pshufd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 20917,20924 ----
[(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SSE2"
"pextrw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_pshufd"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20644,20650 ****
(match_operand:SI 2 "immediate_operand" "i")] 41))]
"TARGET_SSE2"
"pshufd\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_pshuflw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20926,20933 ----
(match_operand:SI 2 "immediate_operand" "i")] 41))]
"TARGET_SSE2"
"pshufd\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_pshuflw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20652,20658 ****
(match_operand:SI 2 "immediate_operand" "i")] 55))]
"TARGET_SSE2"
"pshuflw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_pshufhw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20935,20942 ----
(match_operand:SI 2 "immediate_operand" "i")] 55))]
"TARGET_SSE2"
"pshuflw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_pshufhw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20660,20666 ****
(match_operand:SI 2 "immediate_operand" "i")] 56))]
"TARGET_SSE2"
"pshufhw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "sse")])
;; MMX mask-generating comparisons
--- 20944,20951 ----
(match_operand:SI 2 "immediate_operand" "i")] 56))]
"TARGET_SSE2"
"pshufhw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
;; MMX mask-generating comparisons
***************
*** 20670,20676 ****
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pcmpeqb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "eqv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20955,20962 ----
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pcmpeqb\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "TI")])
(define_insn "eqv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20678,20684 ****
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pcmpeqw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "eqv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 20964,20971 ----
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pcmpeqw\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "TI")])
(define_insn "eqv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20686,20692 ****
(match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pcmpeqd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "gtv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
--- 20973,20980 ----
(match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pcmpeqd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "TI")])
(define_insn "gtv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
***************
*** 20694,20700 ****
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pcmpgtb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "gtv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20982,20989 ----
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pcmpgtb\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "TI")])
(define_insn "gtv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20702,20708 ****
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pcmpgtw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "gtv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 20991,20998 ----
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pcmpgtw\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "TI")])
(define_insn "gtv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20710,20716 ****
(match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pcmpgtd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; MMX max/min insns
--- 21000,21007 ----
(match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pcmpgtd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "TI")])
;; MMX max/min insns
***************
*** 20721,20727 ****
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pmaxub\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "smaxv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 21012,21019 ----
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pmaxub\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "smaxv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20729,20735 ****
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pmaxsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "uminv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
--- 21021,21028 ----
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pmaxsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "uminv16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x")
***************
*** 20737,20743 ****
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pminub\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sminv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 21030,21037 ----
(match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pminub\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
(define_insn "sminv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20745,20751 ****
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pminsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; MMX shifts
--- 21039,21046 ----
(match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pminsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseiadd")
! (set_attr "mode" "TI")])
;; MMX shifts
***************
*** 20756,20762 ****
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psraw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "ashrv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 21051,21058 ----
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psraw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseishft")
! (set_attr "mode" "TI")])
(define_insn "ashrv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20764,20770 ****
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrad\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "lshrv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 21060,21067 ----
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrad\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseishft")
! (set_attr "mode" "TI")])
(define_insn "lshrv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20772,20778 ****
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrlw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "lshrv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 21069,21076 ----
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrlw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseishft")
! (set_attr "mode" "TI")])
(define_insn "lshrv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20780,20786 ****
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrld\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_lshrv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
--- 21078,21085 ----
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrld\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseishft")
! (set_attr "mode" "TI")])
(define_insn "sse2_lshrv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
***************
*** 20788,20794 ****
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrlq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "ashlv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 21087,21094 ----
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psrlq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseishft")
! (set_attr "mode" "TI")])
(define_insn "ashlv8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20796,20802 ****
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psllw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "ashlv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 21096,21103 ----
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psllw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseishft")
! (set_attr "mode" "TI")])
(define_insn "ashlv4si3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20804,20810 ****
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"pslld\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_ashlv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
--- 21105,21112 ----
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"pslld\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseishft")
! (set_attr "mode" "TI")])
(define_insn "sse2_ashlv2di3"
[(set (match_operand:V2DI 0 "register_operand" "=x")
***************
*** 20812,20818 ****
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psllq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; See logical MMX insns for the reason for the unspec. Strictly speaking
;; we wouldn't need here it since we never generate TImode arithmetic.
--- 21114,21121 ----
(match_operand:TI 2 "nonmemory_operand" "xi")))]
"TARGET_SSE2"
"psllq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseishft")
! (set_attr "mode" "TI")])
;; See logical MMX insns for the reason for the unspec. Strictly speaking
;; we wouldn't need here it since we never generate TImode arithmetic.
***************
*** 20826,20832 ****
(const_int 8)))] 30))]
"TARGET_SSE2"
"pslldq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_lshrti3"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 21129,21136 ----
(const_int 8)))] 30))]
"TARGET_SSE2"
"pslldq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseishft")
! (set_attr "mode" "TI")])
(define_insn "sse2_lshrti3"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 20836,20842 ****
(const_int 8)))] 30))]
"TARGET_SSE2"
"pslrdq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; SSE unpack
--- 21140,21147 ----
(const_int 8)))] 30))]
"TARGET_SSE2"
"pslrdq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseishft")
! (set_attr "mode" "TI")])
;; SSE unpack
***************
*** 20849,20855 ****
(parallel [(const_int 0)]))))]
"TARGET_SSE2"
"unpckhpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_unpcklpd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 21154,21161 ----
(parallel [(const_int 0)]))))]
"TARGET_SSE2"
"unpckhpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_unpcklpd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 20860,20866 ****
(parallel [(const_int 1)]))))]
"TARGET_SSE2"
"unpcklpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; MMX pack/unpack insns.
--- 21166,21173 ----
(parallel [(const_int 1)]))))]
"TARGET_SSE2"
"unpcklpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
;; MMX pack/unpack insns.
***************
*** 20871,20877 ****
(ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
"TARGET_SSE2"
"packsswb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_packssdw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 21178,21185 ----
(ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
"TARGET_SSE2"
"packsswb\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_packssdw"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20880,20886 ****
(ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
"TARGET_SSE2"
"packssdw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_packuswb"
[(set (match_operand:V16QI 0 "register_operand" "=x")
--- 21188,21195 ----
(ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
"TARGET_SSE2"
"packssdw\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_packuswb"
[(set (match_operand:V16QI 0 "register_operand" "=x")
***************
*** 20889,20895 ****
(us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
"TARGET_SSE2"
"packuswb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_punpckhbw"
[(set (match_operand:V16QI 0 "register_operand" "=x")
--- 21198,21205 ----
(us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
"TARGET_SSE2"
"packuswb\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_punpckhbw"
[(set (match_operand:V16QI 0 "register_operand" "=x")
***************
*** 20915,20921 ****
(const_int 21845)))]
"TARGET_SSE2"
"punpckhbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_punpckhwd"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 21225,21232 ----
(const_int 21845)))]
"TARGET_SSE2"
"punpckhbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_punpckhwd"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20933,20939 ****
(const_int 85)))]
"TARGET_SSE2"
"punpckhwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_punpckhdq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 21244,21251 ----
(const_int 85)))]
"TARGET_SSE2"
"punpckhwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_punpckhdq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20947,20953 ****
(const_int 5)))]
"TARGET_SSE2"
"punpckhdq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_punpcklbw"
[(set (match_operand:V16QI 0 "register_operand" "=x")
--- 21259,21266 ----
(const_int 5)))]
"TARGET_SSE2"
"punpckhdq\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_punpcklbw"
[(set (match_operand:V16QI 0 "register_operand" "=x")
***************
*** 20973,20979 ****
(const_int 21845)))]
"TARGET_SSE2"
"punpcklbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_punpcklwd"
[(set (match_operand:V8HI 0 "register_operand" "=x")
--- 21286,21293 ----
(const_int 21845)))]
"TARGET_SSE2"
"punpcklbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_punpcklwd"
[(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20991,20997 ****
(const_int 85)))]
"TARGET_SSE2"
"punpcklwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_punpckldq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 21305,21312 ----
(const_int 85)))]
"TARGET_SSE2"
"punpcklwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_punpckldq"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 21005,21011 ****
(const_int 5)))]
"TARGET_SSE2"
"punpckldq\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; SSE2 moves
--- 21320,21327 ----
(const_int 5)))]
"TARGET_SSE2"
"punpckldq\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
;; SSE2 moves
***************
*** 21016,21022 ****
"@
movapd\t{%1, %0|%0, %1}
movapd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse2_movupd"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
--- 21332,21339 ----
"@
movapd\t{%1, %0|%0, %1}
movapd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "V2DF")])
(define_insn "sse2_movupd"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
***************
*** 21025,21031 ****
"@
movupd\t{%1, %0|%0, %1}
movupd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse2_movdqa"
[(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
--- 21342,21349 ----
"@
movupd\t{%1, %0|%0, %1}
movupd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V2DF")])
(define_insn "sse2_movdqa"
[(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
***************
*** 21034,21040 ****
"@
movdqa\t{%1, %0|%0, %1}
movdqa\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse2_movdqu"
[(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
--- 21352,21359 ----
"@
movdqa\t{%1, %0|%0, %1}
movdqa\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "TI")])
(define_insn "sse2_movdqu"
[(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
***************
*** 21043,21049 ****
"@
movdqu\t{%1, %0|%0, %1}
movdqu\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse2_movdq2q"
[(set (match_operand:DI 0 "nonimmediate_operand" "=y")
--- 21362,21369 ----
"@
movdqu\t{%1, %0|%0, %1}
movdqu\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_movdq2q"
[(set (match_operand:DI 0 "nonimmediate_operand" "=y")
***************
*** 21051,21057 ****
(parallel [(const_int 0)])))]
"TARGET_SSE2"
"movdq2q\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse2_movq2dq"
[(set (match_operand:V2DI 0 "nonimmediate_operand" "=x")
--- 21371,21378 ----
(parallel [(const_int 0)])))]
"TARGET_SSE2"
"movdq2q\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_movq2dq"
[(set (match_operand:V2DI 0 "nonimmediate_operand" "=x")
***************
*** 21059,21065 ****
(const_vector:DI [(const_int 0)])))]
"TARGET_SSE2"
"movq2dq\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse2_movhpd"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
--- 21380,21387 ----
(const_vector:DI [(const_int 0)])))]
"TARGET_SSE2"
"movq2dq\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "TI")])
(define_insn "sse2_movhpd"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
***************
*** 21069,21075 ****
(const_int 2)))]
"TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
"movhpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_movlpd"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
--- 21391,21398 ----
(const_int 2)))]
"TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
"movhpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V2DF")])
(define_insn "sse2_movlpd"
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
***************
*** 21079,21085 ****
(const_int 1)))]
"TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
"movlpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_loadsd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 21402,21409 ----
(const_int 1)))]
"TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
"movlpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V2DF")])
(define_insn "sse2_loadsd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 21089,21095 ****
(const_int 1)))]
"TARGET_SSE2"
"movsd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse2_movsd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 21413,21420 ----
(const_int 1)))]
"TARGET_SSE2"
"movsd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "DF")])
(define_insn "sse2_movsd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 21099,21105 ****
(const_int 1)))]
"TARGET_SSE2"
"movsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse2_storesd"
[(set (match_operand:DF 0 "memory_operand" "=m")
--- 21424,21431 ----
(const_int 1)))]
"TARGET_SSE2"
"movsd\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "DF")])
(define_insn "sse2_storesd"
[(set (match_operand:DF 0 "memory_operand" "=m")
***************
*** 21108,21114 ****
(parallel [(const_int 0)])))]
"TARGET_SSE2"
"movsd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse2_shufpd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
--- 21434,21441 ----
(parallel [(const_int 0)])))]
"TARGET_SSE2"
"movsd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "DF")])
(define_insn "sse2_shufpd"
[(set (match_operand:V2DF 0 "register_operand" "=x")
***************
*** 21118,21130 ****
"TARGET_SSE2"
;; @@@ check operand order for intel/nonintel syntax
"shufpd\t{%3, %2, %0|%0, %2, %3}"
! [(set_attr "type" "sse")])
(define_insn "sse2_clflush"
[(unspec_volatile [(match_operand:SI 0 "address_operand" "p")] 57)]
"TARGET_SSE2"
"clflush %0"
! [(set_attr "type" "sse")])
(define_expand "sse2_mfence"
[(set (match_dup 0)
--- 21445,21459 ----
"TARGET_SSE2"
;; @@@ check operand order for intel/nonintel syntax
"shufpd\t{%3, %2, %0|%0, %2, %3}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V2DF")])
(define_insn "sse2_clflush"
[(unspec_volatile [(match_operand:SI 0 "address_operand" "p")] 57)]
"TARGET_SSE2"
"clflush %0"
! [(set_attr "type" "sse")
! (set_attr "memory" "unknown")])
(define_expand "sse2_mfence"
[(set (match_dup 0)
next prev parent reply other threads:[~2002-04-30 17:27 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-04-27 16:15 Jan Hubicka
2002-04-29 15:19 ` Richard Henderson
2002-04-30 10:29 ` Jan Hubicka [this message]
[not found] ` <20020430160511.GK18000@atrey.karlin.mff.cuni.cz>
[not found] ` <20020430163200.A3211@redhat.com>
[not found] ` <20020501070806.GC21948@atrey.karlin.mff.cuni.cz>
[not found] ` <20020501093122.A3948@redhat.com>
[not found] ` <20020501194421.GD1512@atrey.karlin.mff.cuni.cz>
[not found] ` <20020501135713.A4134@redhat.com>
[not found] ` <20020501220959.GB10884@atrey.karlin.mff.cuni.cz>
[not found] ` <20020501153524.A4237@redhat.com>
2002-05-02 9:33 ` Re-enable crossjumping before bb-reorder Jan Hubicka
2002-05-02 10:34 ` Richard Henderson
2002-05-02 10:39 ` Jan Hubicka
2002-05-02 10:42 ` Richard Henderson
[not found] ` <20020514091823.GN6514@atrey.karlin.mff.cuni.cz>
[not found] ` <20020514172803.GC1535@atrey.karlin.mff.cuni.cz>
[not found] ` <20020515072607.GH4292@atrey.karlin.mff.cuni.cz>
[not found] ` <20020515151110.GA24680@atrey.karlin.mff.cuni.cz>
2002-05-15 17:00 ` Basic block renumbering removal Richard Henderson
2002-05-15 23:48 ` Zdenek Dvorak
2002-05-16 10:41 ` Richard Henderson
2002-05-16 11:42 ` Zdenek Dvorak
2002-05-16 13:00 ` Zdenek Dvorak
2002-05-16 15:30 ` Richard Henderson
2002-05-16 15:38 ` Zdenek Dvorak
2002-05-17 5:10 ` Jan Hubicka
2002-05-17 4:53 ` Jan Hubicka
2002-05-19 14:40 ` Zdenek Dvorak
2002-05-19 14:48 ` Richard Henderson
2002-05-19 15:13 ` Zdenek Dvorak
2002-05-19 16:56 ` Richard Henderson
2002-05-19 18:50 ` Basic block renumbering removal, part 2 Zdenek Dvorak
2002-05-20 20:10 ` Richard Henderson
2002-05-20 23:09 ` Zdenek Dvorak
2002-05-21 1:03 ` Richard Henderson
2002-05-22 13:43 ` Basic block renumbering removal, part 3 Zdenek Dvorak
2002-05-23 1:18 ` Richard Henderson
2002-05-23 16:27 ` Basic block renumbering removal, part 4 Zdenek Dvorak
2002-05-25 21:41 ` Richard Henderson
2002-05-27 15:12 ` Zdenek Dvorak
2002-05-27 16:33 ` Richard Henderson
2002-12-19 11:24 ` [PATCH] rtlopt merge part 1 -- loop analysis Zdenek Dvorak
2002-12-19 11:38 ` Joseph S. Myers
2002-12-19 12:42 ` Zdenek Dvorak
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20020430172739.GT18000@atrey.karlin.mff.cuni.cz \
--to=jh@suse.cz \
--cc=gcc-patches@gcc.gnu.org \
--cc=patches@x86-64.org \
--cc=rth@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).