* ns32k port patches
@ 2002-07-13 7:14 Ian Dall
2002-07-13 11:23 ` Jason R Thorpe
2002-07-15 15:45 ` Richard Henderson
0 siblings, 2 replies; 7+ messages in thread
From: Ian Dall @ 2002-07-13 7:14 UTC (permalink / raw)
To: gcc-patches
This patch for the ns32k port cleans up the machine dependent options.
It adds a new -mieee-fp option with the same semantics as for i386 port.
This requires kernel support and is off by default for most targets.
It fixes up a case of incorrect code generation with -fomit-frame-pointer.
Here is the ChangeLog entry:
2002-07-13 Ian Dall <ian@sibyl.beware.dropbear.id.au>
* doc/invoke.texi (NS32K Options): Document -mieee-fp option
* config/ns32k/ns32k.md (addsi3, *frame_addr, *stack_addr): merge
into addsi3 using register class "x" and "y".
* config/ns32k/ns32k.md (*madddf, *maddsf, *msubdf, *msubsf):
"earlyclobber" constraint modifier for some alternative.
* config/ns32k/ns32k.md (tstdf, tstsf, cmpdf, cmpsf, blt, ble)
(*ble, *blt): Flag to indicate bCOND and sCOND should check for
unordered.
config/ns32k/ns32k.h (CC_UNORD): define corresponding mask.
* config/ns32k/ns32k.h (TARGET_IEEE_FP, MASK_IEEE_FP,
OVERRIDE_OPTIONS): Add -mieee-fp. option.
* config/ns32k/ns32k.h (TARGET_DEFAULT, OVERRIDE_OPTIONS)
(MASK_32081, MASK_32381, MASK_MULT_ADD, MASK_RTD, MASK_REGPARM)
(MASK_32532, MASK_32332, MASK_SB, MASK_HIMEM, MASK_BITFIELD)
(MASK_SRC, SMALL_REGISTER_CLASSES): Use symbolic representation of
option masks and rationalize.
(config/ns32k/merlin.h (TARGET_DEFAULT): likewise.
(config/ns32k/pc532.h (TARGET_DEFAULT): likewise.
(config/ns32k/sequent.h (TARGET_DEFAULT): likewise.
(config/ns32k/tek6000.h (TARGET_DEFAULT): likewise.
and here is the patch:
Index: config/ns32k/encore.h
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/encore.h,v
retrieving revision 1.1.1.3
diff -c -r1.1.1.3 encore.h
*** config/ns32k/encore.h 30 Apr 2002 23:38:11 -0000 1.1.1.3
--- config/ns32k/encore.h 9 Jul 2002 14:02:03 -0000
***************
*** 48,54 ****
#undef TARGET_VERSION
#undef FUNCTION_PROFILER
! #define TARGET_DEFAULT 9 /* 32332 with 32081. */
#define TARGET_VERSION fprintf (stderr, " (32000, Encore syntax)");
/* Note Encore does not standardly do -Dencore. */
/* budd: should have a -ns32332 (or -apc) switch! but no harm for now */
--- 48,55 ----
#undef TARGET_VERSION
#undef FUNCTION_PROFILER
! #undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_32532 | MASK_32081 | MASK_SB)
#define TARGET_VERSION fprintf (stderr, " (32000, Encore syntax)");
/* Note Encore does not standardly do -Dencore. */
/* budd: should have a -ns32332 (or -apc) switch! but no harm for now */
Index: config/ns32k/merlin.h
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/merlin.h,v
retrieving revision 1.1.1.1
diff -c -r1.1.1.1 merlin.h
*** config/ns32k/merlin.h 25 Nov 2001 13:34:22 -0000 1.1.1.1
--- config/ns32k/merlin.h 9 Jul 2002 14:02:03 -0000
***************
*** 37,43 ****
/* Don't split DBX symbols into continuations. */
#define DBX_CONTIN_LENGTH 0
! #define TARGET_DEFAULT 1
/* Print subsidiary information on the compiler version in use. */
#undef TARGET_VERSION
--- 37,44 ----
/* Don't split DBX symbols into continuations. */
#define DBX_CONTIN_LENGTH 0
! #undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_32081 | MASK_SB | MASK_BITFIELD)
/* Print subsidiary information on the compiler version in use. */
#undef TARGET_VERSION
Index: config/ns32k/netbsd.h
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/netbsd.h,v
retrieving revision 1.1.1.2
diff -c -r1.1.1.2 netbsd.h
*** config/ns32k/netbsd.h 30 Apr 2002 23:38:11 -0000 1.1.1.2
--- config/ns32k/netbsd.h 9 Jul 2002 14:02:03 -0000
***************
*** 28,34 ****
FPU is 32381;
Use multiply-add instructions */
! #define TARGET_DEFAULT (1 + 24 + 32 + 64 + 256 + 512)
/* 32-bit alignment for efficiency */
--- 28,36 ----
FPU is 32381;
Use multiply-add instructions */
! #undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_32532 \
! | MASK_32381 | MASK_IEEE_FP | MASK_MULT_ADD)
/* 32-bit alignment for efficiency */
Index: config/ns32k/ns32k.h
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/ns32k.h,v
retrieving revision 1.1.1.3
diff -c -r1.1.1.3 ns32k.h
*** config/ns32k/ns32k.h 30 Apr 2002 23:38:11 -0000 1.1.1.3
--- config/ns32k/ns32k.h 13 Jul 2002 12:33:15 -0000
***************
*** 62,77 ****
extern int target_flags;
/* Macros used in the machine description to test the flags. */
/* Compile 32081 insns for floating point (not library calls). */
! #define TARGET_32081 (target_flags & 1)
! #define TARGET_32381 (target_flags & 256)
/* The use of multiply-add instructions is optional because there may
* be cases where it produces worse code.
*/
! #define TARGET_MULT_ADD (target_flags & 512)
/* Compile using rtd insn calling sequence.
This will not work unless you use prototypes at least
--- 62,90 ----
extern int target_flags;
/* Macros used in the machine description to test the flags. */
+ /* Masks for -m flags */
+ #define MASK_32081 1
+ #define MASK_32381 256
+ #define MASK_MULT_ADD 512
+ #define MASK_RTD 2
+ #define MASK_REGPARM 4
+ #define MASK_32532 8
+ #define MASK_32332 16
+ #define MASK_SB 32
+ #define MASK_HIMEM 128
+ #define MASK_BITFIELD 64
+ #define MASK_IEEE_FP 2048
+ #define MASK_SRC 1024
/* Compile 32081 insns for floating point (not library calls). */
! #define TARGET_32081 (target_flags & MASK_32081)
! #define TARGET_32381 (target_flags & MASK_32381)
/* The use of multiply-add instructions is optional because there may
* be cases where it produces worse code.
*/
! #define TARGET_MULT_ADD (target_flags & MASK_MULT_ADD)
/* Compile using rtd insn calling sequence.
This will not work unless you use prototypes at least
***************
*** 79,97 ****
#define TARGET_RTD (target_flags & 2)
/* Compile passing first two args in regs 0 and 1. */
! #define TARGET_REGPARM (target_flags & 4)
/* Options to select type of CPU, for better optimization.
The output is correct for any kind of 32000 regardless of these options. */
! #define TARGET_32532 (target_flags & 8)
! #define TARGET_32332 (target_flags & 16)
/* Ok to use the static base register (and presume it's 0) */
! #define TARGET_SB ((target_flags & 32) == 0)
! #define TARGET_HIMEM (target_flags & 128)
/* Compile using bitfield insns. */
! #define TARGET_BITFIELD ((target_flags & 64) == 0)
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
--- 92,115 ----
#define TARGET_RTD (target_flags & 2)
/* Compile passing first two args in regs 0 and 1. */
! #define TARGET_REGPARM (target_flags & MASK_REGPARM)
/* Options to select type of CPU, for better optimization.
The output is correct for any kind of 32000 regardless of these options. */
!
! #define TARGET_32532 (target_flags & MASK_32532)
!
! #define TARGET_32332 (target_flags & MASK_32332)
/* Ok to use the static base register (and presume it's 0) */
! #define TARGET_SB (target_flags & MASK_SB)
!
! #define TARGET_HIMEM (target_flags & MASK_HIMEM)
/* Compile using bitfield insns. */
! #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
!
! #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
***************
*** 99,140 ****
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
! #define TARGET_SWITCHES \
! { { "32081", 1, N_("Use hardware fp")}, \
! { "soft-float", -257, N_("Don't use hardware fp")}, \
! { "rtd", 2, N_("Alternative calling convention")}, \
! { "nortd", -2, N_("Use normal calling convention")}, \
! { "regparm", 4, N_("Pass some arguments in registers")}, \
! { "noregparm", -4, N_("Pass all arguments on stack")}, \
! { "32532", 24, N_("Optimize for 32532 cpu")}, \
! { "32332", 16, N_("Optimize for 32332 cpu")}, \
! { "32332", -8, 0}, \
! { "32032", -24, N_("Optimize for 32032")}, \
! { "sb", -32, \
! N_("Register sb is zero. Use for absolute addressing")}, \
! { "nosb", 32, N_("Do not use register sb")}, \
! { "bitfield", -64, N_("Do not use bit-field instructions")}, \
! { "nobitfield", 64, N_("Use bit-field instructions")}, \
! { "himem", 128, N_("Generate code for high memory")}, \
! { "nohimem", -128, N_("Generate code for low memory")}, \
! { "32381", 256, N_("32381 fpu")}, \
! { "mult-add", 512, N_("Use multiply-accumulate fp instructions")}, \
! { "nomult-add", -512, \
! N_("Do not use multiply-accumulate fp instructions") }, \
! { "src", 1024, N_("\"Small register classes\" kludge")}, \
! { "nosrc", -1024, N_("No \"Small register classes\" kludge")}, \
{ "", TARGET_DEFAULT, 0}}
! /* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */
/* When we are generating PIC, the sb is used as a pointer
to the GOT. 32381 is a superset of 32081 */
! #define OVERRIDE_OPTIONS \
! { \
! if (flag_pic || TARGET_HIMEM) target_flags |= 32; \
! if (TARGET_32381) target_flags |= 1; \
! else target_flags &= ~512; \
}
/* Zero or more C statements that may conditionally modify two
--- 117,166 ----
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
! #define TARGET_SWITCHES \
! { { "32081", MASK_32081, N_("Use hardware fp")}, \
! { "soft-float", -(MASK_32081 | MASK_32381), \
! N_("Don't use hardware fp")}, \
! { "rtd", MASK_RTD, N_("Alternative calling convention")}, \
! { "nortd", -MASK_RTD, N_("Use normal calling convention")}, \
! { "regparm", MASK_REGPARM, N_("Pass some arguments in registers")}, \
! { "noregparm", -MASK_REGPARM, N_("Pass all arguments on stack")}, \
! { "32532", MASK_32532, N_("Optimize for 32532 cpu")}, \
! { "32332", MASK_32332, N_("Optimize for 32332 cpu")}, \
! { "32032", -(MASK_32532 | MASK_32332), N_("Optimize for 32032")}, \
! { "sb", MASK_SB, \
! N_("Register sb is zero. Use for absolute addressing")}, \
! { "nosb", -MASK_SB, N_("Do not use register sb")}, \
! { "bitfield", MASK_BITFIELD, N_("Do not use bit-field instructions")}, \
! { "nobitfield", -MASK_BITFIELD, N_("Use bit-field instructions")}, \
! { "himem", MASK_HIMEM, N_("Generate code for high memory")}, \
! { "nohimem", -MASK_HIMEM, N_("Generate code for low memory")}, \
! { "32381", MASK_32381, N_("32381 fpu")}, \
! { "mult-add", MASK_MULT_ADD, \
! N_("Use multiply-accumulate fp instructions")}, \
! { "nomult-add", -MASK_MULT_ADD, \
! N_("Do not use multiply-accumulate fp instructions") }, \
! { "src", MASK_SRC, N_("\"Small register classes\" kludge")}, \
! { "nosrc", -MASK_SRC, N_("No \"Small register classes\" kludge")}, \
! { "ieee-fp", MASK_IEEE_FP, N_("Use IEEE math for fp comparisons")}, \
! { "noieee-fp", -MASK_IEEE_FP, \
! N_("Do not use IEEE math for fp comparisons")}, \
{ "", TARGET_DEFAULT, 0}}
! /* TARGET_DEFAULT is redefined in encore.h, pc532.h, etc. */
! #define TARGET_DEFAULT (MASK_32081 | MASK_SB | MASK_BITFIELD | MASK_IEEE_FP)
/* When we are generating PIC, the sb is used as a pointer
to the GOT. 32381 is a superset of 32081 */
! #define OVERRIDE_OPTIONS \
! { \
! if (TARGET_32532) target_flags |= MASK_32532; \
! if (flag_pic || TARGET_HIMEM) target_flags |= MASK_SB; \
! if (TARGET_32381) target_flags |= MASK_32081; \
! else target_flags &= ~MASK_MULT_ADD; \
! if (flag_unsafe_math_optimizations) \
! target_flags &= ~MASK_IEEE_FP; \
}
/* Zero or more C statements that may conditionally modify two
***************
*** 848,854 ****
/* SMALL_REGISTER_CLASSES is a run time option. This should no longer
be necessay and should go when we have confidence that we won't run
out of spill registers */
! #define SMALL_REGISTER_CLASSES (target_flags & 1024)
/* A C expression whose value is nonzero if pseudos that have been
assigned to registers of class CLASS would likely be spilled
--- 874,880 ----
/* SMALL_REGISTER_CLASSES is a run time option. This should no longer
be necessay and should go when we have confidence that we won't run
out of spill registers */
! #define SMALL_REGISTER_CLASSES (target_flags & MASK_SRC)
/* A C expression whose value is nonzero if pseudos that have been
assigned to registers of class CLASS would likely be spilled
***************
*** 1176,1181 ****
--- 1202,1211 ----
/* This bit means that what ought to be in the Z bit
is complemented in the F bit. */
#define CC_Z_IN_NOT_F 010000
+
+ /* This bit means that the L bit indicates unordered (IEEE) comparison.
+ */
+ #define CC_UNORD 020000
/* Store in cc_status the expressions
that the condition codes will describe
Index: config/ns32k/ns32k.md
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/ns32k.md,v
retrieving revision 1.3
diff -c -r1.3 ns32k.md
*** config/ns32k/ns32k.md 18 Jun 2002 15:13:07 -0000 1.3
--- config/ns32k/ns32k.md 9 Jul 2002 14:42:01 -0000
***************
*** 94,99 ****
--- 94,101 ----
"TARGET_32081"
"*
{ cc_status.flags |= CC_REVERSED;
+ if (TARGET_IEEE_FP)
+ cc_status.flags |= CC_UNORD;
operands[1] = CONST0_RTX (DFmode);
return \"cmpl %1,%0\"; }")
***************
*** 103,108 ****
--- 105,112 ----
"TARGET_32081"
"*
{ cc_status.flags |= CC_REVERSED;
+ if (TARGET_IEEE_FP)
+ cc_status.flags |= CC_UNORD;
operands[1] = CONST0_RTX (SFmode);
return \"cmpf %1,%0\"; }")
***************
*** 202,215 ****
(compare (match_operand:DF 0 "general_operand" "lmF")
(match_operand:DF 1 "general_operand" "lmF")))]
"TARGET_32081"
! "cmpl %0,%1")
(define_insn "cmpsf"
[(set (cc0)
(compare (match_operand:SF 0 "general_operand" "fmF")
(match_operand:SF 1 "general_operand" "fmF")))]
"TARGET_32081"
! "cmpf %0,%1")
\f
;; movdf and movsf copy between general and floating registers using
;; the stack. In principle, we could get better code not allowing
--- 206,227 ----
(compare (match_operand:DF 0 "general_operand" "lmF")
(match_operand:DF 1 "general_operand" "lmF")))]
"TARGET_32081"
! "*
! {
! if (TARGET_IEEE_FP)
! cc_status.flags |= CC_UNORD;
! return \"cmpl %0,%1\";}")
(define_insn "cmpsf"
[(set (cc0)
(compare (match_operand:SF 0 "general_operand" "fmF")
(match_operand:SF 1 "general_operand" "fmF")))]
"TARGET_32081"
! "*
! {
! if (TARGET_IEEE_FP)
! cc_status.flags |= CC_UNORD;
! return \"cmpf %0,%1\";}")
\f
;; movdf and movsf copy between general and floating registers using
;; the stack. In principle, we could get better code not allowing
***************
*** 798,804 ****
\f
;; Multiply-add instructions
(define_insn "*madddf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,lm")
(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
(match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
(match_operand:DF 3 "general_operand" "0,lmF,lmF")))]
--- 810,816 ----
\f
;; Multiply-add instructions
(define_insn "*madddf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,&lm")
(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
(match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
(match_operand:DF 3 "general_operand" "0,lmF,lmF")))]
***************
*** 809,815 ****
mull %2,%0\;addl %3,%0")
(define_insn "*maddsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,fm")
(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
(match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
(match_operand:SF 3 "general_operand" "0,fmF,fmF")))]
--- 821,827 ----
mull %2,%0\;addl %3,%0")
(define_insn "*maddsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,&fm")
(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
(match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
(match_operand:SF 3 "general_operand" "0,fmF,fmF")))]
***************
*** 822,828 ****
;; Multiply-sub instructions
(define_insn "*msubdf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=v,lm")
(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
(match_operand:DF 2 "general_operand" "lmF,lmF"))
(match_operand:DF 3 "general_operand" "lmF,lmF")))]
--- 834,840 ----
;; Multiply-sub instructions
(define_insn "*msubdf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=&v,&lm")
(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
(match_operand:DF 2 "general_operand" "lmF,lmF"))
(match_operand:DF 3 "general_operand" "lmF,lmF")))]
***************
*** 832,838 ****
mull %2,%0\;subl %3,%0")
(define_insn "*msubsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=u,fm")
(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
(match_operand:SF 2 "general_operand" "fmF,fmF"))
(match_operand:SF 3 "general_operand" "fmF,fmF")))]
--- 844,850 ----
mull %2,%0\;subl %3,%0")
(define_insn "*msubsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=&u,&fm")
(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
(match_operand:SF 2 "general_operand" "fmF,fmF"))
(match_operand:SF 3 "general_operand" "fmF,fmF")))]
***************
*** 883,902 ****
return \"adjspd %n0\";
}")
- (define_insn "*frame_addr"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
- (plus:SI (reg:SI 24)
- (match_operand:SI 1 "immediate_operand" "i")))]
- "GET_CODE (operands[1]) == CONST_INT"
- "addr %c1(fp),%0")
-
- (define_insn "*stack_addr"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
- (plus:SI (reg:SI 25)
- (match_operand:SI 1 "immediate_operand" "i")))]
- "GET_CODE (operands[1]) == CONST_INT"
- "addr %c1(sp),%0")
-
(define_insn "adddi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
(plus:DI (match_operand:DI 1 "general_operand" "%0")
--- 895,900 ----
***************
*** 940,948 ****
;; See Note 1
(define_insn "addsi3"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm&<")
! (plus:SI (match_operand:SI 1 "general_operand" "%0,r")
! (match_operand:SI 2 "general_operand" "g,i")))]
""
"*
{
--- 938,946 ----
;; See Note 1
(define_insn "addsi3"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm<,=rm<")
! (plus:SI (match_operand:SI 1 "general_operand" "%0,r,xy")
! (match_operand:SI 2 "general_operand" "g,i,i")))]
""
"*
{
***************
*** 964,969 ****
--- 962,975 ----
return \"addr %c2(%1),%0\";
}
}
+ else if (which_alternative == 2)
+ {
+ if (GET_CODE (operands[2]) == CONST_INT &&
+ NS32K_DISPLACEMENT_P (INTVAL (operands[2])))
+ return \"addr %c2(%1),%0\";
+ else
+ return \"sprd %1,%0\;addd %2,%0\";
+ }
else if (GET_CODE (operands[2]) == CONST_INT)
{
int i = INTVAL (operands[2]);
***************
*** 2313,2319 ****
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "blt %l0")
(define_insn "bltu"
[(set (pc)
--- 2319,2331 ----
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;blt %l0\;0:\";
! else
! return \"blt %l0\";
! }")
(define_insn "bltu"
[(set (pc)
***************
*** 2349,2355 ****
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "ble %l0")
(define_insn "bleu"
[(set (pc)
--- 2361,2373 ----
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;ble %l0\;0:\";
! else
! return \"ble %l0\";
! }")
(define_insn "bleu"
[(set (pc)
***************
*** 2399,2405 ****
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "ble %l0")
(define_insn "*bleu"
[(set (pc)
--- 2417,2429 ----
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;ble %l0\;0:\";
! else
! return \"ble %l0\";
! }")
(define_insn "*bleu"
[(set (pc)
***************
*** 2435,2441 ****
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "blt %l0")
(define_insn "*bltu"
[(set (pc)
--- 2459,2471 ----
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;blt %l0\;0:\";
! else
! return \"blt %l0\";
! }")
(define_insn "*bltu"
[(set (pc)
Index: config/ns32k/pc532.h
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/pc532.h,v
retrieving revision 1.1.1.1
diff -c -r1.1.1.1 pc532.h
*** config/ns32k/pc532.h 25 Nov 2001 13:34:22 -0000 1.1.1.1
--- config/ns32k/pc532.h 9 Jul 2002 14:02:02 -0000
***************
*** 26,32 ****
/* Compile for the floating point unit & 32532 by default;
also presume SB is zero and no bitfield instructions */
! #define TARGET_DEFAULT (1 + 24 + 64)
/* Write DBX debugging info for gdb to read */
--- 26,33 ----
/* Compile for the floating point unit & 32532 by default;
also presume SB is zero and no bitfield instructions */
! #undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_32381 | MASK_32532 | MASK_SB)
/* Write DBX debugging info for gdb to read */
Index: config/ns32k/sequent.h
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/sequent.h,v
retrieving revision 1.1.1.1
diff -c -r1.1.1.1 sequent.h
*** config/ns32k/sequent.h 25 Nov 2001 13:34:22 -0000 1.1.1.1
--- config/ns32k/sequent.h 9 Jul 2002 14:02:01 -0000
***************
*** 30,36 ****
/* Don't split DBX symbols into continuations. */
#define DBX_CONTIN_LENGTH 0
! #define TARGET_DEFAULT 9 /* 32332 with 32081 (guessing). */
/* Print subsidiary information on the compiler version in use. */
#undef TARGET_VERSION
--- 30,37 ----
/* Don't split DBX symbols into continuations. */
#define DBX_CONTIN_LENGTH 0
! #undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_32081 | MASK_32332)
/* Print subsidiary information on the compiler version in use. */
#undef TARGET_VERSION
Index: config/ns32k/tek6000.h
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/tek6000.h,v
retrieving revision 1.1.1.1
diff -c -r1.1.1.1 tek6000.h
*** config/ns32k/tek6000.h 25 Nov 2001 13:34:22 -0000 1.1.1.1
--- config/ns32k/tek6000.h 9 Jul 2002 14:02:02 -0000
***************
*** 85,91 ****
/* ------------------------------------------- */
! #define TARGET_DEFAULT 1
/* These control the C++ compiler somehow. */
#define FASCIST_ASSEMBLER
--- 85,92 ----
/* ------------------------------------------- */
! #undef TARGET_DEFAULT
! #define TARGET_DEFAULT (MASK_32081 | MASK_SB | MASK_BITFIELD)
/* These control the C++ compiler somehow. */
#define FASCIST_ASSEMBLER
Index: doc/invoke.texi
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.1.1.2
diff -c -r1.1.1.2 invoke.texi
*** doc/invoke.texi 3 Jun 2002 14:14:51 -0000 1.1.1.2
--- doc/invoke.texi 13 Jul 2002 13:29:32 -0000
***************
*** 8656,8661 ****
--- 8656,8670 ----
Generate output containing library calls for floating point.
@strong{Warning:} the requisite libraries may not be available.
+ @item -mieee-fp
+ @itemx -mno-ieee-fp
+ @opindex mieee-fp
+ @opindex mno-ieee-fp
+ Control whether or not the compiler uses IEEE floating point
+ comparisons. These handle correctly the case where the result of a
+ comparison is unordered.
+ @strong{Warning:} the requisite kernel support may not be available.
+
@item -mnobitfield
@opindex mnobitfield
Do not use the bit-field instructions. On some machines it is faster to
Index: testsuite/gcc.c-torture/execute/20010122-1.x
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/testsuite/gcc.c-torture/execute/20010122-1.x,v
retrieving revision 1.1.1.1
diff -c -r1.1.1.1 20010122-1.x
*** testsuite/gcc.c-torture/execute/20010122-1.x 30 Apr 2002 23:39:33 -0000 1.1.1.1
--- testsuite/gcc.c-torture/execute/20010122-1.x 3 Jul 2002 11:06:53 -0000
***************
*** 5,8 ****
--- 5,17 ----
set torture_execute_xfail "mips*-sgi-irix6*"
}
+ # This test relies on __builtin_return_address(1) returning something
+ # useful. This is not guaranteed to be be so, especially
+ # when the -fomit-frame-pointer flag is used.
+ # Do not test with -fomit-frame-pointer option.
+ set torture_eval_before_compile {
+ if {[string match {*-fomit-frame-pointer*} "$option"]} {
+ continue}
+ }
+
return 0
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: ns32k port patches
2002-07-13 7:14 ns32k port patches Ian Dall
@ 2002-07-13 11:23 ` Jason R Thorpe
2002-07-14 3:39 ` Ian Dall
2002-07-15 15:45 ` Richard Henderson
1 sibling, 1 reply; 7+ messages in thread
From: Jason R Thorpe @ 2002-07-13 11:23 UTC (permalink / raw)
To: Ian Dall; +Cc: gcc-patches
On Sat, Jul 13, 2002 at 11:19:45PM +0930, Ian Dall wrote:
> This patch for the ns32k port cleans up the machine dependent options.
> It adds a new -mieee-fp option with the same semantics as for i386 port.
> This requires kernel support and is off by default for most targets.
> It fixes up a case of incorrect code generation with -fomit-frame-pointer.
Which version of GCC are you working with? The "symbolic names for target
mask" I already checked into the mainline some time ago, and netbsd.h is
the only remaining target config.
--
-- Jason R. Thorpe <thorpej@wasabisystems.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: ns32k port patches
2002-07-13 11:23 ` Jason R Thorpe
@ 2002-07-14 3:39 ` Ian Dall
2002-07-15 5:39 ` Updated " Ian Dall
0 siblings, 1 reply; 7+ messages in thread
From: Ian Dall @ 2002-07-14 3:39 UTC (permalink / raw)
To: thorpej; +Cc: ian, gcc-patches
Jason R Thorpe writes:
> On Sat, Jul 13, 2002 at 11:19:45PM +0930, Ian Dall wrote:
>
> > This patch for the ns32k port cleans up the machine dependent options.
> > It adds a new -mieee-fp option with the same semantics as for i386 port.
> > This requires kernel support and is off by default for most targets.
> > It fixes up a case of incorrect code generation with -fomit-frame-pointer.
>
> Which version of GCC are you working with? The "symbolic names for target
> mask" I already checked into the mainline some time ago, and netbsd.h is
> the only remaining target config.
Ah, bugger.
I guess I am on the wrong branch.
cvs status ns32k.h shows:
Sticky Tag: gcc_latest_snapshot (revision: 1.33)
I guess that sticky tag means I am not on the mainline. I must admit I
am surprised by that gcc_latest_snapshot is not on the mainline, but
so be it.
I'll synchronize and resubmit.
Ian
^ permalink raw reply [flat|nested] 7+ messages in thread
* Updated ns32k port patches
2002-07-14 3:39 ` Ian Dall
@ 2002-07-15 5:39 ` Ian Dall
0 siblings, 0 replies; 7+ messages in thread
From: Ian Dall @ 2002-07-15 5:39 UTC (permalink / raw)
To: gcc-patches; +Cc: thorpej
Ian Dall writes:
> I guess I am on the wrong branch.
> [...]
> I'll synchronize and resubmit.
Here is the revised ChangeLog entry:
2002-07-13 Ian Dall <ian@sibyl.beware.dropbear.id.au>
* doc/invoke.texi (NS32K Options): Document -mieee-fp option
* config/ns32k/ns32k.md (addsi3, *frame_addr, *stack_addr): merge
into addsi3 using register class "x" and "y".
* config/ns32k/ns32k.md (*madddf, *maddsf, *msubdf, *msubsf):
"earlyclobber" constraint modifier for some alternative.
* config/ns32k/ns32k.md (tstdf, tstsf, cmpdf, cmpsf, blt, ble)
(*ble, *blt): Flag to indicate bCOND and sCOND should check for
unordered.
config/ns32k/ns32k.h (CC_UNORD): define corresponding mask.
* config/ns32k/ns32k.h (TARGET_IEEE_FP, MASK_IEEE_FP)
(TARGET_SWITCHES): Add -mieee-fp option.
(OVERRIDE_OPTIONS): 32332 is a subset of
32532. Don't use IEEE_FP -funsafe-math-optimizations.
(TARGET_SWITCHES): Fix description of bitfield option.
* config/ns32k/netbsd.h (TARGET_DEFAULT): Add
-mieee-fp option. Remove 32332 flag.
And here is the patch:
Index: doc/invoke.texi
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.1.1.3
retrieving revision 1.3
diff -c -r1.1.1.3 -r1.3
*** doc/invoke.texi 14 Jul 2002 12:28:22 -0000 1.1.1.3
--- doc/invoke.texi 14 Jul 2002 15:00:17 -0000 1.3
***************
*** 8693,8698 ****
--- 8693,8707 ----
Generate output containing library calls for floating point.
@strong{Warning:} the requisite libraries may not be available.
+ @item -mieee-fp
+ @itemx -mno-ieee-fp
+ @opindex mieee-fp
+ @opindex mno-ieee-fp
+ Control whether or not the compiler uses IEEE floating point
+ comparisons. These handle correctly the case where the result of a
+ comparison is unordered.
+ @strong{Warning:} the requisite kernel support may not be available.
+
@item -mnobitfield
@opindex mnobitfield
Do not use the bit-field instructions. On some machines it is faster to
Index: config/ns32k/netbsd.h
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/netbsd.h,v
retrieving revision 1.1.1.3
retrieving revision 1.3
diff -c -r1.1.1.3 -r1.3
*** config/ns32k/netbsd.h 14 Jul 2002 12:23:51 -0000 1.1.1.3
--- config/ns32k/netbsd.h 14 Jul 2002 15:00:05 -0000 1.3
***************
*** 34,42 ****
FPU is 32381;
Use multiply-add instructions */
#define TARGET_DEFAULT \
! (MASK_32532|MASK_32332 | MASK_NO_SB | MASK_NO_BITFIELD | \
! MASK_32081|MASK_32381 | MASK_MULT_ADD)
/* 32-bit alignment for efficiency */
--- 34,43 ----
FPU is 32381;
Use multiply-add instructions */
+ #undef TARGET_DEFAULT
#define TARGET_DEFAULT \
! (MASK_32532 | MASK_NO_SB | MASK_NO_BITFIELD | \
! MASK_32381 | MASK_IEEE_FP | MASK_MULT_ADD)
/* 32-bit alignment for efficiency */
Index: config/ns32k/ns32k.h
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/ns32k.h,v
retrieving revision 1.1.1.4
diff -c -r1.1.1.4 ns32k.h
*** config/ns32k/ns32k.h 14 Jul 2002 12:23:52 -0000 1.1.1.4
--- config/ns32k/ns32k.h 15 Jul 2002 12:05:16 -0000
***************
*** 82,87 ****
--- 82,88 ----
extern int target_flags;
+ /* Masks for target_flags */
#define MASK_32081 1
#define MASK_RTD 2
#define MASK_REGPARM 4
***************
*** 93,98 ****
--- 94,100 ----
#define MASK_32381 256
#define MASK_MULT_ADD 512
#define MASK_SRC 1024
+ #define MASK_IEEE_FP 2048
/* Macros used in the machine description to test the flags. */
***************
*** 121,137 ****
/* Ok to use the static base register (and presume it's 0) */
#define TARGET_SB ((target_flags & MASK_NO_SB) == 0)
#define TARGET_HIMEM (target_flags & MASK_HIMEM)
/* Compile using bitfield insns. */
#define TARGET_BITFIELD ((target_flags & MASK_NO_BITFIELD) == 0)
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
-
#define TARGET_SWITCHES \
{ { "32081", MASK_32081, N_("Use hardware fp")}, \
{ "soft-float", -(MASK_32081|MASK_32381), \
--- 123,141 ----
/* Ok to use the static base register (and presume it's 0) */
#define TARGET_SB ((target_flags & MASK_NO_SB) == 0)
+
#define TARGET_HIMEM (target_flags & MASK_HIMEM)
/* Compile using bitfield insns. */
#define TARGET_BITFIELD ((target_flags & MASK_NO_BITFIELD) == 0)
+ #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
+
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
{ { "32081", MASK_32081, N_("Use hardware fp")}, \
{ "soft-float", -(MASK_32081|MASK_32381), \
***************
*** 148,164 ****
N_("Register sb is zero. Use for absolute addressing")}, \
{ "nosb", MASK_NO_SB, N_("Do not use register sb")}, \
{ "bitfield", -MASK_NO_BITFIELD, \
N_("Do not use bit-field instructions")}, \
- { "nobitfield", MASK_NO_BITFIELD, N_("Use bit-field instructions")},\
{ "himem", MASK_HIMEM, N_("Generate code for high memory")}, \
{ "nohimem", -MASK_HIMEM, N_("Generate code for low memory")}, \
{ "32381", MASK_32381, N_("32381 fpu")}, \
{ "mult-add", MASK_MULT_ADD, \
N_("Use multiply-accumulate fp instructions")}, \
{ "nomult-add", -MASK_MULT_ADD, \
! N_("Do not use multiply-accumulate fp instructions") }, \
{ "src", MASK_SRC, N_("\"Small register classes\" kludge")}, \
{ "nosrc", -MASK_SRC, N_("No \"Small register classes\" kludge")}, \
{ "", TARGET_DEFAULT, 0}}
/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */
--- 152,172 ----
N_("Register sb is zero. Use for absolute addressing")}, \
{ "nosb", MASK_NO_SB, N_("Do not use register sb")}, \
{ "bitfield", -MASK_NO_BITFIELD, \
+ N_("Use bit-field instructions")}, \
+ { "nobitfield", MASK_NO_BITFIELD, \
N_("Do not use bit-field instructions")}, \
{ "himem", MASK_HIMEM, N_("Generate code for high memory")}, \
{ "nohimem", -MASK_HIMEM, N_("Generate code for low memory")}, \
{ "32381", MASK_32381, N_("32381 fpu")}, \
{ "mult-add", MASK_MULT_ADD, \
N_("Use multiply-accumulate fp instructions")}, \
{ "nomult-add", -MASK_MULT_ADD, \
! N_("Do not use multiply-accumulate fp instructions") }, \
{ "src", MASK_SRC, N_("\"Small register classes\" kludge")}, \
{ "nosrc", -MASK_SRC, N_("No \"Small register classes\" kludge")}, \
+ { "ieee-fp", MASK_IEEE_FP, N_("Use IEEE math for fp comparisons")}, \
+ { "noieee-fp", -MASK_IEEE_FP, \
+ N_("Do not use IEEE math for fp comparisons")}, \
{ "", TARGET_DEFAULT, 0}}
/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */
***************
*** 166,179 ****
/* When we are generating PIC, the sb is used as a pointer
to the GOT. 32381 is a superset of 32081 */
! #define OVERRIDE_OPTIONS \
! { \
! if (flag_pic || TARGET_HIMEM) \
! target_flags |= MASK_NO_SB; \
! if (TARGET_32381) \
! target_flags |= MASK_32081; \
! else \
! target_flags &= ~MASK_MULT_ADD; \
}
/* Zero or more C statements that may conditionally modify two
--- 174,191 ----
/* When we are generating PIC, the sb is used as a pointer
to the GOT. 32381 is a superset of 32081 */
! #define OVERRIDE_OPTIONS \
! { \
! if (target_flags & MASK_32532) \
! target_flags |= MASK_32332; \
! if (flag_pic || TARGET_HIMEM) \
! target_flags |= MASK_NO_SB; \
! if (TARGET_32381) \
! target_flags |= MASK_32081; \
! else \
! target_flags &= ~MASK_MULT_ADD; \
! if (flag_unsafe_math_optimizations) \
! target_flags &= ~MASK_IEEE_FP; \
}
/* Zero or more C statements that may conditionally modify two
***************
*** 1179,1184 ****
--- 1191,1200 ----
/* This bit means that what ought to be in the Z bit
is complemented in the F bit. */
#define CC_Z_IN_NOT_F 010000
+
+ /* This bit means that the L bit indicates unordered (IEEE) comparison.
+ */
+ #define CC_UNORD 020000
/* Store in cc_status the expressions
that the condition codes will describe
Index: config/ns32k/ns32k.md
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/ns32k.md,v
retrieving revision 1.1.1.3
retrieving revision 1.4
diff -c -r1.1.1.3 -r1.4
*** config/ns32k/ns32k.md 14 Jul 2002 12:23:52 -0000 1.1.1.3
--- config/ns32k/ns32k.md 13 Jul 2002 13:56:36 -0000 1.4
***************
*** 94,99 ****
--- 94,101 ----
"TARGET_32081"
"*
{ cc_status.flags |= CC_REVERSED;
+ if (TARGET_IEEE_FP)
+ cc_status.flags |= CC_UNORD;
operands[1] = CONST0_RTX (DFmode);
return \"cmpl %1,%0\"; }")
***************
*** 103,108 ****
--- 105,112 ----
"TARGET_32081"
"*
{ cc_status.flags |= CC_REVERSED;
+ if (TARGET_IEEE_FP)
+ cc_status.flags |= CC_UNORD;
operands[1] = CONST0_RTX (SFmode);
return \"cmpf %1,%0\"; }")
***************
*** 202,215 ****
(compare (match_operand:DF 0 "general_operand" "lmF")
(match_operand:DF 1 "general_operand" "lmF")))]
"TARGET_32081"
! "cmpl %0,%1")
(define_insn "cmpsf"
[(set (cc0)
(compare (match_operand:SF 0 "general_operand" "fmF")
(match_operand:SF 1 "general_operand" "fmF")))]
"TARGET_32081"
! "cmpf %0,%1")
\f
;; movdf and movsf copy between general and floating registers using
;; the stack. In principle, we could get better code not allowing
--- 206,227 ----
(compare (match_operand:DF 0 "general_operand" "lmF")
(match_operand:DF 1 "general_operand" "lmF")))]
"TARGET_32081"
! "*
! {
! if (TARGET_IEEE_FP)
! cc_status.flags |= CC_UNORD;
! return \"cmpl %0,%1\";}")
(define_insn "cmpsf"
[(set (cc0)
(compare (match_operand:SF 0 "general_operand" "fmF")
(match_operand:SF 1 "general_operand" "fmF")))]
"TARGET_32081"
! "*
! {
! if (TARGET_IEEE_FP)
! cc_status.flags |= CC_UNORD;
! return \"cmpf %0,%1\";}")
\f
;; movdf and movsf copy between general and floating registers using
;; the stack. In principle, we could get better code not allowing
***************
*** 798,804 ****
\f
;; Multiply-add instructions
(define_insn "*madddf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,lm")
(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
(match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
(match_operand:DF 3 "general_operand" "0,lmF,lmF")))]
--- 810,816 ----
\f
;; Multiply-add instructions
(define_insn "*madddf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,&lm")
(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
(match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
(match_operand:DF 3 "general_operand" "0,lmF,lmF")))]
***************
*** 809,815 ****
mull %2,%0\;addl %3,%0")
(define_insn "*maddsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,fm")
(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
(match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
(match_operand:SF 3 "general_operand" "0,fmF,fmF")))]
--- 821,827 ----
mull %2,%0\;addl %3,%0")
(define_insn "*maddsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,&fm")
(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
(match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
(match_operand:SF 3 "general_operand" "0,fmF,fmF")))]
***************
*** 822,828 ****
;; Multiply-sub instructions
(define_insn "*msubdf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=v,lm")
(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
(match_operand:DF 2 "general_operand" "lmF,lmF"))
(match_operand:DF 3 "general_operand" "lmF,lmF")))]
--- 834,840 ----
;; Multiply-sub instructions
(define_insn "*msubdf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=&v,&lm")
(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
(match_operand:DF 2 "general_operand" "lmF,lmF"))
(match_operand:DF 3 "general_operand" "lmF,lmF")))]
***************
*** 832,838 ****
mull %2,%0\;subl %3,%0")
(define_insn "*msubsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=u,fm")
(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
(match_operand:SF 2 "general_operand" "fmF,fmF"))
(match_operand:SF 3 "general_operand" "fmF,fmF")))]
--- 844,850 ----
mull %2,%0\;subl %3,%0")
(define_insn "*msubsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=&u,&fm")
(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
(match_operand:SF 2 "general_operand" "fmF,fmF"))
(match_operand:SF 3 "general_operand" "fmF,fmF")))]
***************
*** 883,902 ****
return \"adjspd %n0\";
}")
- (define_insn "*frame_addr"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
- (plus:SI (reg:SI 24)
- (match_operand:SI 1 "immediate_operand" "i")))]
- "GET_CODE (operands[1]) == CONST_INT"
- "addr %c1(fp),%0")
-
- (define_insn "*stack_addr"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
- (plus:SI (reg:SI 25)
- (match_operand:SI 1 "immediate_operand" "i")))]
- "GET_CODE (operands[1]) == CONST_INT"
- "addr %c1(sp),%0")
-
(define_insn "adddi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
(plus:DI (match_operand:DI 1 "general_operand" "%0")
--- 895,900 ----
***************
*** 940,948 ****
;; See Note 1
(define_insn "addsi3"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm&<")
! (plus:SI (match_operand:SI 1 "general_operand" "%0,r")
! (match_operand:SI 2 "general_operand" "g,i")))]
""
"*
{
--- 938,946 ----
;; See Note 1
(define_insn "addsi3"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm<,=rm<")
! (plus:SI (match_operand:SI 1 "general_operand" "%0,r,xy")
! (match_operand:SI 2 "general_operand" "g,i,i")))]
""
"*
{
***************
*** 964,969 ****
--- 962,975 ----
return \"addr %c2(%1),%0\";
}
}
+ else if (which_alternative == 2)
+ {
+ if (GET_CODE (operands[2]) == CONST_INT &&
+ NS32K_DISPLACEMENT_P (INTVAL (operands[2])))
+ return \"addr %c2(%1),%0\";
+ else
+ return \"sprd %1,%0\;addd %2,%0\";
+ }
else if (GET_CODE (operands[2]) == CONST_INT)
{
int i = INTVAL (operands[2]);
***************
*** 2313,2319 ****
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "blt %l0")
(define_insn "bltu"
[(set (pc)
--- 2319,2331 ----
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;blt %l0\;0:\";
! else
! return \"blt %l0\";
! }")
(define_insn "bltu"
[(set (pc)
***************
*** 2349,2355 ****
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "ble %l0")
(define_insn "bleu"
[(set (pc)
--- 2361,2373 ----
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;ble %l0\;0:\";
! else
! return \"ble %l0\";
! }")
(define_insn "bleu"
[(set (pc)
***************
*** 2399,2405 ****
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "ble %l0")
(define_insn "*bleu"
[(set (pc)
--- 2417,2429 ----
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;ble %l0\;0:\";
! else
! return \"ble %l0\";
! }")
(define_insn "*bleu"
[(set (pc)
***************
*** 2435,2441 ****
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "blt %l0")
(define_insn "*bltu"
[(set (pc)
--- 2459,2471 ----
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;blt %l0\;0:\";
! else
! return \"blt %l0\";
! }")
(define_insn "*bltu"
[(set (pc)
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: ns32k port patches
2002-07-13 7:14 ns32k port patches Ian Dall
2002-07-13 11:23 ` Jason R Thorpe
@ 2002-07-15 15:45 ` Richard Henderson
2002-07-16 5:58 ` Ian Dall
1 sibling, 1 reply; 7+ messages in thread
From: Richard Henderson @ 2002-07-15 15:45 UTC (permalink / raw)
To: Ian Dall; +Cc: gcc-patches
On Sat, Jul 13, 2002 at 11:19:45PM +0930, Ian Dall wrote:
> It adds a new -mieee-fp option with the same semantics as for i386 port.
The i386 port should have named the option "-mieee-compares"
or some such. Certainly the option doesn't affect all of
floating point.
Care to rename it?
r~
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: ns32k port patches
2002-07-15 15:45 ` Richard Henderson
@ 2002-07-16 5:58 ` Ian Dall
2002-07-16 10:48 ` Richard Henderson
0 siblings, 1 reply; 7+ messages in thread
From: Ian Dall @ 2002-07-16 5:58 UTC (permalink / raw)
To: rth; +Cc: gcc-patches
[-- Attachment #1: message body text --]
[-- Type: text/plain, Size: 1377 bytes --]
Richard Henderson writes:
> On Sat, Jul 13, 2002 at 11:19:45PM +0930, Ian Dall wrote:
> > It adds a new -mieee-fp option with the same semantics as for i386 port.
>
> The i386 port should have named the option "-mieee-compares"
> or some such. Certainly the option doesn't affect all of
> floating point.
>
> Care to rename it?
Yes, I was going for consistency over descriptiveness.
Ian
Here is a revised ChangeLog entry:
2002-07-13 Ian Dall <ian@sibyl.beware.dropbear.id.au>
* doc/invoke.texi (NS32K Options): Document -mieee-compare option
* config/ns32k/ns32k.md (addsi3, *frame_addr, *stack_addr): merge
into addsi3 using register class "x" and "y".
* config/ns32k/ns32k.md (*madddf, *maddsf, *msubdf, *msubsf):
"earlyclobber" constraint modifier for some alternative.
* config/ns32k/ns32k.md (tstdf, tstsf, cmpdf, cmpsf, blt, ble)
(*ble, *blt): Flag to indicate bCOND and sCOND should check for
unordered.
config/ns32k/ns32k.h (CC_UNORD): define corresponding mask.
* config/ns32k/ns32k.h (TARGET_IEEE_COMPARE, MASK_IEEE_COMPARE)
(TARGET_SWITCHES): Add -mieee-compare option.
(OVERRIDE_OPTIONS): 32332 is a subset of
32532. Don't use IEEE_COMPARE -funsafe-math-optimizations.
(TARGET_SWITCHES): Fix description of bitfield option.
* config/ns32k/netbsd.h (TARGET_DEFAULT): Add
-mieee-compare option. Remove 32332 flag.
and patch:
[-- Attachment #2: patch --]
[-- Type: text/plain, Size: 15973 bytes --]
Index: doc/invoke.texi
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.1.1.3
diff -c -r1.1.1.3 invoke.texi
*** doc/invoke.texi 14 Jul 2002 12:28:22 -0000 1.1.1.3
--- doc/invoke.texi 16 Jul 2002 12:19:10 -0000
***************
*** 8693,8698 ****
--- 8693,8707 ----
Generate output containing library calls for floating point.
@strong{Warning:} the requisite libraries may not be available.
+ @item -mieee-compare
+ @itemx -mno-ieee-compare
+ @opindex mieee-compare
+ @opindex mno-ieee-compare
+ Control whether or not the compiler uses IEEE floating point
+ comparisons. These handle correctly the case where the result of a
+ comparison is unordered.
+ @strong{Warning:} the requisite kernel support may not be available.
+
@item -mnobitfield
@opindex mnobitfield
Do not use the bit-field instructions. On some machines it is faster to
Index: config/ns32k/netbsd.h
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/netbsd.h,v
retrieving revision 1.1.1.3
diff -c -r1.1.1.3 netbsd.h
*** config/ns32k/netbsd.h 14 Jul 2002 12:23:51 -0000 1.1.1.3
--- config/ns32k/netbsd.h 16 Jul 2002 12:17:33 -0000
***************
*** 34,42 ****
FPU is 32381;
Use multiply-add instructions */
#define TARGET_DEFAULT \
! (MASK_32532|MASK_32332 | MASK_NO_SB | MASK_NO_BITFIELD | \
! MASK_32081|MASK_32381 | MASK_MULT_ADD)
/* 32-bit alignment for efficiency */
--- 34,43 ----
FPU is 32381;
Use multiply-add instructions */
+ #undef TARGET_DEFAULT
#define TARGET_DEFAULT \
! (MASK_32532 | MASK_NO_SB | MASK_NO_BITFIELD | \
! MASK_32381 | MASK_IEEE_COMPARE | MASK_MULT_ADD)
/* 32-bit alignment for efficiency */
Index: config/ns32k/ns32k.h
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/ns32k.h,v
retrieving revision 1.1.1.4
diff -c -r1.1.1.4 ns32k.h
*** config/ns32k/ns32k.h 14 Jul 2002 12:23:52 -0000 1.1.1.4
--- config/ns32k/ns32k.h 16 Jul 2002 12:17:32 -0000
***************
*** 82,87 ****
--- 82,88 ----
extern int target_flags;
+ /* Masks for target_flags */
#define MASK_32081 1
#define MASK_RTD 2
#define MASK_REGPARM 4
***************
*** 93,98 ****
--- 94,100 ----
#define MASK_32381 256
#define MASK_MULT_ADD 512
#define MASK_SRC 1024
+ #define MASK_IEEE_COMPARE 2048
/* Macros used in the machine description to test the flags. */
***************
*** 121,137 ****
/* Ok to use the static base register (and presume it's 0) */
#define TARGET_SB ((target_flags & MASK_NO_SB) == 0)
#define TARGET_HIMEM (target_flags & MASK_HIMEM)
/* Compile using bitfield insns. */
#define TARGET_BITFIELD ((target_flags & MASK_NO_BITFIELD) == 0)
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
-
#define TARGET_SWITCHES \
{ { "32081", MASK_32081, N_("Use hardware fp")}, \
{ "soft-float", -(MASK_32081|MASK_32381), \
--- 123,141 ----
/* Ok to use the static base register (and presume it's 0) */
#define TARGET_SB ((target_flags & MASK_NO_SB) == 0)
+
#define TARGET_HIMEM (target_flags & MASK_HIMEM)
/* Compile using bitfield insns. */
#define TARGET_BITFIELD ((target_flags & MASK_NO_BITFIELD) == 0)
+ #define TARGET_IEEE_FP (target_flags & MASK_IEEE_COMPARE)
+
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
where VALUE is the bits to set or minus the bits to clear.
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
{ { "32081", MASK_32081, N_("Use hardware fp")}, \
{ "soft-float", -(MASK_32081|MASK_32381), \
***************
*** 148,164 ****
N_("Register sb is zero. Use for absolute addressing")}, \
{ "nosb", MASK_NO_SB, N_("Do not use register sb")}, \
{ "bitfield", -MASK_NO_BITFIELD, \
N_("Do not use bit-field instructions")}, \
- { "nobitfield", MASK_NO_BITFIELD, N_("Use bit-field instructions")},\
{ "himem", MASK_HIMEM, N_("Generate code for high memory")}, \
{ "nohimem", -MASK_HIMEM, N_("Generate code for low memory")}, \
{ "32381", MASK_32381, N_("32381 fpu")}, \
{ "mult-add", MASK_MULT_ADD, \
N_("Use multiply-accumulate fp instructions")}, \
{ "nomult-add", -MASK_MULT_ADD, \
! N_("Do not use multiply-accumulate fp instructions") }, \
{ "src", MASK_SRC, N_("\"Small register classes\" kludge")}, \
{ "nosrc", -MASK_SRC, N_("No \"Small register classes\" kludge")}, \
{ "", TARGET_DEFAULT, 0}}
/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */
--- 152,172 ----
N_("Register sb is zero. Use for absolute addressing")}, \
{ "nosb", MASK_NO_SB, N_("Do not use register sb")}, \
{ "bitfield", -MASK_NO_BITFIELD, \
+ N_("Use bit-field instructions")}, \
+ { "nobitfield", MASK_NO_BITFIELD, \
N_("Do not use bit-field instructions")}, \
{ "himem", MASK_HIMEM, N_("Generate code for high memory")}, \
{ "nohimem", -MASK_HIMEM, N_("Generate code for low memory")}, \
{ "32381", MASK_32381, N_("32381 fpu")}, \
{ "mult-add", MASK_MULT_ADD, \
N_("Use multiply-accumulate fp instructions")}, \
{ "nomult-add", -MASK_MULT_ADD, \
! N_("Do not use multiply-accumulate fp instructions") }, \
{ "src", MASK_SRC, N_("\"Small register classes\" kludge")}, \
{ "nosrc", -MASK_SRC, N_("No \"Small register classes\" kludge")}, \
+ { "ieee-compare", MASK_IEEE_COMPARE, N_("Use IEEE math for fp comparisons")}, \
+ { "noieee-compare", -MASK_IEEE_COMPARE, \
+ N_("Do not use IEEE math for fp comparisons")}, \
{ "", TARGET_DEFAULT, 0}}
/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */
***************
*** 166,179 ****
/* When we are generating PIC, the sb is used as a pointer
to the GOT. 32381 is a superset of 32081 */
! #define OVERRIDE_OPTIONS \
! { \
! if (flag_pic || TARGET_HIMEM) \
! target_flags |= MASK_NO_SB; \
! if (TARGET_32381) \
! target_flags |= MASK_32081; \
! else \
! target_flags &= ~MASK_MULT_ADD; \
}
/* Zero or more C statements that may conditionally modify two
--- 174,191 ----
/* When we are generating PIC, the sb is used as a pointer
to the GOT. 32381 is a superset of 32081 */
! #define OVERRIDE_OPTIONS \
! { \
! if (target_flags & MASK_32532) \
! target_flags |= MASK_32332; \
! if (flag_pic || TARGET_HIMEM) \
! target_flags |= MASK_NO_SB; \
! if (TARGET_32381) \
! target_flags |= MASK_32081; \
! else \
! target_flags &= ~MASK_MULT_ADD; \
! if (flag_unsafe_math_optimizations) \
! target_flags &= ~MASK_IEEE_COMPARE; \
}
/* Zero or more C statements that may conditionally modify two
***************
*** 1179,1184 ****
--- 1191,1200 ----
/* This bit means that what ought to be in the Z bit
is complemented in the F bit. */
#define CC_Z_IN_NOT_F 010000
+
+ /* This bit means that the L bit indicates unordered (IEEE) comparison.
+ */
+ #define CC_UNORD 020000
/* Store in cc_status the expressions
that the condition codes will describe
Index: config/ns32k/ns32k.md
===================================================================
RCS file: /usr/local/cvs-rep/gcc/gcc/config/ns32k/ns32k.md,v
retrieving revision 1.1.1.3
diff -c -r1.1.1.3 ns32k.md
*** config/ns32k/ns32k.md 14 Jul 2002 12:23:52 -0000 1.1.1.3
--- config/ns32k/ns32k.md 16 Jul 2002 12:17:31 -0000
***************
*** 94,99 ****
--- 94,101 ----
"TARGET_32081"
"*
{ cc_status.flags |= CC_REVERSED;
+ if (TARGET_IEEE_COMPARE)
+ cc_status.flags |= CC_UNORD;
operands[1] = CONST0_RTX (DFmode);
return \"cmpl %1,%0\"; }")
***************
*** 103,108 ****
--- 105,112 ----
"TARGET_32081"
"*
{ cc_status.flags |= CC_REVERSED;
+ if (TARGET_IEEE_COMPARE)
+ cc_status.flags |= CC_UNORD;
operands[1] = CONST0_RTX (SFmode);
return \"cmpf %1,%0\"; }")
***************
*** 202,215 ****
(compare (match_operand:DF 0 "general_operand" "lmF")
(match_operand:DF 1 "general_operand" "lmF")))]
"TARGET_32081"
! "cmpl %0,%1")
(define_insn "cmpsf"
[(set (cc0)
(compare (match_operand:SF 0 "general_operand" "fmF")
(match_operand:SF 1 "general_operand" "fmF")))]
"TARGET_32081"
! "cmpf %0,%1")
\f
;; movdf and movsf copy between general and floating registers using
;; the stack. In principle, we could get better code not allowing
--- 206,227 ----
(compare (match_operand:DF 0 "general_operand" "lmF")
(match_operand:DF 1 "general_operand" "lmF")))]
"TARGET_32081"
! "*
! {
! if (TARGET_IEEE_COMPARE)
! cc_status.flags |= CC_UNORD;
! return \"cmpl %0,%1\";}")
(define_insn "cmpsf"
[(set (cc0)
(compare (match_operand:SF 0 "general_operand" "fmF")
(match_operand:SF 1 "general_operand" "fmF")))]
"TARGET_32081"
! "*
! {
! if (TARGET_IEEE_COMPARE)
! cc_status.flags |= CC_UNORD;
! return \"cmpf %0,%1\";}")
\f
;; movdf and movsf copy between general and floating registers using
;; the stack. In principle, we could get better code not allowing
***************
*** 798,804 ****
\f
;; Multiply-add instructions
(define_insn "*madddf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,lm")
(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
(match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
(match_operand:DF 3 "general_operand" "0,lmF,lmF")))]
--- 810,816 ----
\f
;; Multiply-add instructions
(define_insn "*madddf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,&lm")
(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
(match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
(match_operand:DF 3 "general_operand" "0,lmF,lmF")))]
***************
*** 809,815 ****
mull %2,%0\;addl %3,%0")
(define_insn "*maddsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,fm")
(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
(match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
(match_operand:SF 3 "general_operand" "0,fmF,fmF")))]
--- 821,827 ----
mull %2,%0\;addl %3,%0")
(define_insn "*maddsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,&fm")
(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
(match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
(match_operand:SF 3 "general_operand" "0,fmF,fmF")))]
***************
*** 822,828 ****
;; Multiply-sub instructions
(define_insn "*msubdf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=v,lm")
(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
(match_operand:DF 2 "general_operand" "lmF,lmF"))
(match_operand:DF 3 "general_operand" "lmF,lmF")))]
--- 834,840 ----
;; Multiply-sub instructions
(define_insn "*msubdf"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=&v,&lm")
(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
(match_operand:DF 2 "general_operand" "lmF,lmF"))
(match_operand:DF 3 "general_operand" "lmF,lmF")))]
***************
*** 832,838 ****
mull %2,%0\;subl %3,%0")
(define_insn "*msubsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=u,fm")
(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
(match_operand:SF 2 "general_operand" "fmF,fmF"))
(match_operand:SF 3 "general_operand" "fmF,fmF")))]
--- 844,850 ----
mull %2,%0\;subl %3,%0")
(define_insn "*msubsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=&u,&fm")
(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
(match_operand:SF 2 "general_operand" "fmF,fmF"))
(match_operand:SF 3 "general_operand" "fmF,fmF")))]
***************
*** 883,902 ****
return \"adjspd %n0\";
}")
- (define_insn "*frame_addr"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
- (plus:SI (reg:SI 24)
- (match_operand:SI 1 "immediate_operand" "i")))]
- "GET_CODE (operands[1]) == CONST_INT"
- "addr %c1(fp),%0")
-
- (define_insn "*stack_addr"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
- (plus:SI (reg:SI 25)
- (match_operand:SI 1 "immediate_operand" "i")))]
- "GET_CODE (operands[1]) == CONST_INT"
- "addr %c1(sp),%0")
-
(define_insn "adddi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
(plus:DI (match_operand:DI 1 "general_operand" "%0")
--- 895,900 ----
***************
*** 940,948 ****
;; See Note 1
(define_insn "addsi3"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm&<")
! (plus:SI (match_operand:SI 1 "general_operand" "%0,r")
! (match_operand:SI 2 "general_operand" "g,i")))]
""
"*
{
--- 938,946 ----
;; See Note 1
(define_insn "addsi3"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm<,=rm<")
! (plus:SI (match_operand:SI 1 "general_operand" "%0,r,xy")
! (match_operand:SI 2 "general_operand" "g,i,i")))]
""
"*
{
***************
*** 964,969 ****
--- 962,975 ----
return \"addr %c2(%1),%0\";
}
}
+ else if (which_alternative == 2)
+ {
+ if (GET_CODE (operands[2]) == CONST_INT &&
+ NS32K_DISPLACEMENT_P (INTVAL (operands[2])))
+ return \"addr %c2(%1),%0\";
+ else
+ return \"sprd %1,%0\;addd %2,%0\";
+ }
else if (GET_CODE (operands[2]) == CONST_INT)
{
int i = INTVAL (operands[2]);
***************
*** 2313,2319 ****
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "blt %l0")
(define_insn "bltu"
[(set (pc)
--- 2319,2331 ----
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;blt %l0\;0:\";
! else
! return \"blt %l0\";
! }")
(define_insn "bltu"
[(set (pc)
***************
*** 2349,2355 ****
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "ble %l0")
(define_insn "bleu"
[(set (pc)
--- 2361,2373 ----
(label_ref (match_operand 0 "" ""))
(pc)))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;ble %l0\;0:\";
! else
! return \"ble %l0\";
! }")
(define_insn "bleu"
[(set (pc)
***************
*** 2399,2405 ****
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "ble %l0")
(define_insn "*bleu"
[(set (pc)
--- 2417,2429 ----
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;ble %l0\;0:\";
! else
! return \"ble %l0\";
! }")
(define_insn "*bleu"
[(set (pc)
***************
*** 2435,2441 ****
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "blt %l0")
(define_insn "*bltu"
[(set (pc)
--- 2459,2471 ----
(pc)
(label_ref (match_operand 0 "" ""))))]
""
! "*
! {
! if (cc_prev_status.flags & CC_UNORD)
! return \"bhi 0f\;blt %l0\;0:\";
! else
! return \"blt %l0\";
! }")
(define_insn "*bltu"
[(set (pc)
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: ns32k port patches
2002-07-16 5:58 ` Ian Dall
@ 2002-07-16 10:48 ` Richard Henderson
0 siblings, 0 replies; 7+ messages in thread
From: Richard Henderson @ 2002-07-16 10:48 UTC (permalink / raw)
To: Ian Dall; +Cc: gcc-patches
Applied.
r~
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2002-07-16 17:46 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2002-07-13 7:14 ns32k port patches Ian Dall
2002-07-13 11:23 ` Jason R Thorpe
2002-07-14 3:39 ` Ian Dall
2002-07-15 5:39 ` Updated " Ian Dall
2002-07-15 15:45 ` Richard Henderson
2002-07-16 5:58 ` Ian Dall
2002-07-16 10:48 ` Richard Henderson
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