* Enable more patterns for powerpc64
@ 2002-07-24 16:48 Alan Modra
2002-07-24 20:03 ` David Edelsohn
2002-07-25 18:37 ` David Edelsohn
0 siblings, 2 replies; 4+ messages in thread
From: Alan Modra @ 2002-07-24 16:48 UTC (permalink / raw)
To: gcc-patches; +Cc: David Edelsohn
Many of the SImode instruction patterns using rlwinm in rs6000.md are
currently disabled for PowerPC64, no doubt due to the problem of a
mask wrapping over the high 32 bits. Now that mask_operand checks
for this case, it's safe to use them, as in fact we've been doing
for months on powerpc64-linux. I noticed the extzvsi attribute
problem last night, so that change hasn't had the benefit of months of
testing, but survives bootstrap and reg testing on powerpc-linux.
* config/rs6000/rs6000.md: Enable patterns using rlwinm for
PowerPC64. Replace "T" and "S" constraints with "i" when the
predicate will do. Formatting fixes.
(extzvsi_internal1): Correct attr.
(extzvsi_internal2): Use "andi.", "andis." as for extzvsi_internal1.
Correct attr.
diff -urp -x'*~' gcc-3.2-orig/gcc/config/rs6000/rs6000.md gcc-3.2/gcc/config/rs6000/rs6000.md
--- gcc-3.2-orig/gcc/config/rs6000/rs6000.md 2002-07-24 16:49:15.000000000 +0930
+++ gcc-3.2/gcc/config/rs6000/rs6000.md 2002-07-24 23:35:38.000000000 +0930
@@ -3760,7 +3760,7 @@
(match_operand:SI 3 "const_int_operand" "i,i"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r,r"))]
- "! TARGET_POWERPC64"
+ ""
"*
{
int start = INTVAL (operands[3]) & 31;
@@ -3792,7 +3792,13 @@
operands[3] = GEN_INT (start + size);
return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
}"
- [(set_attr "type" "compare")
+ [(set (attr "type")
+ (if_then_else (ior (and (gt (match_dup 3) (const_int 0))
+ (le (plus (match_dup 3) (match_dup 2))
+ (const_int 16)))
+ (ge (match_dup 3) (const_int 16)))
+ (const_string "compare")
+ (const_string "delayed_compare")))
(set_attr "length" "4,8")])
(define_split
@@ -3802,7 +3808,7 @@
(match_operand:SI 3 "const_int_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
- "! TARGET_POWERPC64 && reload_completed"
+ "reload_completed"
[(set (match_dup 4)
(zero_extract:SI (match_dup 1) (match_dup 2)
(match_dup 3)))
@@ -3819,7 +3825,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
- "! TARGET_POWERPC64"
+ ""
"*
{
int start = INTVAL (operands[3]) & 31;
@@ -3829,10 +3835,14 @@
if (which_alternative == 1)
return \"#\";
- if (start >= 16 && start + size == 32)
+ if ((start > 0 && start + size <= 16) || start >= 16)
{
- operands[3] = GEN_INT ((1 << (32 - start)) - 1);
- return \"{andil.|andi.} %0,%1,%3\";
+ operands[3] = GEN_INT (((1 << (16 - (start & 15)))
+ - (1 << (16 - (start & 15) - size))));
+ if (start < 16)
+ return \"{andiu.|andis.} %0,%1,%3\";
+ else
+ return \"{andil.|andi.} %0,%1,%3\";
}
if (start + size >= 32)
@@ -3841,7 +3851,13 @@
operands[3] = GEN_INT (start + size);
return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
}"
- [(set_attr "type" "delayed_compare")
+ [(set (attr "type")
+ (if_then_else (ior (and (gt (match_dup 3) (const_int 0))
+ (le (plus (match_dup 3) (match_dup 2))
+ (const_int 16)))
+ (ge (match_dup 3) (const_int 16)))
+ (const_string "compare")
+ (const_string "delayed_compare")))
(set_attr "length" "4,8")])
(define_split
@@ -3852,7 +3868,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
- "! TARGET_POWERPC64 && reload_completed"
+ "reload_completed"
[(set (match_dup 0)
(zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
(set (match_dup 4)
@@ -3935,7 +3951,7 @@
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r"))]
- "! TARGET_POWERPC64"
+ ""
"@
{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
#"
@@ -3948,7 +3964,7 @@
(match_operand:SI 2 "reg_or_cint_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 3 ""))]
- "! TARGET_POWERPC64 && reload_completed"
+ "reload_completed"
[(set (match_dup 3)
(rotate:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0)
@@ -3963,7 +3979,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(rotate:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWERPC64"
+ ""
"@
{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
#"
@@ -3977,7 +3993,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(rotate:SI (match_dup 1) (match_dup 2)))]
- "! TARGET_POWERPC64 && reload_completed"
+ "reload_completed"
[(set (match_dup 0)
(rotate:SI (match_dup 1) (match_dup 2)))
(set (match_dup 3)
@@ -3989,7 +4005,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
- (match_operand:SI 3 "mask_operand" "T")))]
+ (match_operand:SI 3 "mask_operand" "i")))]
""
"{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
@@ -3998,10 +4014,10 @@
(compare:CC (and:SI
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
- (match_operand:SI 3 "mask_operand" "T,T"))
+ (match_operand:SI 3 "mask_operand" "i,i"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r,r"))]
- "! TARGET_POWERPC64"
+ ""
"@
{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
#"
@@ -4016,7 +4032,7 @@
(match_operand:SI 3 "mask_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
- "! TARGET_POWERPC64 && reload_completed"
+ "reload_completed"
[(set (match_dup 4)
(and:SI (rotate:SI (match_dup 1)
(match_dup 2))
@@ -4031,11 +4047,11 @@
(compare:CC (and:SI
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
- (match_operand:SI 3 "mask_operand" "T,T"))
+ (match_operand:SI 3 "mask_operand" "i,i"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "! TARGET_POWERPC64"
+ ""
"@
{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
#"
@@ -4051,7 +4067,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "! TARGET_POWERPC64 && reload_completed"
+ "reload_completed"
[(set (match_dup 0)
(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
@@ -4369,7 +4385,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:SI 3 "mask_operand" "T")))]
+ (match_operand:SI 3 "mask_operand" "i")))]
"includes_lshift_p (operands[2], operands[3])"
"{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
@@ -4378,10 +4394,10 @@
(compare:CC
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:SI 3 "mask_operand" "T,T"))
+ (match_operand:SI 3 "mask_operand" "i,i"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r,r"))]
- "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
+ "includes_lshift_p (operands[2], operands[3])"
"@
{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
#"
@@ -4396,7 +4412,7 @@
(match_operand:SI 3 "mask_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
- "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
+ "includes_lshift_p (operands[2], operands[3]) && reload_completed"
[(set (match_dup 4)
(and:SI (ashift:SI (match_dup 1) (match_dup 2))
(match_dup 3)))
@@ -4410,11 +4426,11 @@
(compare:CC
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:SI 3 "mask_operand" "T,T"))
+ (match_operand:SI 3 "mask_operand" "i,i"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
+ "includes_lshift_p (operands[2], operands[3])"
"@
{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
#"
@@ -4430,7 +4446,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
+ "includes_lshift_p (operands[2], operands[3]) && reload_completed"
[(set (match_dup 0)
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
@@ -4608,7 +4624,7 @@
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:SI 3 "mask_operand" "T")))]
+ (match_operand:SI 3 "mask_operand" "i")))]
"includes_rshift_p (operands[2], operands[3])"
"{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
@@ -4617,10 +4633,10 @@
(compare:CC
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:SI 3 "mask_operand" "T,T"))
+ (match_operand:SI 3 "mask_operand" "i,i"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r,r"))]
- "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
+ "includes_rshift_p (operands[2], operands[3])"
"@
{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
#"
@@ -4635,7 +4651,7 @@
(match_operand:SI 3 "mask_operand" ""))
(const_int 0)))
(clobber (match_scratch:SI 4 ""))]
- "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
+ "includes_rshift_p (operands[2], operands[3]) && reload_completed"
[(set (match_dup 4)
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
(match_dup 3)))
@@ -4649,11 +4665,11 @@
(compare:CC
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:SI 3 "mask_operand" "T,T"))
+ (match_operand:SI 3 "mask_operand" "i,i"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
+ "includes_rshift_p (operands[2], operands[3])"
"@
{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
#"
@@ -4669,7 +4685,7 @@
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
+ "includes_rshift_p (operands[2], operands[3]) && reload_completed"
[(set (match_dup 0)
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
(set (match_dup 4)
@@ -6698,7 +6714,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_cint_operand" "ri"))
- (match_operand:DI 3 "mask64_operand" "S")))]
+ (match_operand:DI 3 "mask64_operand" "i")))]
"TARGET_POWERPC64"
"rld%I2c%B3 %0,%1,%H2,%S3")
@@ -6707,7 +6723,7 @@
(compare:CC (and:DI
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
- (match_operand:DI 3 "mask64_operand" "S,S"))
+ (match_operand:DI 3 "mask64_operand" "i,i"))
(const_int 0)))
(clobber (match_scratch:DI 4 "=r,r"))]
"TARGET_POWERPC64"
@@ -6740,7 +6756,7 @@
(compare:CC (and:DI
(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
- (match_operand:DI 3 "mask64_operand" "S,S"))
+ (match_operand:DI 3 "mask64_operand" "i,i"))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
@@ -7155,7 +7171,7 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:DI 3 "mask64_operand" "S")))]
+ (match_operand:DI 3 "mask64_operand" "i")))]
"TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
"rldicr %0,%1,%H2,%S3")
@@ -7164,7 +7180,7 @@
(compare:CC
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:DI 3 "mask64_operand" "S,S"))
+ (match_operand:DI 3 "mask64_operand" "i,i"))
(const_int 0)))
(clobber (match_scratch:DI 4 "=r,r"))]
"TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
@@ -7197,7 +7213,7 @@
(compare:CC
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "const_int_operand" "i,i"))
- (match_operand:DI 3 "mask64_operand" "S,S"))
+ (match_operand:DI 3 "mask64_operand" "i,i"))
(const_int 0)))
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
@@ -11059,7 +11075,7 @@
(set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
(match_dup 3)))]
- "! TARGET_POWERPC64"
+ ""
"*
{
int is_bit = ccr_bit (operands[1], 1);
@@ -11094,7 +11110,7 @@
(set (match_operand:SI 4 "gpc_reg_operand" "")
(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
(match_dup 3)))]
- "! TARGET_POWERPC64 && reload_completed"
+ "reload_completed"
[(set (match_dup 4)
(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
(match_dup 3)))
@@ -11460,9 +11476,9 @@
(clobber (match_scratch:SI 4 ""))]
"! TARGET_POWERPC64 && reload_completed"
[(parallel [(set (match_dup 3)
- (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
- (const_int 31))
- (match_dup 2)))
+ (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
+ (const_int 31))
+ (match_dup 2)))
(clobber (match_dup 4))])
(set (match_dup 0)
(compare:CC (match_dup 3)
@@ -14945,7 +14961,6 @@
(define_insn "altivec_vmrglb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
-
(parallel [(const_int 0)
(const_int 1)
(const_int 2)
--
Alan Modra
IBM OzLabs - Linux Technology Centre
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Enable more patterns for powerpc64
2002-07-24 16:48 Enable more patterns for powerpc64 Alan Modra
@ 2002-07-24 20:03 ` David Edelsohn
2002-07-25 2:15 ` Alan Modra
2002-07-25 18:37 ` David Edelsohn
1 sibling, 1 reply; 4+ messages in thread
From: David Edelsohn @ 2002-07-24 20:03 UTC (permalink / raw)
To: Alan Modra; +Cc: gcc-patches
Replace "T" and "S" constraints with "i" when the predicate will do.
I thought that this was going to change to "n", not "i".
David
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Enable more patterns for powerpc64
2002-07-24 20:03 ` David Edelsohn
@ 2002-07-25 2:15 ` Alan Modra
0 siblings, 0 replies; 4+ messages in thread
From: Alan Modra @ 2002-07-25 2:15 UTC (permalink / raw)
To: David Edelsohn; +Cc: gcc-patches
On Wed, Jul 24, 2002 at 09:58:29PM -0400, David Edelsohn wrote:
> Replace "T" and "S" constraints with "i" when the predicate will do.
>
> I thought that this was going to change to "n", not "i".
We've been using "i", but I'm quite happy with "n" too. In fact,
even an "X" should work, as the predicate does all the checking
necessary. The main idea in not using "S" or "T" is to avoid
calling the predicate again, as that is what rs6000.h
EXTRA_CONSTRAINT does.
--
Alan Modra
IBM OzLabs - Linux Technology Centre
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Enable more patterns for powerpc64
2002-07-24 16:48 Enable more patterns for powerpc64 Alan Modra
2002-07-24 20:03 ` David Edelsohn
@ 2002-07-25 18:37 ` David Edelsohn
1 sibling, 0 replies; 4+ messages in thread
From: David Edelsohn @ 2002-07-25 18:37 UTC (permalink / raw)
To: Alan Modra; +Cc: gcc-patches
* config/rs6000/rs6000.md: Enable patterns using rlwinm for
PowerPC64. Replace "T" and "S" constraints with "i" when the
predicate will do. Formatting fixes.
(extzvsi_internal2): Use "andi.", "andis." as for extzvsi_internal1.
Please change constraint "i" to constraint "n" and remove the
compare/delayed_compare attr complexity. Then it's okay to commit.
Thanks, David
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2002-07-26 1:22 UTC | newest]
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2002-07-24 16:48 Enable more patterns for powerpc64 Alan Modra
2002-07-24 20:03 ` David Edelsohn
2002-07-25 2:15 ` Alan Modra
2002-07-25 18:37 ` David Edelsohn
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