* patch applied to sh port: suppress some warnings.
@ 2002-07-18 12:30 Joern Rennecke
2002-08-08 6:37 ` Alexandre Oliva
0 siblings, 1 reply; 6+ messages in thread
From: Joern Rennecke @ 2002-07-18 12:30 UTC (permalink / raw)
To: gcc-patches
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SuperH
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330
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Thu Jul 18 19:39:18 2002 J"orn Rennecke <joern.rennecke@superh.com>
* sh-protos.h (sh_expand_unop_v2sf): Move inside #ifdef RTX_CODE guard.
(sh_expand_binop_v2sf): Likewise.
* sh.c (machine_dependent_reorg): Add move for UNSPEC_MOVA.
(int_gpr_dest, trunc_hi_operand): New functions.
* sh.h (PREDICATE_CODES): Add any_register_operand, int_gpr_dest and
trunc_hi_operand.
(SPECIAL_MODE_PREDICATES, any_register_operand): Define.
* sh.md (cmpeqdi_t+1): Remove comments that genrecog warns about.
(adddi3_compact+1, subdi3_compact+1, ashlsi3_n+1, ashlhi3+1): Likewise.
(ashrsi2_16+1, ashrsi2_31+1, lshrsi3_n+1, ashrdi3+[12]): Likewise.
(and_shl_scratch+[12], zero_extendhidi2+1): Likewise.
(zero_extendhisi2_media+1, extendhidi2+1, extendqidi2+1): Likewise.
(extendhisi2_media+1, extendqisi2_media+1): Likewise.
(movsi_media_nofpu+[12], movhi_media+1, movdi_media_nofpu+1): Likewise.
(movdi_const_16bit+[12], movdf_i4+[123], reload_outdf+[2-5]): Likewise.
(movsf_ie+1): Likewise.
(loaddi_trunc): Use int_gpr_dest predicate.
(use_sfunc_addr, indirect_jump_scratch, sibcall_compact): Add mode(s).
(mova, mova_const, GOTaddr2picreg, ptrel, casesi_worker_0): Likewise.
(casesi_worker_0+[12], casesi_worker): Likewise.
(shcompact_preserve_incoming_args): Likewise.
(mov_nop): Use any_register_operand predicate.
(mperm_w0): Use trunc_hi_operand predicate.
Index: config/sh/sh-protos.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh-protos.h,v
retrieving revision 1.29
diff -p -r1.29 sh-protos.h
*** config/sh/sh-protos.h 17 Jul 2002 15:43:17 -0000 1.29
--- config/sh/sh-protos.h 18 Jul 2002 18:38:41 -0000
*************** extern void expand_df_binop PARAMS ((rtx
*** 100,105 ****
--- 100,107 ----
extern void expand_fp_branch PARAMS ((rtx (*)(void), rtx (*)(void)));
extern int sh_insn_length_adjustment PARAMS ((rtx));
extern int sh_can_redirect_branch PARAMS ((rtx, rtx));
+ extern void sh_expand_unop_v2sf (enum rtx_code, rtx, rtx);
+ extern void sh_expand_binop_v2sf (enum rtx_code, rtx, rtx, rtx);
#ifdef TREE_CODE
extern void sh_va_start PARAMS ((tree, rtx));
extern rtx sh_va_arg PARAMS ((tree, tree));
*************** extern void output_file_start PARAMS ((F
*** 117,124 ****
extern int sh_media_register_for_return PARAMS ((void));
extern void sh_expand_prologue PARAMS ((void));
extern void sh_expand_epilogue PARAMS ((void));
- extern void sh_expand_unop_v2sf (enum rtx_code, rtx, rtx);
- extern void sh_expand_binop_v2sf (enum rtx_code, rtx, rtx, rtx);
extern int sh_need_epilogue PARAMS ((void));
extern int initial_elimination_offset PARAMS ((int, int));
extern int fldi_ok PARAMS ((void));
--- 119,124 ----
Index: config/sh/sh.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.c,v
retrieving revision 1.164
diff -p -r1.164 sh.c
*** config/sh/sh.c 18 Jul 2002 12:47:34 -0000 1.164
--- config/sh/sh.c 18 Jul 2002 18:38:42 -0000
*************** machine_dependent_reorg (first)
*** 3828,3834 ****
{
lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
! newsrc = gen_rtx_UNSPEC (VOIDmode,
gen_rtvec (1, newsrc),
UNSPEC_MOVA);
}
--- 3828,3834 ----
{
lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
! newsrc = gen_rtx_UNSPEC (SImode,
gen_rtvec (1, newsrc),
UNSPEC_MOVA);
}
*************** arith_reg_dest (op, mode)
*** 5870,5875 ****
--- 5870,5890 ----
}
int
+ int_gpr_dest (op, mode)
+ rtx op;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+ {
+ enum machine_mode op_mode = GET_MODE (op);
+
+ if (GET_MODE_CLASS (op_mode) != MODE_INT
+ || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
+ return 0;
+ if (! reload_completed)
+ return 0;
+ return true_regnum (op) <= LAST_GENERAL_REG;
+ }
+
+ int
fp_arith_reg_operand (op, mode)
rtx op;
enum machine_mode mode;
*************** extend_reg_operand (op, mode)
*** 6256,6261 ****
--- 6271,6289 ----
return (GET_CODE (op) == TRUNCATE
? arith_operand
: arith_reg_operand) (op, mode);
+ }
+
+ int
+ trunc_hi_operand (op, mode)
+ rtx op;
+ enum machine_mode mode;
+ {
+ enum machine_mode op_mode = GET_MODE (op);
+
+ if (op_mode != SImode && op_mode != DImode
+ && op_mode != V4HImode && op_mode != V2SImode)
+ return 0;
+ return extend_reg_operand (op, mode);
}
int
Index: config/sh/sh.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.h,v
retrieving revision 1.162
diff -p -r1.162 sh.h
*** config/sh/sh.h 17 Jul 2002 16:02:53 -0000 1.162
--- config/sh/sh.h 18 Jul 2002 18:38:42 -0000
*************** extern int rtx_equal_function_value_matt
*** 3211,3216 ****
--- 3211,3217 ----
/* Define the codes that are matched by predicates in sh.c. */
#define PREDICATE_CODES \
{"and_operand", {SUBREG, REG, CONST_INT}}, \
+ {"any_register_operand", {SUBREG, REG}}, \
{"arith_operand", {SUBREG, REG, CONST_INT}}, \
{"arith_reg_dest", {SUBREG, REG}}, \
{"arith_reg_operand", {SUBREG, REG}}, \
*************** extern int rtx_equal_function_value_matt
*** 3227,3232 ****
--- 3228,3234 ----
{"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
{"general_movdst_operand", {SUBREG, REG, MEM}}, \
{"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
+ {"int_gpr_dest", {SUBREG, REG}}, \
{"inqhi_operand", {TRUNCATE}}, \
{"less_comparison_operator", {LT,LE,LTU,LEU}}, \
{"logical_operand", {SUBREG, REG, CONST_INT}}, \
*************** extern int rtx_equal_function_value_matt
*** 3235,3246 ****
--- 3237,3257 ----
{"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
{"target_reg_operand", {SUBREG, REG}}, \
{"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
+ {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \
{"register_operand", {SUBREG, REG}}, \
{"sh_const_vec", {CONST_VECTOR}}, \
{"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
{"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
{"symbol_ref_operand", {SYMBOL_REF}}, \
{"unary_float_operator", {ABS, NEG, SQRT}}, \
+
+ #define SPECIAL_MODE_PREDICATES \
+ "any_register_operand", \
+ "int_gpr_dest", \
+ "trunc_hi_operand", \
+ /* This line intentionally left blank. */
+
+ #define any_register_operand register_operand
/* Define this macro if it is advisable to hold scalars in registers
in a wider mode than that declared by the program. In such cases,
Index: config/sh/sh.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.md,v
retrieving revision 1.115
diff -p -r1.115 sh.md
*** config/sh/sh.md 17 Jul 2002 16:06:18 -0000 1.115
--- config/sh/sh.md 18 Jul 2002 18:38:42 -0000
***************
*** 857,864 ****
(define_split
[(set (reg:SI T_REG)
! (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
! (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
;; If we applied this split when not optimizing, it would only be
;; applied during the machine-dependent reorg, when no new basic blocks
;; may be created.
--- 857,864 ----
(define_split
[(set (reg:SI T_REG)
! (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
! (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
;; If we applied this split when not optimizing, it would only be
;; applied during the machine-dependent reorg, when no new basic blocks
;; may be created.
***************
*** 1142,1150 ****
[(set_attr "length" "6")])
(define_split
! [(set (match_operand:DI 0 "arith_reg_operand" "=r")
! (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
! (match_operand:DI 2 "arith_reg_operand" "r")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(const_int 0)]
--- 1142,1150 ----
[(set_attr "length" "6")])
(define_split
! [(set (match_operand:DI 0 "arith_reg_operand" "")
! (plus:DI (match_operand:DI 1 "arith_reg_operand" "")
! (match_operand:DI 2 "arith_reg_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(const_int 0)]
***************
*** 1253,1261 ****
[(set_attr "length" "6")])
(define_split
! [(set (match_operand:DI 0 "arith_reg_operand" "=r")
! (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
! (match_operand:DI 2 "arith_reg_operand" "r")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(const_int 0)]
--- 1253,1261 ----
[(set_attr "length" "6")])
(define_split
! [(set (match_operand:DI 0 "arith_reg_operand" "")
! (minus:DI (match_operand:DI 1 "arith_reg_operand" "")
! (match_operand:DI 2 "arith_reg_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(const_int 0)]
***************
*** 1350,1361 ****
;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
;; also has an effect on the register that holds the address of the sfunc.
! ;; To make this work, we have an extra dummy insns that shows the use
;; of this register for reorg.
(define_insn "use_sfunc_addr"
[(set (reg:SI PR_REG)
! (unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
"TARGET_SH1"
""
[(set_attr "length" "0")])
--- 1350,1361 ----
;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
;; also has an effect on the register that holds the address of the sfunc.
! ;; To make this work, we have an extra dummy insn that shows the use
;; of this register for reorg.
(define_insn "use_sfunc_addr"
[(set (reg:SI PR_REG)
! (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
"TARGET_SH1"
""
[(set_attr "length" "0")])
***************
*** 2378,2384 ****
(define_split
[(set (match_operand:SI 0 "arith_reg_operand" "")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
! (match_operand:SI 2 "const_int_operand" "n")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(use (reg:SI R0_REG))]
--- 2378,2384 ----
(define_split
[(set (match_operand:SI 0 "arith_reg_operand" "")
(ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
! (match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(use (reg:SI R0_REG))]
***************
*** 2441,2447 ****
(define_split
[(set (match_operand:HI 0 "arith_reg_operand" "")
(ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
! (match_operand:HI 2 "const_int_operand" "n")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(use (reg:SI R0_REG))]
--- 2441,2447 ----
(define_split
[(set (match_operand:HI 0 "arith_reg_operand" "")
(ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
! (match_operand:HI 2 "const_int_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(use (reg:SI R0_REG))]
***************
*** 2482,2489 ****
[(set_attr "length" "4")])
(define_split
! [(set (match_operand:SI 0 "arith_reg_operand" "=r")
! (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
(const_int 16)))]
"TARGET_SH1"
[(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
--- 2482,2489 ----
[(set_attr "length" "4")])
(define_split
! [(set (match_operand:SI 0 "arith_reg_operand" "")
! (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
(const_int 16)))]
"TARGET_SH1"
[(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
***************
*** 2502,2509 ****
[(set_attr "length" "4")])
(define_split
! [(set (match_operand:SI 0 "arith_reg_operand" "=r")
! (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
(const_int 31)))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
--- 2502,2509 ----
[(set_attr "length" "4")])
(define_split
! [(set (match_operand:SI 0 "arith_reg_operand" "")
! (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
(const_int 31)))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
***************
*** 2628,2634 ****
(define_split
[(set (match_operand:SI 0 "arith_reg_operand" "")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
! (match_operand:SI 2 "const_int_operand" "n")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(use (reg:SI R0_REG))]
--- 2628,2634 ----
(define_split
[(set (match_operand:SI 0 "arith_reg_operand" "")
(lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
! (match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && reload_completed"
[(use (reg:SI R0_REG))]
***************
*** 2803,2810 ****
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
! (match_operand:SI 2 "const_int_operand" "n"))
! (match_operand:SI 3 "const_int_operand" "n")))]
"TARGET_SH1 && (unsigned)INTVAL (operands[2]) < 32"
[(use (reg:SI R0_REG))]
"if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
--- 2803,2810 ----
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
! (match_operand:SI 2 "const_int_operand" ""))
! (match_operand:SI 3 "const_int_operand" "")))]
"TARGET_SH1 && (unsigned)INTVAL (operands[2]) < 32"
[(use (reg:SI R0_REG))]
"if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
***************
*** 2813,2820 ****
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
! (match_operand:SI 2 "const_int_operand" "n"))
! (match_operand:SI 3 "const_int_operand" "n")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && (unsigned)INTVAL (operands[2]) < 32"
[(use (reg:SI R0_REG))]
--- 2813,2820 ----
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
! (match_operand:SI 2 "const_int_operand" ""))
! (match_operand:SI 3 "const_int_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1 && (unsigned)INTVAL (operands[2]) < 32"
[(use (reg:SI R0_REG))]
***************
*** 2895,2909 ****
(set_attr "type" "arith")])
(define_split
! [(set (match_operand:SI 0 "register_operand" "=r,&r")
(lshiftrt:SI
(ashift:SI
(and:SI
! (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
! (match_operand:SI 2 "const_int_operand" "N,n"))
! (match_operand:SI 3 "register_operand" "0,r"))
! (match_operand:SI 4 "const_int_operand" "n,n"))
! (match_operand:SI 5 "const_int_operand" "n,n")))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
[(use (reg:SI R0_REG))]
--- 2895,2909 ----
(set_attr "type" "arith")])
(define_split
! [(set (match_operand:SI 0 "register_operand" "")
(lshiftrt:SI
(ashift:SI
(and:SI
! (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
! (match_operand:SI 2 "const_int_operand" ""))
! (match_operand:SI 3 "register_operand" ""))
! (match_operand:SI 4 "const_int_operand" ""))
! (match_operand:SI 5 "const_int_operand" "")))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
[(use (reg:SI R0_REG))]
***************
*** 2928,2938 ****
;; signed left/right shift combination.
(define_split
! [(set (match_operand:SI 0 "register_operand" "=r")
(sign_extract:SI
! (ashift:SI (match_operand:SI 1 "register_operand" "r")
! (match_operand:SI 2 "const_int_operand" "n"))
! (match_operand:SI 3 "const_int_operand" "n")
(const_int 0)))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
--- 2928,2938 ----
;; signed left/right shift combination.
(define_split
! [(set (match_operand:SI 0 "register_operand" "")
(sign_extract:SI
! (ashift:SI (match_operand:SI 1 "register_operand" "")
! (match_operand:SI 2 "const_int_operand" ""))
! (match_operand:SI 3 "const_int_operand" "")
(const_int 0)))
(clobber (reg:SI T_REG))]
"TARGET_SH1"
***************
*** 3107,3114 ****
[(set_attr "type" "*,load_media")])
(define_split
! [(set (match_operand:DI 0 "register_operand" "=r")
! (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "r")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
(set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))]
--- 3107,3114 ----
[(set_attr "type" "*,load_media")])
(define_split
! [(set (match_operand:DI 0 "register_operand" "")
! (zero_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
(set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 48)))]
***************
*** 3121,3127 ****
;; ??? when a truncated input to a zero_extrend is reloaded, reload will
;; reload the entrire truncate expression.
(define_insn_and_split "*loaddi_trunc"
! [(set (match_operand 0 "register_operand" "=r")
(truncate (match_operand:DI 1 "memory_operand" "m")))]
"TARGET_SHMEDIA && reload_completed"
"#"
--- 3121,3127 ----
;; ??? when a truncated input to a zero_extrend is reloaded, reload will
;; reload the entrire truncate expression.
(define_insn_and_split "*loaddi_trunc"
! [(set (match_operand 0 "int_gpr_dest" "=r")
(truncate (match_operand:DI 1 "memory_operand" "m")))]
"TARGET_SHMEDIA && reload_completed"
"#"
***************
*** 3166,3173 ****
[(set_attr "type" "arith_media,load_media")])
(define_split
! [(set (match_operand:SI 0 "register_operand" "=r")
! (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "r")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 16)))
(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
--- 3166,3173 ----
[(set_attr "type" "arith_media,load_media")])
(define_split
! [(set (match_operand:SI 0 "register_operand" "")
! (zero_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 16)))
(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
***************
*** 3239,3246 ****
[(set_attr "type" "*,load_media")])
(define_split
! [(set (match_operand:DI 0 "register_operand" "=r")
! (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "r")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))]
--- 3239,3246 ----
[(set_attr "type" "*,load_media")])
(define_split
! [(set (match_operand:DI 0 "register_operand" "")
! (sign_extend:DI (match_operand:HI 1 "extend_reg_operand" "")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 48)))
(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 48)))]
***************
*** 3260,3267 ****
[(set_attr "type" "*,load_media")])
(define_split
! [(set (match_operand:DI 0 "register_operand" "=r")
! (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "r")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56)))
(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))]
--- 3260,3267 ----
[(set_attr "type" "*,load_media")])
(define_split
! [(set (match_operand:DI 0 "register_operand" "")
! (sign_extend:DI (match_operand:QI 1 "extend_reg_operand" "")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:DI (subreg:DI (match_dup 1) 0) (const_int 56)))
(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))]
***************
*** 3297,3304 ****
[(set_attr "type" "arith_media,load_media")])
(define_split
! [(set (match_operand:SI 0 "register_operand" "=r")
! (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "r")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 16)))
(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
--- 3297,3304 ----
[(set_attr "type" "arith_media,load_media")])
(define_split
! [(set (match_operand:SI 0 "register_operand" "")
! (sign_extend:SI (match_operand:HI 1 "extend_reg_operand" "")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 16)))
(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))]
***************
*** 3334,3341 ****
[(set_attr "type" "arith_media,load_media")])
(define_split
! [(set (match_operand:SI 0 "register_operand" "=r")
! (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "r")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 24)))
(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
--- 3334,3341 ----
[(set_attr "type" "arith_media,load_media")])
(define_split
! [(set (match_operand:SI 0 "register_operand" "")
! (sign_extend:SI (match_operand:QI 1 "extend_reg_operand" "")))]
"TARGET_SHMEDIA && reload_completed"
[(set (match_dup 0) (ashift:SI (subreg:SI (match_dup 1) 0) (const_int 24)))
(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))]
***************
*** 3601,3608 ****
(set_attr "length" "4,4,8,4,4,4,4,12")])
(define_split
! [(set (match_operand:SI 0 "arith_reg_operand" "=r")
! (match_operand:SI 1 "immediate_operand" "s"))]
"TARGET_SHMEDIA && reload_completed
&& MOVI_SHORI_BASE_OPERAND_P (operands[1])"
[(set (subreg:DI (match_dup 0) 0) (match_dup 2))]
--- 3601,3608 ----
(set_attr "length" "4,4,8,4,4,4,4,12")])
(define_split
! [(set (match_operand:SI 0 "arith_reg_operand" "")
! (match_operand:SI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed
&& MOVI_SHORI_BASE_OPERAND_P (operands[1])"
[(set (subreg:DI (match_dup 0) 0) (match_dup 2))]
***************
*** 3613,3620 ****
}")
(define_split
! [(set (match_operand:SI 0 "register_operand" "=r")
! (match_operand:SI 1 "immediate_operand" "n"))]
"TARGET_SHMEDIA && reload_completed
&& ((GET_CODE (operands[1]) == CONST_INT
&& ! CONST_OK_FOR_J (INTVAL (operands[1])))
--- 3613,3620 ----
}")
(define_split
! [(set (match_operand:SI 0 "register_operand" "")
! (match_operand:SI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed
&& ((GET_CODE (operands[1]) == CONST_INT
&& ! CONST_OK_FOR_J (INTVAL (operands[1])))
***************
*** 3799,3806 ****
[(set_attr "type" "arith_media,arith_media,*,load_media,store_media")])
(define_split
! [(set (match_operand:HI 0 "register_operand" "=r")
! (match_operand:HI 1 "immediate_operand" "n"))]
"TARGET_SHMEDIA && reload_completed
&& ! CONST_OK_FOR_J (INTVAL (operands[1]))"
[(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
--- 3799,3806 ----
[(set_attr "type" "arith_media,arith_media,*,load_media,store_media")])
(define_split
! [(set (match_operand:HI 0 "register_operand" "")
! (match_operand:HI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed
&& ! CONST_OK_FOR_J (INTVAL (operands[1]))"
[(set (subreg:DI (match_dup 0) 0) (match_dup 1))])
***************
*** 3932,3939 ****
(set_attr "length" "4,4,16,4,4,4,4,*")])
(define_split
! [(set (match_operand:DI 0 "arith_reg_operand" "=r")
! (match_operand:DI 1 "immediate_operand" "s"))]
"TARGET_SHMEDIA && reload_completed
&& MOVI_SHORI_BASE_OPERAND_P (operands[1])"
[(set (match_dup 0) (match_dup 1))]
--- 3932,3939 ----
(set_attr "length" "4,4,16,4,4,4,4,*")])
(define_split
! [(set (match_operand:DI 0 "arith_reg_operand" "")
! (match_operand:DI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed
&& MOVI_SHORI_BASE_OPERAND_P (operands[1])"
[(set (match_dup 0) (match_dup 1))]
***************
*** 4040,4047 ****
"")
(define_split
! [(set (match_operand:DI 0 "arith_reg_operand" "=r")
! (match_operand:DI 1 "immediate_operand" "i"))]
"TARGET_SHMEDIA && reload_completed
&& GET_CODE (operands[1]) == CONST_INT
&& ! CONST_OK_FOR_J (INTVAL (operands[1]))"
--- 4040,4047 ----
"")
(define_split
! [(set (match_operand:DI 0 "arith_reg_operand" "")
! (match_operand:DI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed
&& GET_CODE (operands[1]) == CONST_INT
&& ! CONST_OK_FOR_J (INTVAL (operands[1]))"
***************
*** 4138,4145 ****
}")
(define_split
! [(set (match_operand:DI 0 "arith_reg_operand" "=r")
! (match_operand:DI 1 "immediate_operand" "F"))]
"TARGET_SHMEDIA && reload_completed
&& GET_CODE (operands[1]) == CONST_DOUBLE"
[(set (match_dup 0) (match_dup 2))
--- 4138,4145 ----
}")
(define_split
! [(set (match_operand:DI 0 "arith_reg_operand" "")
! (match_operand:DI 1 "immediate_operand" ""))]
"TARGET_SHMEDIA && reload_completed
&& GET_CODE (operands[1]) == CONST_DOUBLE"
[(set (match_dup 0) (match_dup 2))
***************
*** 4326,4332 ****
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" "c"))
(clobber (match_scratch:SI 3 "=X"))]
"TARGET_SH4 && reload_completed
&& (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
--- 4326,4332 ----
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (match_scratch:SI 3 "=X"))]
"TARGET_SH4 && reload_completed
&& (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
***************
*** 4365,4372 ****
(define_split
[(set (match_operand:DF 0 "general_movdst_operand" "")
(match_operand:DF 1 "general_movsrc_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" "c"))
! (clobber (match_scratch:SI 3 "X"))]
"TARGET_SH4
&& reload_completed
&& true_regnum (operands[0]) < 16
--- 4365,4372 ----
(define_split
[(set (match_operand:DF 0 "general_movdst_operand" "")
(match_operand:DF 1 "general_movsrc_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" ""))
! (clobber (match_scratch:SI 3 ""))]
"TARGET_SH4
&& reload_completed
&& true_regnum (operands[0]) < 16
***************
*** 4438,4444 ****
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "memory_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" "c"))
(clobber (reg:SI R0_REG))]
"TARGET_SH4 && reload_completed"
[(parallel [(set (match_dup 0) (match_dup 1))
--- 4438,4444 ----
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "memory_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (reg:SI R0_REG))]
"TARGET_SH4 && reload_completed"
[(parallel [(set (match_dup 0) (match_dup 1))
***************
*** 4476,4482 ****
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" "c"))
(clobber (match_scratch:SI 3 "X"))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
--- 4476,4482 ----
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (match_scratch:SI 3 "X"))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
***************
*** 4495,4502 ****
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(mem:DF (match_operand:SI 1 "register_operand" "")))
! (use (match_operand:PSI 2 "fpscr_operand" "c"))
! (clobber (match_scratch:SI 3 "X"))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
&& find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
--- 4495,4502 ----
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(mem:DF (match_operand:SI 1 "register_operand" "")))
! (use (match_operand:PSI 2 "fpscr_operand" ""))
! (clobber (match_scratch:SI 3 ""))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
&& find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
***************
*** 4521,4528 ****
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "memory_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" "c"))
! (clobber (match_scratch:SI 3 "X"))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
[(const_int 0)]
--- 4521,4528 ----
(define_split
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "memory_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" ""))
! (clobber (match_scratch:SI 3 ""))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
[(const_int 0)]
***************
*** 4562,4569 ****
(define_split
[(set (match_operand:DF 0 "memory_operand" "")
(match_operand:DF 1 "register_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" "c"))
! (clobber (match_scratch:SI 3 "X"))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
[(const_int 0)]
--- 4562,4569 ----
(define_split
[(set (match_operand:DF 0 "memory_operand" "")
(match_operand:DF 1 "register_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" ""))
! (clobber (match_scratch:SI 3 ""))]
"TARGET_SH4 && ! TARGET_FMOVD && reload_completed
&& FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
[(const_int 0)]
***************
*** 5022,5028 ****
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(match_operand:SF 1 "register_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" "c"))
(clobber (reg:SI FPUL_REG))]
"TARGET_SH1"
[(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
--- 5022,5028 ----
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(match_operand:SF 1 "register_operand" ""))
! (use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (reg:SI FPUL_REG))]
"TARGET_SH1"
[(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
***************
*** 5057,5063 ****
}")
(define_insn "mov_nop"
! [(set (match_operand 0 "register_operand" "") (match_dup 0))]
"TARGET_SH3E"
""
[(set_attr "length" "0")
--- 5057,5063 ----
}")
(define_insn "mov_nop"
! [(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
"TARGET_SH3E"
""
[(set_attr "length" "0")
***************
*** 5138,5145 ****
;; This one has the additional purpose to record a possible scratch register
;; for the following branch.
(define_insn "indirect_jump_scratch"
! [(set (match_operand 0 "register_operand" "=r")
! (unspec [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))]
"TARGET_SH1"
""
[(set_attr "length" "0")])
--- 5138,5145 ----
;; This one has the additional purpose to record a possible scratch register
;; for the following branch.
(define_insn "indirect_jump_scratch"
! [(set (match_operand:SI 0 "register_operand" "=r")
! (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))]
"TARGET_SH1"
""
[(set_attr "length" "0")])
***************
*** 6210,6216 ****
[(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
(match_operand 1 "" ""))
(return)
! (use (match_operand 2 "register_operand" "z,x"))
(use (reg:SI R1_REG))
(use (reg:PSI FPSCR_REG))
;; We want to make sure the `x' above will only match MACH_REG
--- 6210,6216 ----
[(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
(match_operand 1 "" ""))
(return)
! (use (match_operand:SI 2 "register_operand" "z,x"))
(use (reg:SI R1_REG))
(use (reg:PSI FPSCR_REG))
;; We want to make sure the `x' above will only match MACH_REG
***************
*** 6633,6639 ****
(define_insn "mova"
[(set (reg:SI R0_REG)
! (unspec [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
"TARGET_SH1"
"mova %O0,r0"
[(set_attr "in_delay_slot" "no")
--- 6633,6639 ----
(define_insn "mova"
[(set (reg:SI R0_REG)
! (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
"TARGET_SH1"
"mova %O0,r0"
[(set_attr "in_delay_slot" "no")
***************
*** 6642,6648 ****
;; machine_dependent_reorg() will make this a `mova'.
(define_insn "mova_const"
[(set (reg:SI R0_REG)
! (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
"TARGET_SH1"
"#"
[(set_attr "in_delay_slot" "no")
--- 6642,6648 ----
;; machine_dependent_reorg() will make this a `mova'.
(define_insn "mova_const"
[(set (reg:SI R0_REG)
! (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
"TARGET_SH1"
"#"
[(set_attr "in_delay_slot" "no")
***************
*** 6650,6657 ****
(define_expand "GOTaddr2picreg"
[(set (reg:SI R0_REG)
! (unspec [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
! UNSPEC_MOVA))
(set (match_dup 0) (const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC)))
(set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
"" "
--- 6650,6657 ----
(define_expand "GOTaddr2picreg"
[(set (reg:SI R0_REG)
! (unspec:SI [(const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC))]
! UNSPEC_MOVA))
(set (match_dup 0) (const:SI (unspec:SI [(match_dup 1)] UNSPEC_PIC)))
(set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
"" "
***************
*** 6728,6735 ****
(set_attr "length" "*")])
(define_insn "ptrel"
! [(set (match_operand:DI 0 "target_reg_operand" "=bk")
! (plus (match_operand:DI 1 "register_operand" "r")
(pc)))
(match_operand:DI 2 "" "")]
"TARGET_SHMEDIA"
--- 6728,6735 ----
(set_attr "length" "*")])
(define_insn "ptrel"
! [(set (match_operand:DI 0 "target_reg_operand" "=b")
! (plus:DI (match_operand:DI 1 "register_operand" "r")
(pc)))
(match_operand:DI 2 "" "")]
"TARGET_SHMEDIA"
***************
*** 6979,6985 ****
(define_insn "casesi_worker_0"
[(set (match_operand:SI 0 "register_operand" "=r,r")
! (unspec:SI [(match_operand 1 "register_operand" "0,r")
(label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
(clobber (match_scratch:SI 3 "=X,1"))
(clobber (match_scratch:SI 4 "=&z,z"))]
--- 6979,6985 ----
(define_insn "casesi_worker_0"
[(set (match_operand:SI 0 "register_operand" "=r,r")
! (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
(label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
(clobber (match_scratch:SI 3 "=X,1"))
(clobber (match_scratch:SI 4 "=&z,z"))]
***************
*** 6988,7024 ****
(define_split
[(set (match_operand:SI 0 "register_operand" "")
! (unspec [(match_operand 1 "register_operand" "")
! (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
(clobber (match_scratch:SI 3 ""))
(clobber (match_scratch:SI 4 ""))]
"TARGET_SH1 && ! TARGET_SH2 && reload_completed"
! [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
(parallel [(set (match_dup 0)
! (unspec [(reg:SI R0_REG) (match_dup 1)
! (label_ref (match_dup 2))] UNSPEC_CASESI))
(clobber (match_dup 3))])
(set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
"if (GET_CODE (operands[2]) == CODE_LABEL) LABEL_NUSES (operands[2])++;")
(define_split
[(set (match_operand:SI 0 "register_operand" "")
! (unspec:SI [(match_operand 1 "register_operand" "")
! (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
(clobber (match_scratch:SI 3 ""))
(clobber (match_scratch:SI 4 ""))]
"TARGET_SH2 && reload_completed"
! [(set (reg:SI R0_REG) (unspec [(label_ref (match_dup 2))] UNSPEC_MOVA))
(parallel [(set (match_dup 0)
(unspec:SI [(reg:SI R0_REG) (match_dup 1)
! (label_ref (match_dup 2))] UNSPEC_CASESI))
(clobber (match_dup 3))])]
"if (GET_CODE (operands[2]) == CODE_LABEL) LABEL_NUSES (operands[2])++;")
(define_insn "*casesi_worker"
[(set (match_operand:SI 0 "register_operand" "=r,r")
! (unspec [(reg:SI R0_REG) (match_operand 1 "register_operand" "0,r")
! (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
(clobber (match_scratch:SI 3 "=X,1"))]
"TARGET_SH1"
"*
--- 6988,7025 ----
(define_split
[(set (match_operand:SI 0 "register_operand" "")
! (unspec:SI [(match_operand:SI 1 "register_operand" "")
! (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
(clobber (match_scratch:SI 3 ""))
(clobber (match_scratch:SI 4 ""))]
"TARGET_SH1 && ! TARGET_SH2 && reload_completed"
! [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
(parallel [(set (match_dup 0)
! (unspec:SI [(reg:SI R0_REG) (match_dup 1)
! (label_ref (match_dup 2))] UNSPEC_CASESI))
(clobber (match_dup 3))])
(set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
"if (GET_CODE (operands[2]) == CODE_LABEL) LABEL_NUSES (operands[2])++;")
(define_split
[(set (match_operand:SI 0 "register_operand" "")
! (unspec:SI [(match_operand:SI 1 "register_operand" "")
! (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
(clobber (match_scratch:SI 3 ""))
(clobber (match_scratch:SI 4 ""))]
"TARGET_SH2 && reload_completed"
! [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
(parallel [(set (match_dup 0)
(unspec:SI [(reg:SI R0_REG) (match_dup 1)
! (label_ref (match_dup 2))] UNSPEC_CASESI))
(clobber (match_dup 3))])]
"if (GET_CODE (operands[2]) == CODE_LABEL) LABEL_NUSES (operands[2])++;")
(define_insn "*casesi_worker"
[(set (match_operand:SI 0 "register_operand" "=r,r")
! (unspec:SI [(reg:SI R0_REG)
! (match_operand:SI 1 "register_operand" "0,r")
! (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
(clobber (match_scratch:SI 3 "=X,1"))]
"TARGET_SH1"
"*
***************
*** 7192,7214 ****
}")
(define_insn "shcompact_preserve_incoming_args"
! [(set (match_operand 0 "register_operand" "+r")
! (unspec [(match_dup 0)] UNSPEC_COMPACT_ARGS))]
"TARGET_SHCOMPACT"
""
[(set_attr "length" "0")])
(define_insn "shcompact_incoming_args"
! [(set (reg:SI R2_REG) (unspec [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R3_REG) (unspec [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R4_REG) (unspec [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R5_REG) (unspec [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R6_REG) (unspec [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R7_REG) (unspec [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R8_REG) (unspec [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R9_REG) (unspec [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS))
(set (mem:BLK (reg:SI MACL_REG))
! (unspec [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS))
(use (reg:SI R0_REG))
(clobber (reg:SI R0_REG))
(clobber (reg:SI MACL_REG))
--- 7193,7215 ----
}")
(define_insn "shcompact_preserve_incoming_args"
! [(set (match_operand:SI 0 "register_operand" "+r")
! (unspec:SI [(match_dup 0)] UNSPEC_COMPACT_ARGS))]
"TARGET_SHCOMPACT"
""
[(set_attr "length" "0")])
(define_insn "shcompact_incoming_args"
! [(set (reg:SI R2_REG) (unspec:SI [(reg:SI R2_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R3_REG) (unspec:SI [(reg:SI R3_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R4_REG) (unspec:SI [(reg:SI R4_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R5_REG) (unspec:SI [(reg:SI R5_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R6_REG) (unspec:SI [(reg:SI R6_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R7_REG) (unspec:SI [(reg:SI R7_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R8_REG) (unspec:SI [(reg:SI R8_REG)] UNSPEC_COMPACT_ARGS))
! (set (reg:SI R9_REG) (unspec:SI [(reg:SI R9_REG)] UNSPEC_COMPACT_ARGS))
(set (mem:BLK (reg:SI MACL_REG))
! (unspec:BLK [(reg:SI MACH_REG)] UNSPEC_COMPACT_ARGS))
(use (reg:SI R0_REG))
(clobber (reg:SI R0_REG))
(clobber (reg:SI MACL_REG))
***************
*** 9898,9904 ****
(define_insn "mperm_w0"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(vec_duplicate:V4HI (truncate:HI (match_operand 1
! "extend_reg_operand" "r"))))]
"TARGET_SHMEDIA"
"mperm.w %1, r63, %0"
[(set_attr "type" "arith_media")])
--- 9899,9905 ----
(define_insn "mperm_w0"
[(set (match_operand:V4HI 0 "arith_reg_dest" "=r")
(vec_duplicate:V4HI (truncate:HI (match_operand 1
! "trunc_hi_operand" "r"))))]
"TARGET_SHMEDIA"
"mperm.w %1, r63, %0"
[(set_attr "type" "arith_media")])
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: patch applied to sh port: suppress some warnings.
2002-07-18 12:30 patch applied to sh port: suppress some warnings Joern Rennecke
@ 2002-08-08 6:37 ` Alexandre Oliva
2002-08-13 6:22 ` Joern Rennecke
2002-08-13 7:47 ` Kaveh R. Ghazi
0 siblings, 2 replies; 6+ messages in thread
From: Alexandre Oliva @ 2002-08-08 6:37 UTC (permalink / raw)
To: Joern Rennecke; +Cc: gcc-patches
Hi, Jörn,
On Jul 18, 2002, Joern Rennecke <joern.rennecke@superh.com> wrote:
> Index: config/sh/sh-protos.h
[snip]
> + extern void sh_expand_unop_v2sf (enum rtx_code, rtx, rtx);
> + extern void sh_expand_binop_v2sf (enum rtx_code, rtx, rtx, rtx);
Catching up on e-mail... This is missing PARAMS.
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{redhat.com, gcc.gnu.org}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist Professional serial bug killer
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: patch applied to sh port: suppress some warnings.
2002-08-08 6:37 ` Alexandre Oliva
@ 2002-08-13 6:22 ` Joern Rennecke
2002-08-13 12:34 ` Alexandre Oliva
2002-08-13 7:47 ` Kaveh R. Ghazi
1 sibling, 1 reply; 6+ messages in thread
From: Joern Rennecke @ 2002-08-13 6:22 UTC (permalink / raw)
To: Alexandre Oliva; +Cc: gcc-patches
Alexandre Oliva wrote:
>
> Hi, Jörn,
>
> On Jul 18, 2002, Joern Rennecke <joern.rennecke@superh.com> wrote:
>
> > Index: config/sh/sh-protos.h
> [snip]
> > + extern void sh_expand_unop_v2sf (enum rtx_code, rtx, rtx);
> > + extern void sh_expand_binop_v2sf (enum rtx_code, rtx, rtx, rtx);
>
> Catching up on e-mail... This is missing PARAMS.
No, it is in accordance with the steering commitee decision that most
ports should be ANSIfied.
--
--------------------------
SuperH
2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
T:+44 1454 462330
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: patch applied to sh port: suppress some warnings.
2002-08-08 6:37 ` Alexandre Oliva
2002-08-13 6:22 ` Joern Rennecke
@ 2002-08-13 7:47 ` Kaveh R. Ghazi
1 sibling, 0 replies; 6+ messages in thread
From: Kaveh R. Ghazi @ 2002-08-13 7:47 UTC (permalink / raw)
To: joern.rennecke; +Cc: aoliva, gcc-patches
> From: Joern Rennecke <joern dot rennecke at superh dot com>
>
> Alexandre Oliva wrote:
> >
> > Hi, J>
> > On Jul 18, 2002, Joern Rennecke <joern.rennecke@superh.com> wrote:
> >
> > > Index: config/sh/sh-protos.h
> > [snip]
> > > + extern void sh_expand_unop_v2sf (enum rtx_code, rtx, rtx);
> > > + extern void sh_expand_binop_v2sf (enum rtx_code, rtx, rtx, rtx);
> >
> > Catching up on e-mail... This is missing PARAMS.
>
> No, it is in accordance with the steering commitee decision that most
> ports should be ANSIfied.
We did not issue any change in ISO policy relating to ports, please
read the original announcement:
http://gcc.gnu.org/ml/gcc/2002-06/msg00871.html
--
Kaveh R. Ghazi Director of Systems Architecture
ghazi@caip.rutgers.edu Qwest Solutions
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: patch applied to sh port: suppress some warnings.
2002-08-13 6:22 ` Joern Rennecke
@ 2002-08-13 12:34 ` Alexandre Oliva
2002-08-13 14:20 ` Mark Mitchell
0 siblings, 1 reply; 6+ messages in thread
From: Alexandre Oliva @ 2002-08-13 12:34 UTC (permalink / raw)
To: Joern Rennecke; +Cc: gcc-patches
On Aug 13, 2002, Joern Rennecke <joern.rennecke@superh.com> wrote:
> No, it is in accordance with the steering commitee decision that most
> ports should be ANSIfied.
Odd... I remember the very opposite to have been decided when someone
asked for clarification regarding what to do about ports. For all I
know, they're part of the backend, and so the general rules say they
should still be buildable with K&R C. Some leeway could be used on
ports that are only ever built with ISO C compilers (i.e., those that
can't be cross-built without GCC and those for platforms whose native
compilers have always been ISO C-compliant). But this is all quoted
from memory, so I'd appreciate if someone would set me straight if I'm
mistaken on any of these points.
--
Alexandre Oliva Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
Red Hat GCC Developer aoliva@{redhat.com, gcc.gnu.org}
CS PhD student at IC-Unicamp oliva@{lsd.ic.unicamp.br, gnu.org}
Free Software Evangelist Professional serial bug killer
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: patch applied to sh port: suppress some warnings.
2002-08-13 12:34 ` Alexandre Oliva
@ 2002-08-13 14:20 ` Mark Mitchell
0 siblings, 0 replies; 6+ messages in thread
From: Mark Mitchell @ 2002-08-13 14:20 UTC (permalink / raw)
To: Alexandre Oliva, Joern Rennecke; +Cc: gcc-patches
--On Tuesday, August 13, 2002 04:34:05 PM -0300 Alexandre Oliva
<aoliva@redhat.com> wrote:
> On Aug 13, 2002, Joern Rennecke <joern.rennecke@superh.com> wrote:
>
>> No, it is in accordance with the steering commitee decision that most
>> ports should be ANSIfied.
>
> Odd... I remember the very opposite to have been decided when someone
> asked for clarification regarding what to do about ports. For all I
> know, they're part of the backend, and so the general rules say they
> should still be buildable with K&R C. Some leeway could be used on
> ports that are only ever built with ISO C compilers (i.e., those that
> can't be cross-built without GCC and those for platforms whose native
> compilers have always been ISO C-compliant). But this is all quoted
> from memory, so I'd appreciate if someone would set me straight if I'm
> mistaken on any of these points.
I believe you (Alexandre) are correct.
--
Mark Mitchell mark@codesourcery.com
CodeSourcery, LLC http://www.codesourcery.com
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2002-08-13 21:20 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2002-07-18 12:30 patch applied to sh port: suppress some warnings Joern Rennecke
2002-08-08 6:37 ` Alexandre Oliva
2002-08-13 6:22 ` Joern Rennecke
2002-08-13 12:34 ` Alexandre Oliva
2002-08-13 14:20 ` Mark Mitchell
2002-08-13 7:47 ` Kaveh R. Ghazi
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