PowerPC PIC code addressibility tweak

PowerPC PIC code addressibility tweak

[David Edelsohn]

	The PowerPC architecture recommends a preferred form for a
branch-and-link instruction that will not return, but used to obtain
addressibility for PIC code.  This form does not corrupt the link register
history stack.  Darwin already uses this form.  This patch converts SVR4
PIC code to use this form as well, as pointed out by Tege.

David


	* config/rs6000/rs6000.md (load_toc_v4_PIC_1): Use preferred form
	for addressibility.
	(load_toc_v4_PIC_1b): Same.

Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.218
diff -c -p -r1.218 rs6000.md
*** rs6000.md	19 Oct 2002 04:36:30 -0000	1.218
--- rs6000.md	30 Oct 2002 15:52:10 -0000
***************
*** 10272,10278 ****
  	(match_operand:SI 1 "immediate_operand" "s"))
     (unspec [(match_dup 1)] 7)]
    "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
!   "bl %1\\n%1:"
    [(set_attr "type" "branch")
     (set_attr "length" "4")])
  
--- 10272,10278 ----
  	(match_operand:SI 1 "immediate_operand" "s"))
     (unspec [(match_dup 1)] 7)]
    "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
!   "bcl 20,31,%1\\n%1:"
    [(set_attr "type" "branch")
     (set_attr "length" "4")])
  
***************
*** 10281,10287 ****
  	(match_operand:SI 1 "immediate_operand" "s"))
     (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)]
    "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
!   "bl %1\\n\\t.long %2-%1+4\\n%1:"
    [(set_attr "type" "branch")
     (set_attr "length" "8")])
  
--- 10281,10287 ----
  	(match_operand:SI 1 "immediate_operand" "s"))
     (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)]
    "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
!   "bcl 20,31,%1\\n\\t.long %2-%1+4\\n%1:"
    [(set_attr "type" "branch")
     (set_attr "length" "8")])
  

Re: PowerPC PIC code addressibility tweak

[Segher Boessenkool]

David Edelsohn wrote:
> 
>         The PowerPC architecture recommends a preferred form for a
> branch-and-link instruction that will not return, but used to obtain
> addressibility for PIC code.  This form does not corrupt the link register
> history stack.

	What document did you take this from?  I could only find this in the
Book E and in the 7450 UM, but both specifically say this is special
cased only for

	bcl	20,31,$+4

so your second patch won't help (as it uses $+8 instead).


Segher


> Darwin already uses this form.  This patch converts SVR4
> PIC code to use this form as well, as pointed out by Tege.
> 
> David
> 
>         * config/rs6000/rs6000.md (load_toc_v4_PIC_1): Use preferred form
>         for addressibility.
>         (load_toc_v4_PIC_1b): Same.
> 
> Index: rs6000.md
> ===================================================================
> RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
> retrieving revision 1.218
> diff -c -p -r1.218 rs6000.md
> *** rs6000.md   19 Oct 2002 04:36:30 -0000      1.218
> --- rs6000.md   30 Oct 2002 15:52:10 -0000
> ***************
> *** 10272,10278 ****
>         (match_operand:SI 1 "immediate_operand" "s"))
>      (unspec [(match_dup 1)] 7)]
>     "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
> !   "bl %1\\n%1:"
>     [(set_attr "type" "branch")
>      (set_attr "length" "4")])
> 
> --- 10272,10278 ----
>         (match_operand:SI 1 "immediate_operand" "s"))
>      (unspec [(match_dup 1)] 7)]
>     "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
> !   "bcl 20,31,%1\\n%1:"
>     [(set_attr "type" "branch")
>      (set_attr "length" "4")])
> 
> ***************
> *** 10281,10287 ****
>         (match_operand:SI 1 "immediate_operand" "s"))
>      (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)]
>     "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
> !   "bl %1\\n\\t.long %2-%1+4\\n%1:"
>     [(set_attr "type" "branch")
>      (set_attr "length" "8")])
> 
> --- 10281,10287 ----
>         (match_operand:SI 1 "immediate_operand" "s"))
>      (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)]
>     "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
> !   "bcl 20,31,%1\\n\\t.long %2-%1+4\\n%1:"
>     [(set_attr "type" "branch")
>      (set_attr "length" "8")])
>

Re: PowerPC PIC code addressibility tweak

[David Edelsohn]

>>>>> Segher Boessenkool writes:

Segher> What document did you take this from?  I could only find this in the
Segher> Book E and in the 7450 UM, but both specifically say this is special
Segher> cased only for

Segher> bcl	20,31,$+4

Segher> so your second patch won't help (as it uses $+8 instead).

	The recommendation is in the PowerPC Microprocessor Family
Programming Environments book.  The example is for $+4, but the effect is
not pushing the link register stack.  At worst, the new instruction is no
worse than the former one.

David

Re: PowerPC PIC code addressibility tweak

[Segher Boessenkool]

David Edelsohn wrote:
> 
> >>>>> Segher Boessenkool writes:
> 
> Segher> What document did you take this from?  I could only find this in the
> Segher> Book E and in the 7450 UM, but both specifically say this is special
> Segher> cased only for
> 
> Segher> bcl     20,31,$+4
> 
> Segher> so your second patch won't help (as it uses $+8 instead).
> 
>         The recommendation is in the PowerPC Microprocessor Family
> Programming Environments book.  The example is for $+4, but the effect is
> not pushing the link register stack.  At worst, the new instruction is no
> worse than the former one.

That's true, of course.

Another idea: why not generate something like

	bl $+4 ; blr

(and do something smart for the second case).

That would leave the return stack intact always (but might be bad for
branch prediction?)


Segher

Re: PowerPC PIC code addressibility tweak

[David Edelsohn]

>>>>> Segher Boessenkool writes:

Segher> Another idea: why not generate something like

Segher> bl $+4 ; blr

	Think about the instruction to which the blr instruction
branches.  Exercise for the reader.

David

Re: PowerPC PIC code addressibility tweak

[Segher Boessenkool]

David Edelsohn wrote:
> 
> >>>>> Segher Boessenkool writes:
> 
> Segher> Another idea: why not generate something like
> 
> Segher> bl $+4 ; blr
> 
>         Think about the instruction to which the blr instruction
> branches.  Exercise for the reader.

David,

Oops.  I feel so ashamed now :)

	bl $+8 ; b $+8 ; blr

and

	bl $+12 ; b $+12 ; .long XXXX ; blr

should work.  I didn't do any timings though; as it's highly likely
that actual processors just look at the "31" in bcl 20,31,$+4 and not
at the "$+4" for the link-stack-or-not decision, my bets are your code
is better.


Segher