[m68k]: Add ffs pattern for ColdFire 528x using the ff1 insn

[m68k]: Add ffs pattern for ColdFire 528x using the ff1 insn

[Peter Barada]

This patch adds ffs support for ColdFire ISA_A+ instructions(in the
528x chip) using the ff1 instruction.  It produces the following code:

foo:
	link.w %fp,#0
	move.l 8(%fp),%d0
	neg.l %d0
	and.l 8(%fp),%d0
	ff1.l %d0
	moveq #32,%d1
	sub.l %d0,%d1
	move.l %d1,%d0
	unlk %fp
	rts

from:

int foo(int x)
{
  return ffs(x);
}


Uberbaum builds C/C++ with this change.


gcc/
2004-06-20  Peter Barada  <peter@the-baradas.com>
	    * config/m68k/m68k.md(clzi2, ctzsi2, ffsi2): New patterns
	    for -m528x.


Index: gcc/config/m68k/m68k.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/m68k/m68k.md,v
retrieving revision 1.78
diff -c -3 -p -r1.78 m68k.md
*** gcc/config/m68k/m68k.md	16 Jun 2004 22:10:37 -0000	1.78
--- gcc/config/m68k/m68k.md	20 Jun 2004 06:56:31 -0000
***************
*** 7202,7204 ****
--- 7202,7242 ----
    default: abort();
    }
  })
+ 
+ (define_insn "clzsi2"
+   [(set (match_operand:SI 0 "register_operand" "=d")
+ 	(clz:SI (match_operand:SI 1 "general_operand" "0")))]
+   "TARGET_528x"
+   "ff1%.l %0")
+ 
+ (define_expand "ctzsi2"
+   [(set (match_dup 2)
+ 	(neg:SI (match_operand:SI 1 "register_operand" "d")))
+    (parallel [(set (match_dup 3) (and:SI (match_dup 1)
+ 					 (match_dup 2)))
+ 	     ])
+    (set (match_dup 4) (clz:SI (match_dup 3)))
+    (set (match_operand:SI 0 "register_operand" "=r")
+ 	(minus:SI (const_int 31) (match_dup 4)))]
+   "TARGET_528x"
+   {
+      operands[2] = gen_reg_rtx (SImode);
+      operands[3] = gen_reg_rtx (SImode);
+      operands[4] = gen_reg_rtx (SImode);
+   })
+ 
+ (define_expand "ffssi2"
+   [(set (match_dup 2)
+ 	(neg:SI (match_operand:SI 1 "register_operand" "d")))
+    (parallel [(set (match_dup 3) (and:SI (match_dup 1)
+ 					 (match_dup 2)))
+ 	      (clobber (scratch:CC))])
+    (set (match_dup 4) (clz:SI (match_dup 3)))
+    (set (match_operand:SI 0 "register_operand" "=d")
+ 	(minus:SI (const_int 32) (match_dup 4)))]
+   "TARGET_528x"
+   {
+      operands[2] = gen_reg_rtx (SImode);
+      operands[3] = gen_reg_rtx (SImode);
+      operands[4] = gen_reg_rtx (SImode);
+   })