From: Rask Ingemann Lambertsen <rask@sygehus.dk>
To: "Gadad, Pompapathi V" <Pompapathi.V.Gadad@nsc.com>
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [Patch] New: CR16 port
Date: Wed, 11 Jul 2007 23:41:00 -0000 [thread overview]
Message-ID: <20070711233258.GX5690@sygehus.dk> (raw)
In-Reply-To: <174557.128221184049955220.JavaMail.root@postal04.nsc.com>
On Tue, Jul 10, 2007 at 06:45:55AM +0000, Gadad, Pompapathi V wrote:
> Index: ChangeLog
> ===================================================================
> --- ChangeLog (revision 126478)
> +++ ChangeLog (working copy)
> @@ -1,3 +1,24 @@
Don't include the ChangeLog entry in the patch, post it separately. The
only exception is if you've already committed the patch. Then it is ok to
include the ChangeLog entry as part of the patch.
> +;; Negation Instructions
> +; move 0,r sub x,r. More efficient than xor -1,x add 1,x
> +(define_expand "neg<mode>2"
> + [(set (match_operand:CR16IM 0 "register_operand" "")
> + (const_int 0))
> + (parallel [(set (match_dup 0)
> + (minus:CR16IM (match_dup 0)
> + (match_operand:CR16IM 1 "register_operand" "")))
> + (clobber (reg:CC CC_REGNUM))])
> + ]
> + ""
> + "")
You can probably leave this out as the middle end will generate "op0 = 0
- op1" if there's no negm2 pattern.
> +(define_insn "mov<mode>_regs"
> + [(set (match_operand:ALLMT 0 "register_operand" "=r, r")
> + (match_operand:ALLMT 1 "nonmemory_operand" "r, <iF>"))]
> + ""
> + "mov<tIsa>\t%1, %0"
> + [(set_attr "length" "2,<lImmArith>")]
> +)
> +
> +; Memory => Reg
> +(define_insn "mov<mode>_load"
> + [(set (match_operand:ALLMT 0 "register_operand" "=r")
> + (match_operand:ALLMT 1 "memory_operand" "m"))]
> + ""
> + "load<tIsa>\t%1, %0"
> + [(set_attr "length" "<lImmArith>")]
> +)
> +
> +(define_insn "mov<mode>_store_reg"
> + [(set (match_operand:ALLMT 0 "store_operand" "=m")
> + (match_operand:ALLMT 1 "register_operand" "r"))]
> + ""
> + "stor<tIsa>\t%1, %0"
> + [(set_attr "length" "<lImmArith>")]
> +)
> +
> +(define_insn "mov<mode>_store_imm4"
> + [(set (match_operand:SHORT 0 "store_operand" "=m")
> + (match_operand:SHORT 1 "u4bits_operand" "<LL>"))]
> + ""
> + "stor<tIsaShort>\t%1, %0"
> + [(set_attr "length" "<lImmShort>")]
> +)
These would normally be one pattern with five alternatives. A reg->reg
copy can turn into a reg->mem copy during reload, for example.
--
Rask Ingemann Lambertsen
next prev parent reply other threads:[~2007-07-11 23:33 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-07-10 7:11 Gadad, Pompapathi V
2007-07-11 23:41 ` Rask Ingemann Lambertsen [this message]
2007-07-13 9:22 ` Pompapathi V Gadad
2007-07-13 15:23 ` Rask Ingemann Lambertsen
2007-07-14 4:00 ` Pompapathi V Gadad
2007-07-16 9:14 ` Pompapathi V Gadad
2007-07-16 12:25 ` 'Rask Ingemann Lambertsen'
2007-07-16 13:01 ` Pompapathi V Gadad
2007-07-16 13:08 ` Pompapathi V Gadad
2007-07-20 9:48 ` Pompapathi V Gadad
2007-07-21 14:33 ` 'Rask Ingemann Lambertsen'
2007-07-25 9:40 ` Pompapathi V Gadad
2007-07-30 8:33 ` 'Rask Ingemann Lambertsen'
2007-07-30 9:14 ` Pompapathi V Gadad
2007-08-03 13:03 ` 'Rask Ingemann Lambertsen'
2007-08-06 4:44 ` Pompapathi V Gadad
2007-08-06 10:43 ` 'Rask Ingemann Lambertsen'
2007-08-06 10:49 ` Pompapathi V Gadad
2007-07-21 12:20 ` 'Rask Ingemann Lambertsen'
2007-07-13 15:56 ` Rask Ingemann Lambertsen
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