[PATCH 0/9] New back end ia16: 16-bit Intel x86

[PATCH 0/9] New back end ia16: 16-bit Intel x86

[Rask Ingemann Lambertsen]

   This is a patch set to add a new back end for 16-bit x86 CPUs. I'll be
posting the following nine parts:

1: top-level config.sub
2: reload: reloads_unique_chain_p()
3: reload: reload_reg_free()
4: reload: push_reload() and reload_inner_reg_of_subreg()
5: Misc config stuff and config/ia16
6: docs
7: backends.html
8: testsuite fixes
9: testsuite skip/xfail

   The back end expects code, data and stack to exist in a single 64 kB
segment and hardware floating point is not implemented.

   Test results are at
<URL:http://gcc.gnu.org/ml/gcc-testresults/2007-07/msg01175.html>. I have
more testsuite patches coming, so the results will improve. The simulator
setup is also rather crude at the moment and I'll post a folloup to this
message in the next few days with more details once I tie a few loose ends.

-- 
Rask Ingemann Lambertsen

[PATCH 1/9] New target 16-bit Intel x86

[Rask Ingemann Lambertsen]

To config-patches@gnu.org: You'll receive only this part of the patch set.

2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>

	* config.sub: Add support for 16-bit Intel x86.

Index: config.sub
===================================================================
--- config.sub	(revision 126653)
+++ config.sub	(working copy)
@@ -247,7 +247,7 @@ case $basic_machine in
 	| d10v | d30v | dlx | dsp16xx \
 	| fido | fr30 | frv \
 	| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
-	| i370 | i860 | i960 | ia64 \
+	| i370 | i860 | i960 | ia64 | ia16 \
 	| ip2k | iq2000 \
 	| m32c | m32r | m32rle | m68000 | m68k | m88k \
 	| maxq | mb | microblaze | mcore | mep \
@@ -327,7 +327,7 @@ case $basic_machine in
 	| f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \
 	| h8300-* | h8500-* \
 	| hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \
-	| i*86-* | i860-* | i960-* | ia64-* \
+	| i*86-* | i860-* | i960-* | ia64-* | ia16-* \
 	| ip2k-* | iq2000-* \
 	| m32c-* | m32r-* | m32rle-* \
 	| m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \

-- 
Rask Ingemann Lambertsen

[PATCH 2/9] Fix reloads_unique_chain_p() missing a conflict

[Rask Ingemann Lambertsen]

   As discussed starting with this message
<URL:http://gcc.gnu.org/ml/gcc-patches/2007-07/msg01343.html>, it is
possible for reloads_unique_chain() to miss a reload conflict. It happens
when two reloads are in a different other than expected. Reloads are sorted
using target specific information and besides, the sorting is performed by
qsort() which isn't guaranteed to be stable. The fix here is to check both
reloads passed to reloads_unique_chain_p().

   This and the other two reload patches in this patch set were bootstrapped
and tested together on x86_64-unknown-linux-gnu with no new failures. I also
built and tested cross compilers for arm-unknown-elf, cris-axis-elf,
m32c-unknown-elf, mipsisa64-unknown-elf, sh-unknown-elf and v850-unknown-elf
with no new failures.

   Ok for trunk?

2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>

	* reload1.c (reloads_unique_chain_p): Check both reloads.

Index: gcc/reload1.c
===================================================================
--- gcc/reload1.c	(revision 126653)
+++ gcc/reload1.c	(working copy)
@@ -4960,7 +4976,8 @@ reloads_unique_chain_p (int r1, int r2)
     if (i != r1 && i != r2 && rld[i].in)
       {
 	/* If our reload is mentioned at all, it isn't a simple chain.  */
-	if (reg_mentioned_p (rld[r1].in, rld[i].in))
+	if (reg_mentioned_p (rld[r1].in, rld[i].in)
+	    || reg_mentioned_p (rld[r2].in, rld[i].in))
 	  return false;
       }
   return true;

-- 
Rask Ingemann Lambertsen

PING [PATCH 2/9] Fix reloads_unique_chain_p() missing a conflict

[Rask Ingemann Lambertsen]

On Mon, Jul 30, 2007 at 04:37:45PM +0200, Rask Ingemann Lambertsen wrote:
>    As discussed starting with this message
> <URL:http://gcc.gnu.org/ml/gcc-patches/2007-07/msg01343.html>, it is
> possible for reloads_unique_chain() to miss a reload conflict. It happens
> when two reloads are in a different other than expected. Reloads are sorted
> using target specific information and besides, the sorting is performed by
> qsort() which isn't guaranteed to be stable. The fix here is to check both
> reloads passed to reloads_unique_chain_p().
> 
>    This and the other two reload patches in this patch set were bootstrapped
> and tested together on x86_64-unknown-linux-gnu with no new failures. I also
> built and tested cross compilers for arm-unknown-elf, cris-axis-elf,
> m32c-unknown-elf, mipsisa64-unknown-elf, sh-unknown-elf and v850-unknown-elf
> with no new failures.
> 
>    Ok for trunk?
> 
> 2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>
> 
> 	* reload1.c (reloads_unique_chain_p): Check both reloads.
> 
> Index: gcc/reload1.c
> ===================================================================
> --- gcc/reload1.c	(revision 126653)
> +++ gcc/reload1.c	(working copy)
> @@ -4960,7 +4976,8 @@ reloads_unique_chain_p (int r1, int r2)
>      if (i != r1 && i != r2 && rld[i].in)
>        {
>  	/* If our reload is mentioned at all, it isn't a simple chain.  */
> -	if (reg_mentioned_p (rld[r1].in, rld[i].in))
> +	if (reg_mentioned_p (rld[r1].in, rld[i].in)
> +	    || reg_mentioned_p (rld[r2].in, rld[i].in))
>  	  return false;
>        }
>    return true;
> 
> -- 
> Rask Ingemann Lambertsen

ping^2 [PATCH 2/9] Fix reloads_unique_chain_p() missing a conflict

[Rask Ingemann Lambertsen]

On Mon, Jul 30, 2007 at 04:37:45PM +0200, Rask Ingemann Lambertsen wrote:
>    As discussed starting with this message
> <URL:http://gcc.gnu.org/ml/gcc-patches/2007-07/msg01343.html>, it is
> possible for reloads_unique_chain() to miss a reload conflict. It happens
> when two reloads are in a different other than expected. Reloads are sorted
> using target specific information and besides, the sorting is performed by
> qsort() which isn't guaranteed to be stable. The fix here is to check both
> reloads passed to reloads_unique_chain_p().
> 
>    This and the other two reload patches in this patch set were bootstrapped
> and tested together on x86_64-unknown-linux-gnu with no new failures. I also
> built and tested cross compilers for arm-unknown-elf, cris-axis-elf,
> m32c-unknown-elf, mipsisa64-unknown-elf, sh-unknown-elf and v850-unknown-elf
> with no new failures.
> 
>    Ok for trunk?
> 
> 2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>
> 
> 	* reload1.c (reloads_unique_chain_p): Check both reloads.
> 
> Index: gcc/reload1.c
> ===================================================================
> --- gcc/reload1.c	(revision 126653)
> +++ gcc/reload1.c	(working copy)
> @@ -4960,7 +4976,8 @@ reloads_unique_chain_p (int r1, int r2)
>      if (i != r1 && i != r2 && rld[i].in)
>        {
>  	/* If our reload is mentioned at all, it isn't a simple chain.  */
> -	if (reg_mentioned_p (rld[r1].in, rld[i].in))
> +	if (reg_mentioned_p (rld[r1].in, rld[i].in)
> +	    || reg_mentioned_p (rld[r2].in, rld[i].in))
>  	  return false;
>        }
>    return true;
> 
> -- 
> Rask Ingemann Lambertsen

ping^3 [PATCH] Fix reloads_unique_chain_p() missing a conflict

[Rask Ingemann Lambertsen]

On Mon, Jul 30, 2007 at 04:37:45PM +0200, Rask Ingemann Lambertsen wrote:
>    As discussed starting with this message
> <URL:http://gcc.gnu.org/ml/gcc-patches/2007-07/msg01343.html>, it is
> possible for reloads_unique_chain() to miss a reload conflict. It happens
> when two reloads are in a different other than expected. Reloads are sorted
> using target specific information and besides, the sorting is performed by
> qsort() which isn't guaranteed to be stable. The fix here is to check both
> reloads passed to reloads_unique_chain_p().
> 
>    This and the other two reload patches in this patch set were bootstrapped
> and tested together on x86_64-unknown-linux-gnu with no new failures. I also
> built and tested cross compilers for arm-unknown-elf, cris-axis-elf,
> m32c-unknown-elf, mipsisa64-unknown-elf, sh-unknown-elf and v850-unknown-elf
> with no new failures.
> 
>    Ok for trunk?
> 
> 2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>
> 
> 	* reload1.c (reloads_unique_chain_p): Check both reloads.
> 
> Index: gcc/reload1.c
> ===================================================================
> --- gcc/reload1.c	(revision 126653)
> +++ gcc/reload1.c	(working copy)
> @@ -4960,7 +4976,8 @@ reloads_unique_chain_p (int r1, int r2)
>      if (i != r1 && i != r2 && rld[i].in)
>        {
>  	/* If our reload is mentioned at all, it isn't a simple chain.  */
> -	if (reg_mentioned_p (rld[r1].in, rld[i].in))
> +	if (reg_mentioned_p (rld[r1].in, rld[i].in)
> +	    || reg_mentioned_p (rld[r2].in, rld[i].in))
>  	  return false;
>        }
>    return true;
> 
> -- 
> Rask Ingemann Lambertsen

[PATCH 3/9] reload_reg_free():

[Rask Ingemann Lambertsen]

   In <URL:http://gcc.gnu.org/ml/gcc/2007-06/msg00269.html>, I described a
case where reload allocates a a register for a RELOAD_FOR_OPADDR_ADDR
and in doing so, picks a register inherited for a 
RELOAD_FOR_OPERAND_ADDRESS, thereby clobbering the register. This patch
fixes it by adding a test for this case.

   This and the other two reload patches in this patch set were bootstrapped
and tested together on x86_64-unknown-linux-gnu with no new failures. I also
built and tested cross compilers for arm-unknown-elf, cris-axis-elf,
m32c-unknown-elf, mipsisa64-unknown-elf, sh-unknown-elf and v850-unknown-elf
with no new failures.

  Ok for trunk?

2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>

	* reload1.c (reload_reg_free_p): A register isn't free to use in
	  RELOAD_FOR_OPADDR_ADDR when already inherited for use in
	  RELOAD_FOR_OPERAND_ADDRESS.

Index: gcc/reload1.c
===================================================================
--- gcc/reload1.c	(revision 127048)
+++ gcc/reload1.c	(working copy)
@@ -4745,8 +4745,11 @@ reload_reg_free_p (unsigned int regno, i
     case RELOAD_FOR_OPADDR_ADDR:
       for (i = 0; i < reload_n_operands; i++)
 	if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
 	  return 0;
+      if (TEST_HARD_REG_BIT (reload_reg_used_for_inherit, regno)
+	  && TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
+        return 0;
 
       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
 
     case RELOAD_FOR_OUTPUT:

-- 
Rask Ingemann Lambertsen

PING [PATCH 3/9] reload_reg_free(): don't clobber inherited registers

[Rask Ingemann Lambertsen]

On Mon, Jul 30, 2007 at 05:08:22PM +0200, Rask Ingemann Lambertsen wrote:
>    In <URL:http://gcc.gnu.org/ml/gcc/2007-06/msg00269.html>, I described a
> case where reload allocates a a register for a RELOAD_FOR_OPADDR_ADDR
> and in doing so, picks a register inherited for a 
> RELOAD_FOR_OPERAND_ADDRESS, thereby clobbering the register. This patch
> fixes it by adding a test for this case.
> 
>    This and the other two reload patches in this patch set were bootstrapped
> and tested together on x86_64-unknown-linux-gnu with no new failures. I also
> built and tested cross compilers for arm-unknown-elf, cris-axis-elf,
> m32c-unknown-elf, mipsisa64-unknown-elf, sh-unknown-elf and v850-unknown-elf
> with no new failures.
> 
>   Ok for trunk?
> 
> 2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>
> 
> 	* reload1.c (reload_reg_free_p): A register isn't free to use in
> 	  RELOAD_FOR_OPADDR_ADDR when already inherited for use in
> 	  RELOAD_FOR_OPERAND_ADDRESS.
> 
> Index: gcc/reload1.c
> ===================================================================
> --- gcc/reload1.c	(revision 127048)
> +++ gcc/reload1.c	(working copy)
> @@ -4745,8 +4745,11 @@ reload_reg_free_p (unsigned int regno, i
>      case RELOAD_FOR_OPADDR_ADDR:
>        for (i = 0; i < reload_n_operands; i++)
>  	if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
>  	  return 0;
> +      if (TEST_HARD_REG_BIT (reload_reg_used_for_inherit, regno)
> +	  && TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
> +        return 0;
>  
>        return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
>  
>      case RELOAD_FOR_OUTPUT:
> 
> -- 
> Rask Ingemann Lambertsen

ping^2 [PATCH 3/9] reload_reg_free(): don't clobber inherited registers

[Rask Ingemann Lambertsen]

On Mon, Jul 30, 2007 at 05:08:22PM +0200, Rask Ingemann Lambertsen wrote:
>    In <URL:http://gcc.gnu.org/ml/gcc/2007-06/msg00269.html>, I described a
> case where reload allocates a a register for a RELOAD_FOR_OPADDR_ADDR
> and in doing so, picks a register inherited for a 
> RELOAD_FOR_OPERAND_ADDRESS, thereby clobbering the register. This patch
> fixes it by adding a test for this case.
> 
>    This and the other two reload patches in this patch set were bootstrapped
> and tested together on x86_64-unknown-linux-gnu with no new failures. I also
> built and tested cross compilers for arm-unknown-elf, cris-axis-elf,
> m32c-unknown-elf, mipsisa64-unknown-elf, sh-unknown-elf and v850-unknown-elf
> with no new failures.
> 
>   Ok for trunk?
> 
> 2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>
> 
> 	* reload1.c (reload_reg_free_p): A register isn't free to use in
> 	  RELOAD_FOR_OPADDR_ADDR when already inherited for use in
> 	  RELOAD_FOR_OPERAND_ADDRESS.
> 
> Index: gcc/reload1.c
> ===================================================================
> --- gcc/reload1.c	(revision 127048)
> +++ gcc/reload1.c	(working copy)
> @@ -4745,8 +4745,11 @@ reload_reg_free_p (unsigned int regno, i
>      case RELOAD_FOR_OPADDR_ADDR:
>        for (i = 0; i < reload_n_operands; i++)
>  	if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
>  	  return 0;
> +      if (TEST_HARD_REG_BIT (reload_reg_used_for_inherit, regno)
> +	  && TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
> +        return 0;
>  
>        return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
>  
>      case RELOAD_FOR_OUTPUT:
> 
> -- 
> Rask Ingemann Lambertsen

ping^3 [PATCH] reload_reg_free(): don't clobber inherited registers

[Rask Ingemann Lambertsen]

On Mon, Jul 30, 2007 at 05:08:22PM +0200, Rask Ingemann Lambertsen wrote:
>    In <URL:http://gcc.gnu.org/ml/gcc/2007-06/msg00269.html>, I described a
> case where reload allocates a a register for a RELOAD_FOR_OPADDR_ADDR
> and in doing so, picks a register inherited for a 
> RELOAD_FOR_OPERAND_ADDRESS, thereby clobbering the register. This patch
> fixes it by adding a test for this case.
> 
>    This and the other two reload patches in this patch set were bootstrapped
> and tested together on x86_64-unknown-linux-gnu with no new failures. I also
> built and tested cross compilers for arm-unknown-elf, cris-axis-elf,
> m32c-unknown-elf, mipsisa64-unknown-elf, sh-unknown-elf and v850-unknown-elf
> with no new failures.
> 
>   Ok for trunk?
> 
> 2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>
> 
> 	* reload1.c (reload_reg_free_p): A register isn't free to use in
> 	  RELOAD_FOR_OPADDR_ADDR when already inherited for use in
> 	  RELOAD_FOR_OPERAND_ADDRESS.
> 
> Index: gcc/reload1.c
> ===================================================================
> --- gcc/reload1.c	(revision 127048)
> +++ gcc/reload1.c	(working copy)
> @@ -4745,8 +4745,11 @@ reload_reg_free_p (unsigned int regno, i
>      case RELOAD_FOR_OPADDR_ADDR:
>        for (i = 0; i < reload_n_operands; i++)
>  	if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
>  	  return 0;
> +      if (TEST_HARD_REG_BIT (reload_reg_used_for_inherit, regno)
> +	  && TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
> +        return 0;
>  
>        return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
>  
>      case RELOAD_FOR_OUTPUT:
> 
> -- 
> Rask Ingemann Lambertsen

[PATCH 4/9] Subreg handling in reload_inner_reg_of_subreg() and push_reload()

[Rask Ingemann Lambertsen]

   In <URL:http://gcc.gnu.org/ml/gcc/2007-05/msg00505.html> and
<URL:http://gcc.gnu.org/ml/gcc-patches/2007-05/msg01570.html> (which was
briefly discussed) I described a case where reload is given HImode subreg of
a multiword SImode hard reg. Because the HImode subreg is made of two QImode
hard regs rather than one HImode hard reg, reload decides to write to the
whole SImode hard reg instead of just the HImode subreg on the assumption
that the subreg is "problematic", as a comment puts it. In fact, the rest of
reload handles such a subreg just fine with no special treatment. This patch
adjusts the checks in reload_inner_reg_of_subreg() and push_reload()
accordingly.

   This and the other two reload patches in this patch set were bootstrapped
and tested together on x86_64-unknown-linux-gnu with no new failures. I also
built and tested cross compilers for arm-unknown-elf, cris-axis-elf,
m32c-unknown-elf, mipsisa64-unknown-elf, sh-unknown-elf and v850-unknown-elf
with no new failures.

   Ok for trunk?

2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>

	* reload.c (reload_inner_reg_of_subreg): No special handling is
	  needed if a subreg consists of more hard regs than words.
	  (push_reload): Likewise.

Index: gcc/reload.c
===================================================================
--- gcc/reload.c	(revision 126653)
+++ gcc/reload.c	(working copy)
@@ -809,13 +809,13 @@ reload_inner_reg_of_subreg (rtx x, enum 
     return 1;
 
   /* If the outer part is a word or smaller, INNER larger than a
-     word and the number of regs for INNER is not the same as the
+     word and the number of regs for INNER is smaller than the
      number of words in INNER, then INNER will need reloading.  */
   return (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
 	  && output
 	  && GET_MODE_SIZE (GET_MODE (inner)) > UNITS_PER_WORD
 	  && ((GET_MODE_SIZE (GET_MODE (inner)) / UNITS_PER_WORD)
-	      != (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)]));
+	      > (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)]));
 }
 
 /* Return nonzero if IN can be reloaded into REGNO with mode MODE without
@@ -1035,8 +1035,8 @@ push_reload (rtx in, rtx out, rtx *inloc
 		       > UNITS_PER_WORD)
 		   && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
 			/ UNITS_PER_WORD)
-		       != (int) hard_regno_nregs[REGNO (SUBREG_REG (in))]
-						[GET_MODE (SUBREG_REG (in))]))
+		       > (int) hard_regno_nregs[REGNO (SUBREG_REG (in))]
+					       [GET_MODE (SUBREG_REG (in))]))
 		  || ! HARD_REGNO_MODE_OK (subreg_regno (in), inmode)))
 	  || (secondary_reload_class (1, class, inmode, in) != NO_REGS
 	      && (secondary_reload_class (1, class, GET_MODE (SUBREG_REG (in)),
@@ -1128,8 +1128,8 @@ push_reload (rtx in, rtx out, rtx *inloc
 		       > UNITS_PER_WORD)
 		   && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
 			/ UNITS_PER_WORD)
-		       != (int) hard_regno_nregs[REGNO (SUBREG_REG (out))]
-						[GET_MODE (SUBREG_REG (out))]))
+		       > (int) hard_regno_nregs[REGNO (SUBREG_REG (out))]
+					       [GET_MODE (SUBREG_REG (out))]))
 		  || ! HARD_REGNO_MODE_OK (subreg_regno (out), outmode)))
 	  || (secondary_reload_class (0, class, outmode, out) != NO_REGS
 	      && (secondary_reload_class (0, class, GET_MODE (SUBREG_REG (out)),

-- 
Rask Ingemann Lambertsen

PING [PATCH 4/9] Subreg handling in reload_inner_reg_of_subreg() and push_reload()

[Rask Ingemann Lambertsen]

On Mon, Jul 30, 2007 at 06:10:23PM +0200, Rask Ingemann Lambertsen wrote:
>    In <URL:http://gcc.gnu.org/ml/gcc/2007-05/msg00505.html> and
> <URL:http://gcc.gnu.org/ml/gcc-patches/2007-05/msg01570.html> (which was
> briefly discussed) I described a case where reload is given HImode subreg of
> a multiword SImode hard reg. Because the HImode subreg is made of two QImode
> hard regs rather than one HImode hard reg, reload decides to write to the
> whole SImode hard reg instead of just the HImode subreg on the assumption
> that the subreg is "problematic", as a comment puts it. In fact, the rest of
> reload handles such a subreg just fine with no special treatment. This patch
> adjusts the checks in reload_inner_reg_of_subreg() and push_reload()
> accordingly.
> 
>    This and the other two reload patches in this patch set were bootstrapped
> and tested together on x86_64-unknown-linux-gnu with no new failures. I also
> built and tested cross compilers for arm-unknown-elf, cris-axis-elf,
> m32c-unknown-elf, mipsisa64-unknown-elf, sh-unknown-elf and v850-unknown-elf
> with no new failures.
> 
>    Ok for trunk?
> 
> 2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>
> 
> 	* reload.c (reload_inner_reg_of_subreg): No special handling is
> 	  needed if a subreg consists of more hard regs than words.
> 	  (push_reload): Likewise.
> 
> Index: gcc/reload.c
> ===================================================================
> --- gcc/reload.c	(revision 126653)
> +++ gcc/reload.c	(working copy)
> @@ -809,13 +809,13 @@ reload_inner_reg_of_subreg (rtx x, enum 
>      return 1;
>  
>    /* If the outer part is a word or smaller, INNER larger than a
> -     word and the number of regs for INNER is not the same as the
> +     word and the number of regs for INNER is smaller than the
>       number of words in INNER, then INNER will need reloading.  */
>    return (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
>  	  && output
>  	  && GET_MODE_SIZE (GET_MODE (inner)) > UNITS_PER_WORD
>  	  && ((GET_MODE_SIZE (GET_MODE (inner)) / UNITS_PER_WORD)
> -	      != (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)]));
> +	      > (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)]));
>  }
>  
>  /* Return nonzero if IN can be reloaded into REGNO with mode MODE without
> @@ -1035,8 +1035,8 @@ push_reload (rtx in, rtx out, rtx *inloc
>  		       > UNITS_PER_WORD)
>  		   && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
>  			/ UNITS_PER_WORD)
> -		       != (int) hard_regno_nregs[REGNO (SUBREG_REG (in))]
> -						[GET_MODE (SUBREG_REG (in))]))
> +		       > (int) hard_regno_nregs[REGNO (SUBREG_REG (in))]
> +					       [GET_MODE (SUBREG_REG (in))]))
>  		  || ! HARD_REGNO_MODE_OK (subreg_regno (in), inmode)))
>  	  || (secondary_reload_class (1, class, inmode, in) != NO_REGS
>  	      && (secondary_reload_class (1, class, GET_MODE (SUBREG_REG (in)),
> @@ -1128,8 +1128,8 @@ push_reload (rtx in, rtx out, rtx *inloc
>  		       > UNITS_PER_WORD)
>  		   && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
>  			/ UNITS_PER_WORD)
> -		       != (int) hard_regno_nregs[REGNO (SUBREG_REG (out))]
> -						[GET_MODE (SUBREG_REG (out))]))
> +		       > (int) hard_regno_nregs[REGNO (SUBREG_REG (out))]
> +					       [GET_MODE (SUBREG_REG (out))]))
>  		  || ! HARD_REGNO_MODE_OK (subreg_regno (out), outmode)))
>  	  || (secondary_reload_class (0, class, outmode, out) != NO_REGS
>  	      && (secondary_reload_class (0, class, GET_MODE (SUBREG_REG (out)),
> 
> -- 
> Rask Ingemann Lambertsen

ping^2 [PATCH 4/9] Subreg handling in reload_inner_reg_of_subreg() and push_reload()

[Rask Ingemann Lambertsen]

On Mon, Jul 30, 2007 at 06:10:23PM +0200, Rask Ingemann Lambertsen wrote:
>    In <URL:http://gcc.gnu.org/ml/gcc/2007-05/msg00505.html> and
> <URL:http://gcc.gnu.org/ml/gcc-patches/2007-05/msg01570.html> (which was
> briefly discussed) I described a case where reload is given HImode subreg of
> a multiword SImode hard reg. Because the HImode subreg is made of two QImode
> hard regs rather than one HImode hard reg, reload decides to write to the
> whole SImode hard reg instead of just the HImode subreg on the assumption
> that the subreg is "problematic", as a comment puts it. In fact, the rest of
> reload handles such a subreg just fine with no special treatment. This patch
> adjusts the checks in reload_inner_reg_of_subreg() and push_reload()
> accordingly.
> 
>    This and the other two reload patches in this patch set were bootstrapped
> and tested together on x86_64-unknown-linux-gnu with no new failures. I also
> built and tested cross compilers for arm-unknown-elf, cris-axis-elf,
> m32c-unknown-elf, mipsisa64-unknown-elf, sh-unknown-elf and v850-unknown-elf
> with no new failures.
> 
>    Ok for trunk?
> 
> 2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>
> 
> 	* reload.c (reload_inner_reg_of_subreg): No special handling is
> 	  needed if a subreg consists of more hard regs than words.
> 	  (push_reload): Likewise.
> 
> Index: gcc/reload.c
> ===================================================================
> --- gcc/reload.c	(revision 126653)
> +++ gcc/reload.c	(working copy)
> @@ -809,13 +809,13 @@ reload_inner_reg_of_subreg (rtx x, enum 
>      return 1;
>  
>    /* If the outer part is a word or smaller, INNER larger than a
> -     word and the number of regs for INNER is not the same as the
> +     word and the number of regs for INNER is smaller than the
>       number of words in INNER, then INNER will need reloading.  */
>    return (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
>  	  && output
>  	  && GET_MODE_SIZE (GET_MODE (inner)) > UNITS_PER_WORD
>  	  && ((GET_MODE_SIZE (GET_MODE (inner)) / UNITS_PER_WORD)
> -	      != (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)]));
> +	      > (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)]));
>  }
>  
>  /* Return nonzero if IN can be reloaded into REGNO with mode MODE without
> @@ -1035,8 +1035,8 @@ push_reload (rtx in, rtx out, rtx *inloc
>  		       > UNITS_PER_WORD)
>  		   && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
>  			/ UNITS_PER_WORD)
> -		       != (int) hard_regno_nregs[REGNO (SUBREG_REG (in))]
> -						[GET_MODE (SUBREG_REG (in))]))
> +		       > (int) hard_regno_nregs[REGNO (SUBREG_REG (in))]
> +					       [GET_MODE (SUBREG_REG (in))]))
>  		  || ! HARD_REGNO_MODE_OK (subreg_regno (in), inmode)))
>  	  || (secondary_reload_class (1, class, inmode, in) != NO_REGS
>  	      && (secondary_reload_class (1, class, GET_MODE (SUBREG_REG (in)),
> @@ -1128,8 +1128,8 @@ push_reload (rtx in, rtx out, rtx *inloc
>  		       > UNITS_PER_WORD)
>  		   && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
>  			/ UNITS_PER_WORD)
> -		       != (int) hard_regno_nregs[REGNO (SUBREG_REG (out))]
> -						[GET_MODE (SUBREG_REG (out))]))
> +		       > (int) hard_regno_nregs[REGNO (SUBREG_REG (out))]
> +					       [GET_MODE (SUBREG_REG (out))]))
>  		  || ! HARD_REGNO_MODE_OK (subreg_regno (out), outmode)))
>  	  || (secondary_reload_class (0, class, outmode, out) != NO_REGS
>  	      && (secondary_reload_class (0, class, GET_MODE (SUBREG_REG (out)),
> 
> -- 
> Rask Ingemann Lambertsen

ping^3 [PATCH] Subreg handling in reload_inner_reg_of_subreg() and push_reload()

[Rask Ingemann Lambertsen]

On Mon, Jul 30, 2007 at 06:10:23PM +0200, Rask Ingemann Lambertsen wrote:
>    In <URL:http://gcc.gnu.org/ml/gcc/2007-05/msg00505.html> and
> <URL:http://gcc.gnu.org/ml/gcc-patches/2007-05/msg01570.html> (which was
> briefly discussed) I described a case where reload is given HImode subreg of
> a multiword SImode hard reg. Because the HImode subreg is made of two QImode
> hard regs rather than one HImode hard reg, reload decides to write to the
> whole SImode hard reg instead of just the HImode subreg on the assumption
> that the subreg is "problematic", as a comment puts it. In fact, the rest of
> reload handles such a subreg just fine with no special treatment. This patch
> adjusts the checks in reload_inner_reg_of_subreg() and push_reload()
> accordingly.
> 
>    This and the other two reload patches in this patch set were bootstrapped
> and tested together on x86_64-unknown-linux-gnu with no new failures. I also
> built and tested cross compilers for arm-unknown-elf, cris-axis-elf,
> m32c-unknown-elf, mipsisa64-unknown-elf, sh-unknown-elf and v850-unknown-elf
> with no new failures.
> 
>    Ok for trunk?
> 
> 2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>
> 
> 	* reload.c (reload_inner_reg_of_subreg): No special handling is
> 	  needed if a subreg consists of more hard regs than words.
> 	  (push_reload): Likewise.
> 
> Index: gcc/reload.c
> ===================================================================
> --- gcc/reload.c	(revision 126653)
> +++ gcc/reload.c	(working copy)
> @@ -809,13 +809,13 @@ reload_inner_reg_of_subreg (rtx x, enum 
>      return 1;
>  
>    /* If the outer part is a word or smaller, INNER larger than a
> -     word and the number of regs for INNER is not the same as the
> +     word and the number of regs for INNER is smaller than the
>       number of words in INNER, then INNER will need reloading.  */
>    return (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
>  	  && output
>  	  && GET_MODE_SIZE (GET_MODE (inner)) > UNITS_PER_WORD
>  	  && ((GET_MODE_SIZE (GET_MODE (inner)) / UNITS_PER_WORD)
> -	      != (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)]));
> +	      > (int) hard_regno_nregs[REGNO (inner)][GET_MODE (inner)]));
>  }
>  
>  /* Return nonzero if IN can be reloaded into REGNO with mode MODE without
> @@ -1035,8 +1035,8 @@ push_reload (rtx in, rtx out, rtx *inloc
>  		       > UNITS_PER_WORD)
>  		   && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))
>  			/ UNITS_PER_WORD)
> -		       != (int) hard_regno_nregs[REGNO (SUBREG_REG (in))]
> -						[GET_MODE (SUBREG_REG (in))]))
> +		       > (int) hard_regno_nregs[REGNO (SUBREG_REG (in))]
> +					       [GET_MODE (SUBREG_REG (in))]))
>  		  || ! HARD_REGNO_MODE_OK (subreg_regno (in), inmode)))
>  	  || (secondary_reload_class (1, class, inmode, in) != NO_REGS
>  	      && (secondary_reload_class (1, class, GET_MODE (SUBREG_REG (in)),
> @@ -1128,8 +1128,8 @@ push_reload (rtx in, rtx out, rtx *inloc
>  		       > UNITS_PER_WORD)
>  		   && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))
>  			/ UNITS_PER_WORD)
> -		       != (int) hard_regno_nregs[REGNO (SUBREG_REG (out))]
> -						[GET_MODE (SUBREG_REG (out))]))
> +		       > (int) hard_regno_nregs[REGNO (SUBREG_REG (out))]
> +					       [GET_MODE (SUBREG_REG (out))]))
>  		  || ! HARD_REGNO_MODE_OK (subreg_regno (out), outmode)))
>  	  || (secondary_reload_class (0, class, outmode, out) != NO_REGS
>  	      && (secondary_reload_class (0, class, GET_MODE (SUBREG_REG (out)),
> 
> -- 
> Rask Ingemann Lambertsen

Re: [PATCH 5/9] Libgcc bits and the back end itself

[Rask Ingemann Lambertsen]

[-- Attachment #1: Type: text/plain, Size: 697 bytes --]

   This part includes all the bits needed to make the new back end build.

   Ok for trunk?

libgcc/
2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>

	* config.host: Add support for ia16.
	* ia16/t-ia16: New.

gcc/
2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>
	* config.gcc: Add support for ia16.
	* config/ia16/ia16.md: New.
	* config/ia16/ia16-peepholes.md: New.
	* config/ia16/ia16.opt: New.
	* config/ia16/ia16.c: New.
	* config/ia16/t-ia16: New.
	* config/ia16/ia16-modes.def: New.
	* config/ia16/predicates.md: New.
	* config/ia16/constraints.md: New.
	* config/ia16/ia16.h: New.
	* config/ia16/ia16-protos.h: New.
	* config/ia16/elf.h: New.

-- 
Rask Ingemann Lambertsen

[-- Attachment #2: ia16-gcc.patch.gz --]
[-- Type: application/x-gzip, Size: 50613 bytes --]

[PATCH 6/9] Documentation for the ia16 back end

[Rask Ingemann Lambertsen]

   This patch updates the documentation. I checked with "make info", "make
dvi" and by viewing the resulting DVI files that it causes no obvious
problems.

2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>

	* doc/md.texi: Update for new ia16 back end.
	* doc/invoke.texi: Likewise.
	* doc/contrib.texi: Likewise.
	* doc/install.texi: Likewise.

Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi	(revision 127048)
+++ gcc/doc/invoke.texi	(working copy)
@@ -560,6 +560,9 @@
 -mcmodel=@var{code-model} @gol
 -m32  -m64 -mlarge-data-threshold=@var{num}}
 
+@emph{IA-16 Options}
+@gccoptlist{-mtune=@var{cpu-type}  -march=@var{cpu-type} -mshort-jumps}
+
 @emph{IA-64 Options}
 @gccoptlist{-mbig-endian  -mlittle-endian  -mgnu-as  -mgnu-ld  -mno-pic @gol
 -mvolatile-asm-stop  -mregister-names  -mno-sdata @gol
@@ -7997,6 +8000,7 @@
 * H8/300 Options::
 * HPPA Options::
 * i386 and x86-64 Options::
+* IA-16 Options::
 * IA-64 Options::
 * M32C Options::
 * M32R/D Options::
@@ -10517,6 +10521,65 @@
 about addresses and sizes of sections.
 @end table
 
+@node IA-16 Options
+@subsection IA-16 Options
+@cindex IA-16 Options
+
+These are the @samp{-m} options defined for the Intel IA-16 architecture.
+
+@table @gcctabopt
+@item -mtune=@var{cpu-type}
+@opindex mtune
+Tune to @var{cpu-type} everything applicable about the generated code, except
+for the ABI and the set of available instructions.  The choices for
+@var{cpu-type} are:
+@table @emph
+@item i8086
+The Intel 8086.
+
+@item i8088
+The Intel 8088.
+
+@item i8086
+The Intel 8086.
+
+@item i80186
+The Intel 80186.
+
+@item i80286
+The Intel 80286.
+
+@item v20
+The NEC V20.
+
+@item v30
+The NEC V30.
+
+@item any
+Any CPU listed above.  The aim is to generate code which runs reasonably
+well on any CPU listed above.
+
+@item any_186
+As with @option{-mtune=any}, but assume a CPU which supports immediate
+operands for push, imul and shift/rotate instructions.
+@end table
+
+@item -march=@var{cpu-type}
+@opindex march
+Generate instructions for the machine type @var{cpu-type}.  The choices
+for @var{cpu-type} are the same as for @option{-mtune}.  Moreover,
+specifying @option{-march=@var{cpu-type}} implies @option{-mtune=@var{cpu-type}}.
+
+@item -mshort-jumps
+@itemx -mno-short-jumps
+@opindex mshort-jumps
+@opindex mno-short-jumps
+Allow (or disallow) the use of jump instructions which can only jump
+@minus{}128/+127 bytes.  The default is not to use them.  This option only
+affects instructions for which the assembler doesn't provide a work-around
+and the compiler doesn't know the jump displacement.
+@end table
+
 @node IA-64 Options
 @subsection IA-64 Options
 @cindex IA-64 Options
Index: gcc/doc/contrib.texi
===================================================================
--- gcc/doc/contrib.texi	(revision 127048)
+++ gcc/doc/contrib.texi	(working copy)
@@ -476,6 +476,9 @@
 68020 system.
 
 @item
+Rask Ingemann Lambertsen contributed the 16-bit Intel x86 back end.
+
+@item
 Asher Langton and Mike Kumbera for contributing Cray pointer support
 to GNU Fortran, and for other GNU Fortran improvements.
 
Index: gcc/doc/md.texi
===================================================================
--- gcc/doc/md.texi	(revision 127048)
+++ gcc/doc/md.texi	(working copy)
@@ -1,5 +1,5 @@
 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
-@c 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
+@c 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
 @c This is part of the GCC manual.
 @c For copying conditions, see the file gcc.texi.
 
@@ -2083,6 +2083,120 @@
 
 @end table
 
+@item Intel IA-16---@file{config/ia16/constraints.md}
+@table @code
+@item a
+The @code{ax} register.
+
+@item b
+The @code{bx} register.
+
+@item c
+The @code{cx} register.
+
+@item d
+The @code{dx} register.
+
+@item S
+The @code{si} register.
+
+@item D
+The @code{di} register.
+
+@item Ral
+The @code{al} register.
+
+@item Rah
+The @code{ah} register.
+
+@item Rcl
+The @code{cl} register.
+
+@item Rbp
+The @code{bp} register.
+
+@item q
+Any 8-bit register.
+
+@item T
+Any general or segment register.
+
+@item A
+The @code{dx:ax} register pair.
+
+@item j
+The @code{bx:dx} register pair.
+
+@item l
+The lower half of pairs of 8-bit registers.
+
+@item u
+The upper half of pairs of 8-bit registers.
+
+@item k
+Any 32-bit register group with access to the two lower bytes.
+
+@item x
+The @code{si} and @code{di} registers.
+
+@item w
+The @code{bx} and @code{bp} registers.
+
+@item B
+The @code{bx}, @code{si}, @code{di} and @code{bp} registers.
+
+@item Q
+Any segment register.
+
+@item Z
+The constant 0.
+
+@item P1
+The constant 1.
+
+@item M1
+The constant @minus{}1.
+
+@item Um
+The constant @minus{}256.
+
+@item Lbm
+The constant 255.
+
+@item Lor
+Constants 128 @dots{} 254.
+
+@item Lom
+Constants 1 @dots{} 254.
+
+@item Lar
+Constants @minus{}255 @dots{} @minus{}129.
+
+@item Lam
+Constants @minus{}255 @dots{} @minus{}2.
+
+@item Uo
+Constants 0xXX00 except @minus{}256.
+
+@item Ua
+Constants 0xXXFF.
+
+@item Ish
+A constant usable as a shift count.
+
+@item Iaa
+A constant multiplier for the @code{aad} instruction.
+
+@item Ipu
+A constant usable with the @code{push} instruction.
+
+@item Imu
+A constant usable with the @code{imul} instruction except 257.
+
+@item I11
+The constant 257.
+@end table
+
 @item Intel IA-64---@file{config/ia64/ia64.h}
 @table @code
 @item a
Index: gcc/doc/install.texi
===================================================================
--- gcc/doc/install.texi	(revision 127048)
+++ gcc/doc/install.texi	(working copy)
@@ -2451,6 +2451,8 @@
 @item
 @uref{#ix86-x-udk,,i?86-*-udk}
 @item
+@uref{#ia16-x-elf,,ia16-*-elf}
+@item
 @uref{#ia64-x-linux,,ia64-*-linux}
 @item
 @uref{#ia64-x-hpux,,ia64-*-hpux*}
@@ -3266,6 +3268,17 @@
 @html
 <hr />
 @end html
+@heading @anchor{ia16-x-elf}ia16-*-elf
+Intel 16-bit x86 processor configuration for embedded systems.
+
+There is no binutils configuration for this target, but binutils
+configurations for @samp{i?86} ELF systems can be used.  Binutils
+releases from around 2001 or later can be used.
+
+
+@html
+<hr />
+@end html
 @heading @anchor{ia64-x-linux}ia64-*-linux
 IA-64 processor (also known as IPF, or Itanium Processor Family)
 running GNU/Linux.

-- 
Rask Ingemann Lambertsen

Re: [PATCH 6/9] Documentation for the ia16 back end

[Joseph S. Myers]

On Mon, 30 Jul 2007, Rask Ingemann Lambertsen wrote:

> +@item i8086
> +The Intel 8086.

> +@item i8086
> +The Intel 8086.

Duplicate table entries.

-- 
Joseph S. Myers
joseph@codesourcery.com

[PATCH 7/9][wwwdocs] Mention ia16 in backends.html

[Rask Ingemann Lambertsen]

   Checked with the W3 HTML validator and it passed.

Index: htdocs/backends.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/backends.html,v
retrieving revision 1.34
diff -u -r1.34 backends.html
--- htdocs/backends.html	6 Mar 2007 10:34:54 -0000	1.34
+++ htdocs/backends.html	30 Jul 2007 09:12:51 -0000
@@ -77,6 +77,7 @@
 frv      | ??       B      p    da  s
 h8300    |       FI       cp g      s
 i386     |   ? Q        q  p    da   
+ia16     |  ??L        l   p g b     
 ia64     |   ? Q   C    qr p    da   
 iq2000   | ???   FICB      p g  d t  
 m32c     |    L  FI    l   p g      s

-- 
Rask Ingemann Lambertsen

Re: [PATCH 7/9][wwwdocs] Mention ia16 in backends.html

[Gerald Pfeifer]

On Mon, 30 Jul 2007, Rask Ingemann Lambertsen wrote:
> Checked with the W3 HTML validator and it passed.

Please go ahead and commit this as obvious (once the majority of the other
pieces is in).  Well, or commit it as approved, of course. ;-)

Gerald

[PATCH 8/9] Vectorizer testsuite fixes

[Rask Ingemann Lambertsen]

   This patch allows two vectorizer tests to work on 16-bit targets by
making the vector elements of type "char". This fixes two failures on
ia16-unkonwn-elf and m32c-unknown-elf with no changes on
x86_64-unknown-linux-gnu, arm-unknown-elf, cris-axis-elf,
mipsisa64-unknown-elf, sh-unknown-elf or v850-unknown-elf. Ok for trunk?

:ADDPATCH testsuite:

2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>

	* gcc.dg/tree-ssa/gen-vect-2.c: Use "char" for vector elements if
	  "int" is only 16 bit bits wide.
	* gcc.dg/tree-ssa/gen-vect-11a.c: Likewise.

Index: gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c
===================================================================
--- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c	(revision 126653)
+++ gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c	(working copy)
@@ -5,7 +5,9 @@
 
 #define N 16
  
-#if __LONG_MAX__ == 2147483647
+#if __INT_MAX__ == 32767
+typedef char half_word;
+#elif __LONG_MAX__ == 2147483647
 typedef short half_word;
 #else
 typedef int half_word;
Index: gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c
===================================================================
--- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c	(revision 126653)
+++ gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c	(working copy)
@@ -5,7 +5,9 @@
 
 #define N 16
 
-#if __LONG_MAX__ == 2147483647
+#if __INT_MAX__ == 32767
+typedef char half_word;
+#elif __LONG_MAX__ == 2147483647
 typedef short half_word;
 #else
 typedef int half_word;


-- 
Rask Ingemann Lambertsen

Re: [PATCH 8/9] Vectorizer testsuite fixes

[Janis Johnson]

On Mon, 2007-07-30 at 21:34 +0200, Rask Ingemann Lambertsen wrote:
>    This patch allows two vectorizer tests to work on 16-bit targets by
> making the vector elements of type "char". This fixes two failures on
> ia16-unkonwn-elf and m32c-unknown-elf with no changes on
> x86_64-unknown-linux-gnu, arm-unknown-elf, cris-axis-elf,
> mipsisa64-unknown-elf, sh-unknown-elf or v850-unknown-elf. Ok for trunk?

This is OK.

Janis

[PATCH 9/9] Skip or xfail some tests on ia16

[Rask Ingemann Lambertsen]

   This patch disables several tests for features which aren't available on
ia16. I tested it along with patch 8 in this patch set. Ok for trunk?

:ADDPATCH testsuite:

2007-07-30  Rask Ingemann Lambertsen  <rask@sygehus.dk>

	* gcc.dg/20020312-2.c: Skip test of unsupported feature on ia16.
	* gcc.c-torture/compile/20010327-1.c: Likewise.
	* gcc.c-torture/compile/20020604-1.c: Likewise.
	* gcc.dg/pr27639.c: Likewise.
	* gcc.dg/pr19340.c: Likewise.
	* gcc.dg/cpp/_Pragma6.c: Likewise.
	* gcc.dg/20040813-1.c: Likewise.
	* gcc.dg/sibcall-3.c: Xfail on ia16 until sibling calls work.
	* gcc.dg/sibcall-4.c: Likewise.

Index: gcc/testsuite/gcc.dg/20020312-2.c
===================================================================
--- gcc/testsuite/gcc.dg/20020312-2.c	(revision 126653)
+++ gcc/testsuite/gcc.dg/20020312-2.c	(working copy)
@@ -80,6 +80,8 @@ extern void abort (void);
 # else
 #  define PIC_REG "gr17"
 #endif
+#elif defined(__ia16__)
+/* No pic register.  */
 #else
 # error "Modify the test for your target."
 #endif
Index: gcc/testsuite/gcc.c-torture/compile/20010327-1.c
===================================================================
--- gcc/testsuite/gcc.c-torture/compile/20010327-1.c	(revision 126653)
+++ gcc/testsuite/gcc.c-torture/compile/20010327-1.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-skip-if "non-SI pointers" { m32c-*-* } { "*" } { "" } } */
+/* { dg-skip-if "non-SI pointers" { m32c-*-* ia16-*-* } { "*" } { "" } } */
 
 /* This testcase tests whether GCC can produce static initialized data
    that references addresses of size 'unsigned long', even if that's not
Index: gcc/testsuite/gcc.c-torture/compile/20020604-1.c
===================================================================
--- gcc/testsuite/gcc.c-torture/compile/20020604-1.c	(revision 126653)
+++ gcc/testsuite/gcc.c-torture/compile/20020604-1.c	(working copy)
@@ -1,7 +1,7 @@
 /* The array is too big. */
 /* { dg-xfail-if "The array too big" { "h8300-*-*" } { "-mno-h" "-mn" } { "" } } */
 /* { dg-do assemble { xfail m6811-*-* m6812-*-* } } */
-/* { dg-skip-if "" { m32c-*-* } { } { } } */
+/* { dg-skip-if "" { m32c-*-* ia16-*-* } { } { } } */
 
 /* PR c/6957
    This testcase ICEd at -O2 on IA-32, because
Index: gcc/testsuite/gcc.dg/pr27639.c
===================================================================
--- gcc/testsuite/gcc.dg/pr27639.c	(revision 126653)
+++ gcc/testsuite/gcc.dg/pr27639.c	(working copy)
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -std=c99" } */
+/* { dg-skip-if "Array too large" { ia16-*-* } { "*" } { "" } } */
 
 char heap[50000];
 
Index: gcc/testsuite/gcc.dg/pr19340.c
===================================================================
--- gcc/testsuite/gcc.dg/pr19340.c	(revision 126653)
+++ gcc/testsuite/gcc.dg/pr19340.c	(working copy)
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-O1 -fschedule-insns2 -fsched2-use-traces" } */
-/* { dg-skip-if "No scheduling" { mmix-*-* cris-*-* fido-*-* m68k-*-* m32c-*-* } { "*" } { "" } } */
+/* { dg-skip-if "No scheduling" { mmix-*-* cris-*-* fido-*-* m68k-*-* m32c-*-* ia16-*-* } { "*" } { "" } } */
 
 extern double f (double x);
 
Index: gcc/testsuite/gcc.dg/cpp/_Pragma6.c
===================================================================
--- gcc/testsuite/gcc.dg/cpp/_Pragma6.c	(revision 126653)
+++ gcc/testsuite/gcc.dg/cpp/_Pragma6.c	(working copy)
@@ -2,7 +2,7 @@
 /* This is supposed to succeed only if
    the target defines HANDLE_PRAGMA_PACK_PUSH_POP
    and doesn't define HANDLE_PRAGMA_PACK_WITH_EXPANSION.  */
-/* { dg-do compile { target { ! { *-*-solaris2* fido-*-* m68k-*-* sh*-[us]*-elf } } } } */
+/* { dg-do compile { target { ! { *-*-solaris2* fido-*-* m68k-*-* sh*-[us]*-elf ia16-*-* } } } } */
 
 #define push bar
 #define foo _Pragma ("pack(push)")
Index: gcc/testsuite/gcc.dg/20040813-1.c
===================================================================
--- gcc/testsuite/gcc.dg/20040813-1.c	(revision 126653)
+++ gcc/testsuite/gcc.dg/20040813-1.c	(working copy)
@@ -2,7 +2,7 @@
 /* Contributed by Devang Patel  <dpatel@apple.com>  */
 
 /* { dg-do compile } */
-/* { dg-skip-if "No stabs" { mmix-*-* *-*-aix* *-*-netware* alpha*-*-* hppa*64*-*-* ia64-*-* *-*-sysv5* *-*-vxworks* } { "*" } { "" } } */
+/* { dg-skip-if "No stabs" { mmix-*-* *-*-aix* *-*-netware* alpha*-*-* hppa*64*-*-* ia64-*-* *-*-sysv5* *-*-vxworks* ia16-*-* } { "*" } { "" } } */
 /* { dg-options "-gstabs" } */
 
 int
Index: gcc/testsuite/gcc.dg/sibcall-3.c
===================================================================
--- gcc/testsuite/gcc.dg/sibcall-3.c	(revision 127048)
+++ gcc/testsuite/gcc.dg/sibcall-3.c	(working copy)
@@ -5,7 +5,7 @@
    Copyright (C) 2002 Free Software Foundation Inc.
    Contributed by Hans-Peter Nilsson  <hp@bitrange.com>  */
 
-/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
+/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* ia16-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
 /* -mlongcall disables sibcall patterns.  */
 /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
 /* { dg-options "-O2 -foptimize-sibling-calls" } */
Index: gcc/testsuite/gcc.dg/sibcall-4.c
===================================================================
--- gcc/testsuite/gcc.dg/sibcall-4.c	(revision 127048)
+++ gcc/testsuite/gcc.dg/sibcall-4.c	(working copy)
@@ -5,7 +5,7 @@
    Copyright (C) 2002 Free Software Foundation Inc.
    Contributed by Hans-Peter Nilsson  <hp@bitrange.com>  */
 
-/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
+/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* ia16-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
 /* -mlongcall disables sibcall patterns.  */
 /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
 /* { dg-options "-O2 -foptimize-sibling-calls" } */

-- 
Rask Ingemann Lambertsen

Re: [PATCH 9/9] Skip or xfail some tests on ia16

[Janis Johnson]

On Mon, 2007-07-30 at 21:55 +0200, Rask Ingemann Lambertsen wrote:
>    This patch disables several tests for features which aren't available on
> ia16. I tested it along with patch 8 in this patch set. Ok for trunk?
> 
> :ADDPATCH testsuite:

:REVIEWMAIL:

This is OK.

Janis

Re: [PATCH 0/9] New back end ia16: 16-bit Intel x86

[Rask Ingemann Lambertsen]

On Mon, Jul 30, 2007 at 03:42:17PM +0200, Rask Ingemann Lambertsen wrote:
 
>    Test results are at
> <URL:http://gcc.gnu.org/ml/gcc-testresults/2007-07/msg01175.html>. I have
> more testsuite patches coming, so the results will improve. The simulator
> setup is also rather crude at the moment and I'll post a folloup to this
> message in the next few days with more details once I tie a few loose ends.

   Download these files:
http://nospamnospam.homepage.dk/gcc/download/newlib.patch
http://nospamnospam.homepage.dk/gcc/download/newlib.tar.gz
http://nospamnospam.homepage.dk/gcc/download/unix.exp

1) Create a combined tree with newlib and libgloss.
2) Apply newlib.patch.
3) Extract newlib.tar.gz.
4) Find binutils for an i386 ELF system somewhere and create links to the
binaries as ia16-unknown-elf-{as,ld,ar,ranlib,strip,nm}.
5) Configure --target=ia16-unknown-elf and build as with any other target.

   There's a quick and dirty simulator for Linux/ia32 systems included. It's
only a wrapper around the vm86() system call and provides none of the fancy
stuff, just arguments and return value. Use unix.exp above when running the
testsuite. Note: It needs to be called unix.exp.

-- 
Rask Ingemann Lambertsen

[PATCH 1/9] New target 16-bit Intel x86

[Andrew Jenner]

To config-patches@gnu.org: You'll receive only this part of the patch set.

2017-04-01  Andrew Jenner  <andrew@codesourcery.com>
	Rask Ingemann Lambertsen  <rask@sygehus.dk>

	* config.sub: Add support for 16-bit Intel x86.

Index: config.sub
===================================================================
--- config.sub	(revision 475331)
+++ config.sub	(revision 475455)
@@ -263,7 +263,7 @@ case $basic_machine in
  	| fido | fr30 | frv | ft32 \
  	| h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \
  	| hexagon \
-	| i370 | i860 | i960 | ia64 \
+	| i370 | i860 | i960 | ia64 | ia16 \
  	| ip2k | iq2000 \
  	| k1om \
  	| le32 | le64 \
@@ -387,7 +387,7 @@ case $basic_machine in
  	| h8300-* | h8500-* \
  	| hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \
  	| hexagon-* \
-	| i*86-* | i860-* | i960-* | ia64-* \
+	| i*86-* | i860-* | i960-* | ia64-* | ia16-* \
  	| ip2k-* | iq2000-* \
  	| k1om-* \
  	| le32-* | le64-* \

Re: [PATCH 1/9] New target 16-bit Intel x86

[Ben Elliston]

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On Sat, Apr 01, 2017 at 05:47:46PM +0100, Andrew Jenner wrote:

> 2017-04-01  Andrew Jenner  <andrew@codesourcery.com>
> 	Rask Ingemann Lambertsen  <rask@sygehus.dk>
> 
> 	* config.sub: Add support for 16-bit Intel x86.

Applied, thanks.

Ben

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