From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7170 invoked by alias); 30 Jul 2007 18:49:50 -0000 Received: (qmail 7094 invoked by uid 22791); 30 Jul 2007 18:49:49 -0000 X-Spam-Check-By: sourceware.org Received: from pfepa.post.tele.dk (HELO pfepa.post.tele.dk) (195.41.46.235) by sourceware.org (qpsmtpd/0.31) with ESMTP; Mon, 30 Jul 2007 18:49:43 +0000 Received: from x1-6-00-0f-9f-c6-3e-90 (x1-6-00-0f-9f-c6-3e-90.k75.webspeed.dk [80.197.1.215]) by pfepa.post.tele.dk (Postfix) with ESMTP id 4A392FAC04D for ; Mon, 30 Jul 2007 20:49:40 +0200 (CEST) Received: from x1-6-00-0f-9f-c6-3e-90 (localhost.localdomain [127.0.0.1]) by x1-6-00-0f-9f-c6-3e-90 (8.14.0/8.14.0) with ESMTP id l6UIndHk015360 for ; Mon, 30 Jul 2007 20:49:39 +0200 Received: (from rask@localhost) by x1-6-00-0f-9f-c6-3e-90 (8.14.0/8.14.0/Submit) id l6UIncDq015359 for gcc-patches@gcc.gnu.org; Mon, 30 Jul 2007 20:49:38 +0200 Date: Mon, 30 Jul 2007 19:08:00 -0000 From: Rask Ingemann Lambertsen To: gcc-patches@gcc.gnu.org Subject: [PATCH 6/9] Documentation for the ia16 back end Message-ID: <20070730184938.GQ25795@sygehus.dk> References: <20070730134217.GK25795@sygehus.dk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20070730134217.GK25795@sygehus.dk> User-Agent: Mutt/1.5.14 (2007-02-12) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2007-07/txt/msg02133.txt.bz2 This patch updates the documentation. I checked with "make info", "make dvi" and by viewing the resulting DVI files that it causes no obvious problems. 2007-07-30 Rask Ingemann Lambertsen * doc/md.texi: Update for new ia16 back end. * doc/invoke.texi: Likewise. * doc/contrib.texi: Likewise. * doc/install.texi: Likewise. Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi (revision 127048) +++ gcc/doc/invoke.texi (working copy) @@ -560,6 +560,9 @@ -mcmodel=@var{code-model} @gol -m32 -m64 -mlarge-data-threshold=@var{num}} +@emph{IA-16 Options} +@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} -mshort-jumps} + @emph{IA-64 Options} @gccoptlist{-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic @gol -mvolatile-asm-stop -mregister-names -mno-sdata @gol @@ -7997,6 +8000,7 @@ * H8/300 Options:: * HPPA Options:: * i386 and x86-64 Options:: +* IA-16 Options:: * IA-64 Options:: * M32C Options:: * M32R/D Options:: @@ -10517,6 +10521,65 @@ about addresses and sizes of sections. @end table +@node IA-16 Options +@subsection IA-16 Options +@cindex IA-16 Options + +These are the @samp{-m} options defined for the Intel IA-16 architecture. + +@table @gcctabopt +@item -mtune=@var{cpu-type} +@opindex mtune +Tune to @var{cpu-type} everything applicable about the generated code, except +for the ABI and the set of available instructions. The choices for +@var{cpu-type} are: +@table @emph +@item i8086 +The Intel 8086. + +@item i8088 +The Intel 8088. + +@item i8086 +The Intel 8086. + +@item i80186 +The Intel 80186. + +@item i80286 +The Intel 80286. + +@item v20 +The NEC V20. + +@item v30 +The NEC V30. + +@item any +Any CPU listed above. The aim is to generate code which runs reasonably +well on any CPU listed above. + +@item any_186 +As with @option{-mtune=any}, but assume a CPU which supports immediate +operands for push, imul and shift/rotate instructions. +@end table + +@item -march=@var{cpu-type} +@opindex march +Generate instructions for the machine type @var{cpu-type}. The choices +for @var{cpu-type} are the same as for @option{-mtune}. Moreover, +specifying @option{-march=@var{cpu-type}} implies @option{-mtune=@var{cpu-type}}. + +@item -mshort-jumps +@itemx -mno-short-jumps +@opindex mshort-jumps +@opindex mno-short-jumps +Allow (or disallow) the use of jump instructions which can only jump +@minus{}128/+127 bytes. The default is not to use them. This option only +affects instructions for which the assembler doesn't provide a work-around +and the compiler doesn't know the jump displacement. +@end table + @node IA-64 Options @subsection IA-64 Options @cindex IA-64 Options Index: gcc/doc/contrib.texi =================================================================== --- gcc/doc/contrib.texi (revision 127048) +++ gcc/doc/contrib.texi (working copy) @@ -476,6 +476,9 @@ 68020 system. @item +Rask Ingemann Lambertsen contributed the 16-bit Intel x86 back end. + +@item Asher Langton and Mike Kumbera for contributing Cray pointer support to GNU Fortran, and for other GNU Fortran improvements. Index: gcc/doc/md.texi =================================================================== --- gcc/doc/md.texi (revision 127048) +++ gcc/doc/md.texi (working copy) @@ -1,5 +1,5 @@ @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001, -@c 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. +@c 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @@ -2083,6 +2083,120 @@ @end table +@item Intel IA-16---@file{config/ia16/constraints.md} +@table @code +@item a +The @code{ax} register. + +@item b +The @code{bx} register. + +@item c +The @code{cx} register. + +@item d +The @code{dx} register. + +@item S +The @code{si} register. + +@item D +The @code{di} register. + +@item Ral +The @code{al} register. + +@item Rah +The @code{ah} register. + +@item Rcl +The @code{cl} register. + +@item Rbp +The @code{bp} register. + +@item q +Any 8-bit register. + +@item T +Any general or segment register. + +@item A +The @code{dx:ax} register pair. + +@item j +The @code{bx:dx} register pair. + +@item l +The lower half of pairs of 8-bit registers. + +@item u +The upper half of pairs of 8-bit registers. + +@item k +Any 32-bit register group with access to the two lower bytes. + +@item x +The @code{si} and @code{di} registers. + +@item w +The @code{bx} and @code{bp} registers. + +@item B +The @code{bx}, @code{si}, @code{di} and @code{bp} registers. + +@item Q +Any segment register. + +@item Z +The constant 0. + +@item P1 +The constant 1. + +@item M1 +The constant @minus{}1. + +@item Um +The constant @minus{}256. + +@item Lbm +The constant 255. + +@item Lor +Constants 128 @dots{} 254. + +@item Lom +Constants 1 @dots{} 254. + +@item Lar +Constants @minus{}255 @dots{} @minus{}129. + +@item Lam +Constants @minus{}255 @dots{} @minus{}2. + +@item Uo +Constants 0xXX00 except @minus{}256. + +@item Ua +Constants 0xXXFF. + +@item Ish +A constant usable as a shift count. + +@item Iaa +A constant multiplier for the @code{aad} instruction. + +@item Ipu +A constant usable with the @code{push} instruction. + +@item Imu +A constant usable with the @code{imul} instruction except 257. + +@item I11 +The constant 257. +@end table + @item Intel IA-64---@file{config/ia64/ia64.h} @table @code @item a Index: gcc/doc/install.texi =================================================================== --- gcc/doc/install.texi (revision 127048) +++ gcc/doc/install.texi (working copy) @@ -2451,6 +2451,8 @@ @item @uref{#ix86-x-udk,,i?86-*-udk} @item +@uref{#ia16-x-elf,,ia16-*-elf} +@item @uref{#ia64-x-linux,,ia64-*-linux} @item @uref{#ia64-x-hpux,,ia64-*-hpux*} @@ -3266,6 +3268,17 @@ @html
@end html +@heading @anchor{ia16-x-elf}ia16-*-elf +Intel 16-bit x86 processor configuration for embedded systems. + +There is no binutils configuration for this target, but binutils +configurations for @samp{i?86} ELF systems can be used. Binutils +releases from around 2001 or later can be used. + + +@html +
+@end html @heading @anchor{ia64-x-linux}ia64-*-linux IA-64 processor (also known as IPF, or Itanium Processor Family) running GNU/Linux. -- Rask Ingemann Lambertsen