From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3362 invoked by alias); 10 Aug 2007 09:40:53 -0000 Received: (qmail 3283 invoked by uid 22791); 10 Aug 2007 09:40:52 -0000 X-Spam-Check-By: sourceware.org Received: from pfepb.post.tele.dk (HELO pfepb.post.tele.dk) (195.41.46.236) by sourceware.org (qpsmtpd/0.31) with ESMTP; Fri, 10 Aug 2007 09:40:50 +0000 Received: from x1-6-00-0f-9f-c6-3e-90 (x1-6-00-0f-9f-c6-3e-90.k75.webspeed.dk [80.197.1.215]) by pfepb.post.tele.dk (Postfix) with ESMTP id 7B9D3A50031 for ; Fri, 10 Aug 2007 11:40:47 +0200 (CEST) Received: from x1-6-00-0f-9f-c6-3e-90 (localhost.localdomain [127.0.0.1]) by x1-6-00-0f-9f-c6-3e-90 (8.14.0/8.14.0) with ESMTP id l7A9elNn024474 for ; Fri, 10 Aug 2007 11:40:47 +0200 Received: (from rask@localhost) by x1-6-00-0f-9f-c6-3e-90 (8.14.0/8.14.0/Submit) id l7A9eltp024473 for gcc-patches@gcc.gnu.org; Fri, 10 Aug 2007 11:40:47 +0200 Date: Fri, 10 Aug 2007 09:40:00 -0000 From: Rask Ingemann Lambertsen To: gcc-patches@gcc.gnu.org Subject: [PATCH] i386: Remove "m" constraint for "register_operand" Message-ID: <20070810094046.GU25795@sygehus.dk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.14 (2007-02-12) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2007-08/txt/msg00654.txt.bz2 There is a mismatch between the constraints permitting memory operands and the predicate accepting only register operands. This patch fixes that. Bootstrapped and tested on x86_64-unknown-linux-gnu with no regressions. Ok for trunk? 2007-08-10 Rask Ingemann Lambertsen * config/i386/i386.md (subsi3_carry_zext): Remove "m" constraint for "register_operand". (*iorsi_1_zext): Likewise. (*iorsi_1_zext_imm): Likewise. * config/i386/sse.md: (*sse4_1_extractps): Likewise. (sse2_vmsqrtv2df2): Likewise. Index: gcc/config/i386/i386.md =================================================================== @@ -6645,11 +6751,11 @@ (set_attr "mode" "SI")]) (define_insn "subsi3_carry_zext" - [(set (match_operand:DI 0 "register_operand" "=rm,r") + [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI - (minus:SI (match_operand:SI 1 "register_operand" "0,0") + (minus:SI (match_operand:SI 1 "register_operand" "0") (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "") - (match_operand:SI 2 "general_operand" "ri,rm"))))) + (match_operand:SI 2 "general_operand" "g"))))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)" "sbb{l}\t{%2, %k0|%k0, %2}" @@ -8661,7 +8767,7 @@ ;; See comment for addsi_1_zext why we do use nonimmediate_operand (define_insn "*iorsi_1_zext" - [(set (match_operand:DI 0 "register_operand" "=rm") + [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") (match_operand:SI 2 "general_operand" "rim")))) @@ -8672,7 +8778,7 @@ (set_attr "mode" "SI")]) (define_insn "*iorsi_1_zext_imm" - [(set (match_operand:DI 0 "register_operand" "=rm") + [(set (match_operand:DI 0 "register_operand" "=r") (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z"))) (clobber (reg:CC FLAGS_REG))] Index: gcc/config/i386/sse.md =================================================================== --- gcc/config/i386/sse.md (revision 127179) +++ gcc/config/i386/sse.md (working copy) @@ -1532,7 +1532,7 @@ }) (define_insn "*sse4_1_extractps" - [(set (match_operand:SF 0 "register_operand" "=rm") + [(set (match_operand:SF 0 "register_operand" "=r") (vec_select:SF (match_operand:V4SF 1 "register_operand" "x") (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")])))] @@ -1694,7 +1694,7 @@ (define_insn "sse2_vmsqrtv2df2" [(set (match_operand:V2DF 0 "register_operand" "=x") (vec_merge:V2DF - (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")) + (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "x")) (match_operand:V2DF 2 "register_operand" "0") (const_int 1)))] "TARGET_SSE2"