Re: [PATCH,SH] Add SH2A new instructions 5/6

Re: [PATCH,SH] Add SH2A new instructions 5/6

[Naveen H.S.]

[-- Attachment #1: Type: text/plain, Size: 1186 bytes --]

Hi,

I sincerely thank you for the valuable suggestions regarding the usage
of 
constraints instead of predicates. We had implemented these instructions

before the constraints.md file was separated from sh.h. So predicates
were 
used to implement these bit instructions.

Please find attached the modified patch "sh2a5.patch" as per the
suggestions.

ChangeLog
2007-10-25	Naveen.H.S naveen.hs@kpitcummins.com
            
	* config/sh/constraints.md : Pso, Psz : New constraints.
	* config/sh/sh.c (print_operand): "V" prints the position of a
single 
	bit set.
	"W" prints the position of a single bit cleared.
	* config/sh/sh.md : andsi3_bclr, iorsi3_bset : New.

Regards,
Naveen.H.S.
KPIT Cummins Infosystems Ltd,
Pune (INDIA) 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	
Free download of GNU based tool-chains for Renesas' SH, H8, R8C, M16C	
and M32C Series. The following site also offers free technical support	
to its users. Visit http://www.kpitgnutools.com for details. 	
Latest versions of KPIT GNU tools were released on October 1, 2007.	
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	


[-- Attachment #2: sh2a5.patch --]
[-- Type: application/octet-stream, Size: 7322 bytes --]

diff -upr gcc-4.3-20070921/gcc/config/sh/constraints.md tars/gcc-4.3-20070921/gcc/config/sh/constraints.md
--- gcc-4.3-20070921/gcc/config/sh/constraints.md	2007-10-24 12:09:31.000000000 +0530
+++ tars/gcc-4.3-20070921/gcc/config/sh/constraints.md	2007-10-24 12:18:12.000000000 +0530
@@ -35,6 +35,8 @@
 ;;  M: 1
 ;;  N: 0
 ;;  P27: 1 | 2 | 8 | 16
+;;  Pso: 1 | 2 | 4 | 8 | 16 | 32 | 64 | 128
+;;  Psz: ~1 | ~2 | ~4 | ~8 | ~16 | ~32 | ~64 | ~128
 ;; Q: pc relative load operand
 ;; Rxx: reserved for exotic register classes.
 ;; Sxx: extra memory (storage) constraints
@@ -204,6 +206,30 @@
    PIC_DIRECT_ADDR_P."
   (match_test "IS_NON_EXPLICIT_CONSTANT_P (op)"))
 
+(define_constraint "Pso"
+  "Integer constant with a single bit set in its lower 8-bit."
+  (and (match_code "const_int")
+       (ior (match_test "ival == 1")
+            (match_test "ival == 2")
+            (match_test "ival == 4")
+            (match_test "ival == 8")
+            (match_test "ival == 16")
+            (match_test "ival == 32")
+            (match_test "ival == 64")
+            (match_test "ival == 128"))))
+
+(define_constraint "Psz"
+  "Integer constant with a single zero bit in the lower 8-bit."
+  (and (match_code "const_int")
+       (ior (match_test "~ival == 1")
+            (match_test "~ival == 2")
+            (match_test "~ival == 4")
+            (match_test "~ival == 8")
+            (match_test "~ival == 16")
+            (match_test "~ival == 32")
+            (match_test "~ival == 64")
+            (match_test "~ival == 128"))))
+
 (define_memory_constraint "Sr0"
   "@internal"
   (and (match_test "memory_operand (op, GET_MODE (op))")
diff -upr gcc-4.3-20070921/gcc/config/sh/sh.c tars/gcc-4.3-20070921/gcc/config/sh/sh.c
--- gcc-4.3-20070921/gcc/config/sh/sh.c	2007-10-24 12:18:00.000000000 +0530
+++ tars/gcc-4.3-20070921/gcc/config/sh/sh.c	2007-10-24 12:18:12.000000000 +0530
@@ -676,6 +676,8 @@ print_operand_address (FILE *stream, rtx
    'd'  print a V2SF reg as dN instead of fpN.
    'm'  print a pair `base,offset' or `base,index', for LD and ST.
    'U'  Likewise for {LD,ST}{HI,LO}.
+   'V'  print the position of a single bit set.
+   'W'  print the position of a single bit cleared.
    'u'  prints the lowest 16 bits of CONST_INT, as an unsigned value.
    'o'  output an operator.  */
 
@@ -883,6 +885,22 @@ print_operand (FILE *stream, rtx x, int 
 	}
       break;
 
+    case 'V':
+      {
+	int num = exact_log2 (INTVAL (x));
+	gcc_assert (num >= 0);
+	fprintf (stream, "#%d", num);
+      }
+      break;
+
+    case 'W':
+      {
+	int num = exact_log2 (~INTVAL (x));
+	gcc_assert (num >= 0);
+	fprintf (stream, "#%d", num);
+      }
+      break;
+
     case 'd':
       gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == V2SFmode);
 
diff -upr gcc-4.3-20070921/gcc/config/sh/sh.md tars/gcc-4.3-20070921/gcc/config/sh/sh.md
--- gcc-4.3-20070921/gcc/config/sh/sh.md	2007-10-24 12:18:00.000000000 +0530
+++ tars/gcc-4.3-20070921/gcc/config/sh/sh.md	2007-10-24 12:18:12.000000000 +0530
@@ -3164,6 +3164,14 @@ label:
 	andi	%1, %2, %0"
   [(set_attr "type" "arith_media")])
 
+(define_insn "*andsi3_bclr"
+  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+        (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
+                (match_operand:SI 2 "const_int_operand" "Psz")))]
+  "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
+  "bclr\\t%W2,%0"
+  [(set_attr "type" "arith")])
+
 ;; If the constant is 255, then emit an extu.b instruction instead of an
 ;; and, since that will give better code.
 
@@ -3246,6 +3254,14 @@ label:
 	ori	%1, %2, %0"
   [(set_attr "type" "arith_media")])
 
+(define_insn "*iorsi3_bset"
+  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+        (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
+                (match_operand:SI 2 "const_int_operand" "Pso")))]
+  "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
+  "bset\\t%V2,%0"
+  [(set_attr "type" "arith")])
+
 (define_insn "iordi3"
   [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
 	(ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
diff -uprN gcc-4.3-20070921/gcc/testsuite/gcc.target/sh/sh2a-bclr.c tars/gcc-4.3-20070921/gcc/testsuite/gcc.target/sh/sh2a-bclr.c
--- gcc-4.3-20070921/gcc/testsuite/gcc.target/sh/sh2a-bclr.c	1970-01-01 05:30:00.000000000 +0530
+++ tars/gcc-4.3-20070921/gcc/testsuite/gcc.target/sh/sh2a-bclr.c	2007-10-24 12:20:01.000000000 +0530
@@ -0,0 +1,63 @@
+/* Testcase to check generation of a SH2A specific instruction
+   "BCLR #imm3,Rn"  */
+
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single
+   -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bclr"} }  */
+
+struct a
+{
+  char a, b;
+  short c;
+};
+
+/* This function generates the instruction "BCLR #imm3,Rn" only
+   on using optimization option "-O1" and above  */
+
+int
+a2 ()
+{
+  volatile int j;
+  volatile static struct a x = { 1, 66, ~1 }, y =
+  {
+  1, 2, ~2};
+
+  if (j > 1)
+    return (x.a == y.a && (x.b & ~1) == y.b);
+  if (j > 2)
+    return (x.a == y.a && (x.b & ~2) == y.b);
+  if (j > 3)
+    return (x.a == y.a && (x.b & ~4) == y.b);
+  if (j > 4)
+    return (x.a == y.a && (x.b & ~8) == y.b);
+  if (j > 5)
+    return (x.a == y.a && (x.b & ~16) == y.b);
+  if (j > 6)
+    return (x.a == y.a && (x.b & ~32) == y.b);
+  if (j > 7)
+    return (x.a == y.a && (x.b & ~64) == y.b);
+  if (j > 8)
+    return (x.a == y.a && (x.b & ~128) == y.b);
+}
+
+int
+main ()
+{
+  volatile unsigned char x;
+
+  x &= 0xFE;
+  x &= 0xFD;
+  x &= 0xFB;
+  x &= 0xF7;
+  x &= 0xEF;
+  x &= 0xDF;
+  x &= 0xBF;
+  x &= 0x7F;
+
+  if (!a2 ())
+  return 0;
+}
+
+
diff -uprN gcc-4.3-20070921/gcc/testsuite/gcc.target/sh/sh2a-bset.c tars/gcc-4.3-20070921/gcc/testsuite/gcc.target/sh/sh2a-bset.c
--- gcc-4.3-20070921/gcc/testsuite/gcc.target/sh/sh2a-bset.c	1970-01-01 05:30:00.000000000 +0530
+++ tars/gcc-4.3-20070921/gcc/testsuite/gcc.target/sh/sh2a-bset.c	2007-10-24 12:20:50.000000000 +0530
@@ -0,0 +1,62 @@
+/* Testcase to check generation of a SH2A specific instruction
+  "BSET #imm3,Rn"  */
+
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single
+   -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bclr"} }  */
+
+struct a
+{
+  char a, b;
+  short c;
+};
+
+/* This function generates the instruction "BSET #imm3,Rn" only
+   on using optimization option "-O1" and above  */
+
+int
+a2 ()
+{
+  volatile int j;
+  volatile static struct a x = { 1, 66, ~1 }, y =
+  {
+  1, 2, ~2};
+
+  if (j > 1)
+    return (x.a == y.a && (x.b | 1) == y.b);
+  if (j > 2)
+    return (x.a == y.a && (x.b | 2) == y.b);
+  if (j > 3)
+    return (x.a == y.a && (x.b | 4) == y.b);
+  if (j > 4)
+    return (x.a == y.a && (x.b | 8) == y.b);
+  if (j > 5)
+    return (x.a == y.a && (x.b | 16) == y.b);
+  if (j > 6)
+    return (x.a == y.a && (x.b | 32) == y.b);
+  if (j > 7)
+    return (x.a == y.a && (x.b | 64) == y.b);
+  if (j > 8)
+    return (x.a == y.a && (x.b | 128) == y.b);
+}
+
+int
+main ()
+{
+  volatile unsigned char x;
+
+  x |= 0x1;
+  x |= 0x2;
+  x |= 0x4;
+  x |= 0x8;
+  x |= 0x16;
+  x |= 0x32;
+  x |= 0x64;
+  x |= 0x128;
+
+  if (!a2 ())
+  return 0;
+}
+

Re: [PATCH,SH] Add SH2A new instructions 5/6

[Kaz Kojima]

"Naveen H.S." <naveen.hs@kpitcummins.com> wrote:
> Please find attached the modified patch "sh2a5.patch" as per the
> suggestions.

Looks fine, except for a few problems about coding standard.
Re-post the revised patch when the trunk returns to stage1.
Don't forget to describe how the patch is tested then.

> --- gcc-4.3-20070921/gcc/config/sh/constraints.md	2007-10-24 12:09:31.000000000 +0530
> +++ tars/gcc-4.3-20070921/gcc/config/sh/constraints.md	2007-10-24 12:18:12.000000000 +0530
[snip]
> @@ -204,6 +206,30 @@
>     PIC_DIRECT_ADDR_P."
>    (match_test "IS_NON_EXPLICIT_CONSTANT_P (op)"))
>  
> +(define_constraint "Pso"
> +  "Integer constant with a single bit set in its lower 8-bit."
> +  (and (match_code "const_int")
> +       (ior (match_test "ival == 1")
> +            (match_test "ival == 2")
> +            (match_test "ival == 4")
> +            (match_test "ival == 8")
> +            (match_test "ival == 16")
> +            (match_test "ival == 32")
> +            (match_test "ival == 64")
> +            (match_test "ival == 128"))))
> +
> +(define_constraint "Psz"
> +  "Integer constant with a single zero bit in the lower 8-bit."
> +  (and (match_code "const_int")
> +       (ior (match_test "~ival == 1")
> +            (match_test "~ival == 2")
> +            (match_test "~ival == 4")
> +            (match_test "~ival == 8")
> +            (match_test "~ival == 16")
> +            (match_test "~ival == 32")
> +            (match_test "~ival == 64")
> +            (match_test "~ival == 128"))))
    ^^^^^^^^
Use tabs instead of 8 spaces.

> --- gcc-4.3-20070921/gcc/config/sh/sh.md	2007-10-24 12:18:00.000000000 +0530
> +++ tars/gcc-4.3-20070921/gcc/config/sh/sh.md	2007-10-24 12:18:12.000000000 +0530
> @@ -3164,6 +3164,14 @@ label:
>  	andi	%1, %2, %0"
>    [(set_attr "type" "arith_media")])
>  
> +(define_insn "*andsi3_bclr"
> +  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
> +        (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
> +                (match_operand:SI 2 "const_int_operand" "Psz")))]
    ^^^^^^^^
Same here

> @@ -3246,6 +3254,14 @@ label:
>  	ori	%1, %2, %0"
>    [(set_attr "type" "arith_media")])
>  
> +(define_insn "*iorsi3_bset"
> +  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
> +        (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
> +                (match_operand:SI 2 "const_int_operand" "Pso")))]
    ^^^^^^^^
and here.

> --- gcc-4.3-20070921/gcc/testsuite/gcc.target/sh/sh2a-bclr.c	1970-01-01 05:30:00.000000000 +0530
> +++ tars/gcc-4.3-20070921/gcc/testsuite/gcc.target/sh/sh2a-bclr.c	2007-10-24 12:20:01.000000000 +0530
> @@ -0,0 +1,63 @@
> +/* Testcase to check generation of a SH2A specific instruction
> +   "BCLR #imm3,Rn"  */

Missing period.

> +/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single
> +   -m2a-single-only" }  */

A single line would be safer.

> +  volatile static struct a x = { 1, 66, ~1 }, y =
> +  {
> +  1, 2, ~2};

Wrong indentation.  Simply

  volatile static struct a x = { 1, 66, ~1 }, y = { 1, 2, ~2};

would be Ok.

> --- gcc-4.3-20070921/gcc/testsuite/gcc.target/sh/sh2a-bset.c	1970-01-01 05:30:00.000000000 +0530
> +++ tars/gcc-4.3-20070921/gcc/testsuite/gcc.target/sh/sh2a-bset.c	2007-10-24 12:20:50.000000000 +0530
> @@ -0,0 +1,62 @@
> +/* Testcase to check generation of a SH2A specific instruction
> +  "BSET #imm3,Rn"  */
[snip]
> +  volatile static struct a x = { 1, 66, ~1 }, y =
> +  {
> +  1, 2, ~2};

Same here.

> 2007-10-25	Naveen.H.S naveen.hs@kpitcummins.com
>             
> 	* config/sh/constraints.md : Pso, Psz : New constraints.
> 	* config/sh/sh.c (print_operand): "V" prints the position of a
> single 
> 	bit set.
> 	"W" prints the position of a single bit cleared.
> 	* config/sh/sh.md : andsi3_bclr, iorsi3_bset : New.

The style of this entry is wrong.  Should be

200z-xx-yy  Naveen.H.S  <naveen.hs@kpitcummins.com>
            
	* config/sh/constraints.md (Pso, Psz): New constraints.
	* config/sh/sh.c (print_operand): Add %V and %W operand codes.
	* config/sh/sh.md (*andsi3_bclr, *iorsi3_bset): New insns.

Also new testcases require an entry in gcc/testsuite/ChangeLog:

200z-xx-yy  Naveen.H.S  <naveen.hs@kpitcummins.com>

	* gcc.target/sh/sh2a-bclr.c: New test.
	* gcc.target/sh/sh2a-bset.c: New test.

Regards,
	kaz

RE: [PATCH,SH] Add SH2A new instructions 5/6

[Naveen H.S.]

[-- Attachment #1: Type: text/plain, Size: 1037 bytes --]

Hi Kaz,

>> It seems that there is a typo in that test. 

Thanks for pointing out the mistake. It has been rectified.
Please find the revised patch attached "sh2a5.patch" as per the
suggestions.

2008-03-24  Naveen.H.S  <naveen.hs@kpitcummins.com>
            
	* config/sh/constraints.md (Pso, Psz): New constraints.
	* config/sh/sh.c (print_operand): Add %V and %W operand codes.
	* config/sh/sh.md (*andsi3_bclr, *iorsi3_bset): New insns.
	
	* gcc.target/sh/sh2a-bclr.c: New test.
	* gcc.target/sh/sh2a-bset.c: New test.

Regards,
Naveen.H.S.
KPIT Cummins Infosystems Ltd,
Pune (INDIA) 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	
Free download of GNU based tool-chains for Renesas' SH, H8, R8C, M16C	
and M32C Series. The following site also offers free technical support	
to its users. Visit http://www.kpitgnutools.com for details. 	
Latest versions of KPIT GNU tools were released on February 4, 2008.	
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	

[-- Attachment #2: sh2a5.patch --]
[-- Type: application/octet-stream, Size: 9840 bytes --]

diff -upr /home/naveenh/tars/gcc-4.4-20080222/gcc/config/sh/constraints.md m32c/src/gcc-4.4-20080222/gcc/config/sh/constraints.md
--- /home/naveenh/tars/gcc-4.4-20080222/gcc/config/sh/constraints.md	2008-03-24 12:53:02.000000000 +0530
+++ m32c/src/gcc-4.4-20080222/gcc/config/sh/constraints.md	2008-03-20 09:59:58.000000000 +0530
@@ -35,6 +35,8 @@
 ;;  M: 1
 ;;  N: 0
 ;;  P27: 1 | 2 | 8 | 16
+;;  Pso: 1 | 2 | 4 | 8 | 16 | 32 | 64 | 128
+;;  Psz: ~1 | ~2 | ~4 | ~8 | ~16 | ~32 | ~64 | ~128
 ;; Q: pc relative load operand
 ;; Rxx: reserved for exotic register classes.
 ;; Sxx: extra memory (storage) constraints
@@ -204,6 +206,30 @@
    PIC_DIRECT_ADDR_P."
   (match_test "IS_NON_EXPLICIT_CONSTANT_P (op)"))
 
+(define_constraint "Pso"
+  "Integer constant with a single bit set in its lower 8-bit."
+  (and (match_code "const_int")
+       (ior (match_test "ival == 1")
+	    (match_test "ival == 2")
+	    (match_test "ival == 4")
+	    (match_test "ival == 8")
+	    (match_test "ival == 16")
+	    (match_test "ival == 32")
+	    (match_test "ival == 64")
+	    (match_test "ival == 128"))))
+
+(define_constraint "Psz"
+  "Integer constant with a single zero bit in the lower 8-bit."
+  (and (match_code "const_int")
+       (ior (match_test "~ival == 1")
+	    (match_test "~ival == 2")
+	    (match_test "~ival == 4")
+	    (match_test "~ival == 8")
+	    (match_test "~ival == 16")
+	    (match_test "~ival == 32")
+	    (match_test "~ival == 64")
+	    (match_test "~ival == 128"))))
+
 (define_memory_constraint "Sr0"
   "@internal"
   (and (match_test "memory_operand (op, GET_MODE (op))")
Only in m32c/src/gcc-4.4-20080222/gcc/config/sh/: constraints.md.orig
Only in m32c/src/gcc-4.4-20080222/gcc/config/sh/: predicates.md.orig
diff -upr /home/naveenh/tars/gcc-4.4-20080222/gcc/config/sh/sh.c m32c/src/gcc-4.4-20080222/gcc/config/sh/sh.c
--- /home/naveenh/tars/gcc-4.4-20080222/gcc/config/sh/sh.c	2008-03-24 12:55:24.000000000 +0530
+++ m32c/src/gcc-4.4-20080222/gcc/config/sh/sh.c	2008-03-20 09:59:59.000000000 +0530
@@ -678,6 +678,8 @@ print_operand_address (FILE *stream, rtx
    'd'  print a V2SF reg as dN instead of fpN.
    'm'  print a pair `base,offset' or `base,index', for LD and ST.
    'U'  Likewise for {LD,ST}{HI,LO}.
+   'V'  print the position of a single bit set.
+   'W'  print the position of a single bit cleared.
    'u'  prints the lowest 16 bits of CONST_INT, as an unsigned value.
    'o'  output an operator.  */
 
@@ -884,6 +886,22 @@ print_operand (FILE *stream, rtx x, int 
 	}
       break;
 
+    case 'V':
+      {
+	int num = exact_log2 (INTVAL (x));
+	gcc_assert (num >= 0);
+	fprintf (stream, "#%d", num);
+      }
+      break;
+
+    case 'W':
+      {
+	int num = exact_log2 (~INTVAL (x));
+	gcc_assert (num >= 0);
+	fprintf (stream, "#%d", num);
+      }
+      break;
+
     case 'd':
       gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == V2SFmode);
 
diff -upr /home/naveenh/tars/gcc-4.4-20080222/gcc/config/sh/sh.c.orig m32c/src/gcc-4.4-20080222/gcc/config/sh/sh.c.orig
--- /home/naveenh/tars/gcc-4.4-20080222/gcc/config/sh/sh.c.orig	2008-03-24 12:53:02.000000000 +0530
+++ m32c/src/gcc-4.4-20080222/gcc/config/sh/sh.c.orig	2008-03-19 14:35:55.000000000 +0530
@@ -678,6 +678,11 @@ print_operand_address (FILE *stream, rtx
    'd'  print a V2SF reg as dN instead of fpN.
    'm'  print a pair `base,offset' or `base,index', for LD and ST.
    'U'  Likewise for {LD,ST}{HI,LO}.
+   'V'  print the position of a single bit set.
+   'W'  print the position of a single bit cleared.
+   'f'  output the bit operator.
+   'e'  output the bitnot operator.
+   't'  print a memory address which is a register.
    'u'  prints the lowest 16 bits of CONST_INT, as an unsigned value.
    'o'  output an operator.  */
 
@@ -817,6 +822,21 @@ print_operand (FILE *stream, rtx x, int 
 	  break;
 	}
       break;
+
+    case 't':
+      gcc_assert (GET_CODE (x) == MEM);
+      x = XEXP (x, 0);
+      switch (GET_CODE (x))
+	{
+	case REG:
+	case SUBREG:
+	  print_operand (stream, x, 0);
+	  break;
+	default:
+	  break;
+	}
+      break;
+
     case 'o':
       switch (GET_CODE (x))
 	{
@@ -884,6 +904,22 @@ print_operand (FILE *stream, rtx x, int 
 	}
       break;
 
+    case 'V':
+      {
+	int num = exact_log2 (INTVAL (x));
+	gcc_assert (num >= 0);
+	fprintf (stream, "#%d", num);
+      }
+      break;
+
+    case 'W':
+      {
+	int num = exact_log2 (~INTVAL (x));
+	gcc_assert (num >= 0);
+	fprintf (stream, "#%d", num);
+      }
+      break;
+
     case 'd':
       gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == V2SFmode);
 
@@ -10591,6 +10627,9 @@ sh_expand_t_scc (enum rtx_code code, rtx
   val = INTVAL (sh_compare_op1);
   if ((code == EQ && val == 1) || (code == NE && val == 0))
     emit_insn (gen_movt (result));
+  else if (TARGET_SH2A && ((code == EQ && val == 0)
+			    || (code == NE && val == 1)))
+    emit_insn (gen_movrt (result));
   else if ((code == EQ && val == 0) || (code == NE && val == 1))
     {
       emit_insn (gen_rtx_CLOBBER (VOIDmode, result));
Only in m32c/src/gcc-4.4-20080222/gcc/config/sh/: sh.h.orig
diff -upr /home/naveenh/tars/gcc-4.4-20080222/gcc/config/sh/sh.md m32c/src/gcc-4.4-20080222/gcc/config/sh/sh.md
--- /home/naveenh/tars/gcc-4.4-20080222/gcc/config/sh/sh.md	2008-03-24 12:55:24.000000000 +0530
+++ m32c/src/gcc-4.4-20080222/gcc/config/sh/sh.md	2008-03-20 10:00:00.000000000 +0530
@@ -3170,6 +3170,14 @@ label:
 	andi	%1, %2, %0"
   [(set_attr "type" "arith_media")])
 
+(define_insn "*andsi3_bclr"
+  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+	(and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
+		(match_operand:SI 2 "const_int_operand" "Psz")))]
+  "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
+  "bclr\\t%W2,%0"
+  [(set_attr "type" "arith")])
+
 ;; If the constant is 255, then emit an extu.b instruction instead of an
 ;; and, since that will give better code.
 
@@ -3252,6 +3260,14 @@ label:
 	ori	%1, %2, %0"
   [(set_attr "type" "arith_media")])
 
+(define_insn "*iorsi3_bset"
+  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+	(ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
+	(match_operand:SI 2 "const_int_operand" "Pso")))]
+  "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
+  "bset\\t%V2,%0"
+  [(set_attr "type" "arith")])
+
 (define_insn "iordi3"
   [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
 	(ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
Only in m32c/src/gcc-4.4-20080222/gcc/config/sh/: sh.md.orig
Only in m32c/src/gcc-4.4-20080222/gcc/config/sh/: sh.opt.orig
diff -uprN /home/naveenh/tars/gcc-4.4-20080222/gcc/testsuite/gcc.target/sh/sh2a-bclr.c m32c/src/gcc-4.4-20080222/gcc/testsuite/gcc.target/sh/sh2a-bclr.c
--- /home/naveenh/tars/gcc-4.4-20080222/gcc/testsuite/gcc.target/sh/sh2a-bclr.c	1970-01-01 05:30:00.000000000 +0530
+++ m32c/src/gcc-4.4-20080222/gcc/testsuite/gcc.target/sh/sh2a-bclr.c	2008-03-19 14:35:52.000000000 +0530
@@ -0,0 +1,59 @@
+/* Testcase to check generation of a SH2A specific instruction
+   'BCLR #imm3,Rn'.  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bclr"} }  */
+
+struct a
+{
+  char a, b;
+  short c;
+};
+
+/* This function generates the instruction "BCLR #imm3,Rn" only
+   on using optimization option "-O1" and above.  */
+
+int
+a2 ()
+{
+  volatile int j;
+  volatile static struct a x = {1, 66, ~1}, y = {1, 2, ~2};
+
+  if (j > 1)
+    return (x.a == y.a && (x.b & ~1) == y.b);
+  if (j > 2)
+    return (x.a == y.a && (x.b & ~2) == y.b);
+  if (j > 3)
+    return (x.a == y.a && (x.b & ~4) == y.b);
+  if (j > 4)
+    return (x.a == y.a && (x.b & ~8) == y.b);
+  if (j > 5)
+    return (x.a == y.a && (x.b & ~16) == y.b);
+  if (j > 6)
+    return (x.a == y.a && (x.b & ~32) == y.b);
+  if (j > 7)
+    return (x.a == y.a && (x.b & ~64) == y.b);
+  if (j > 8)
+    return (x.a == y.a && (x.b & ~128) == y.b);
+}
+
+int
+main ()
+{
+  volatile unsigned char x;
+
+  x &= 0xFE;
+  x &= 0xFD;
+  x &= 0xFB;
+  x &= 0xF7;
+  x &= 0xEF;
+  x &= 0xDF;
+  x &= 0xBF;
+  x &= 0x7F;
+
+  if (!a2 ())
+  return 0;
+}
+
+
diff -uprN /home/naveenh/tars/gcc-4.4-20080222/gcc/testsuite/gcc.target/sh/sh2a-bset.c m32c/src/gcc-4.4-20080222/gcc/testsuite/gcc.target/sh/sh2a-bset.c
--- /home/naveenh/tars/gcc-4.4-20080222/gcc/testsuite/gcc.target/sh/sh2a-bset.c	1970-01-01 05:30:00.000000000 +0530
+++ m32c/src/gcc-4.4-20080222/gcc/testsuite/gcc.target/sh/sh2a-bset.c	2008-03-20 09:58:30.000000000 +0530
@@ -0,0 +1,58 @@
+/* Testcase to check generation of a SH2A specific instruction
+  'BSET #imm3,Rn'.  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bset"} }  */
+
+struct a
+{
+  char a, b;
+  short c;
+};
+
+/* This function generates the instruction "BSET #imm3,Rn" only
+   on using optimization option "-O1" and above.  */
+
+int
+a2 ()
+{
+  volatile int j;
+  volatile static struct a x = {1, 66, ~1}, y = {1, 2, ~2};
+
+  if (j > 1)
+    return (x.a == y.a && (x.b | 1) == y.b);
+  if (j > 2)
+    return (x.a == y.a && (x.b | 2) == y.b);
+  if (j > 3)
+    return (x.a == y.a && (x.b | 4) == y.b);
+  if (j > 4)
+    return (x.a == y.a && (x.b | 8) == y.b);
+  if (j > 5)
+    return (x.a == y.a && (x.b | 16) == y.b);
+  if (j > 6)
+    return (x.a == y.a && (x.b | 32) == y.b);
+  if (j > 7)
+    return (x.a == y.a && (x.b | 64) == y.b);
+  if (j > 8)
+    return (x.a == y.a && (x.b | 128) == y.b);
+}
+
+int
+main ()
+{
+  volatile unsigned char x;
+
+  x |= 0x1;
+  x |= 0x2;
+  x |= 0x4;
+  x |= 0x8;
+  x |= 0x16;
+  x |= 0x32;
+  x |= 0x64;
+  x |= 0x128;
+
+  if (!a2 ())
+  return 0;
+}
+

Re: [PATCH,SH] Add SH2A new instructions 5/6

[Kaz Kojima]

"Naveen H.S." <naveen.hs@kpitcummins.com> wrote:
> 	* gcc.target/sh/sh2a-bclr.c: New test.
> 	* gcc.target/sh/sh2a-bset.c: New test.

I've got a failure

FAIL: gcc.target/sh/sh2a-bset.c scan-assembler bclr

for the new sh2a-bset.c test with -m2a.  It seems that
there is a typo in that test.  Perhaps

@@ -3,7 +3,7 @@
 /* { dg-do assemble {target sh*-*-*}}  */
 /* { dg-options "-O1" }  */
 /* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
-/* { dg-final { scan-assembler "bclr"} }  */
+/* { dg-final { scan-assembler "bset"} }  */
 
 struct a
 {

Regards,
	kaz

[PATCH,SH] Add SH2A new instructions 5/6

[Naveen H.S.]

[-- Attachment #1: Type: text/plain, Size: 1178 bytes --]

Hi Kaz,

>> Re-post the revised patch when the trunk returns to stage1.

Please find the revised patch attached "sh2a5.patch" as per the
suggestions. Thanks a lot for the valuable guidance.

>> Don't forget to describe how the patch is tested then.

The patch was tested using the C and C++ testsuite for all the SH2A
combinations.

2008-03-19  Naveen.H.S  <naveen.hs@kpitcummins.com>
            
	* config/sh/constraints.md (Pso, Psz): New constraints.
	* config/sh/sh.c (print_operand): Add %V and %W operand codes.
	* config/sh/sh.md (*andsi3_bclr, *iorsi3_bset): New insns.
	
	* gcc.target/sh/sh2a-bclr.c: New test.
	* gcc.target/sh/sh2a-bset.c: New test.

Regards,
Naveen.H.S.
KPIT Cummins Infosystems Ltd,
Pune (INDIA) 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	
Free download of GNU based tool-chains for Renesas' SH, H8, R8C, M16C	
and M32C Series. The following site also offers free technical support	
to its users. Visit http://www.kpitgnutools.com for details. 	
Latest versions of KPIT GNU tools were released on February 4, 2008.	
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	

[-- Attachment #2: sh2a5.patch --]
[-- Type: application/octet-stream, Size: 6431 bytes --]


--- /gcc/config/sh/constraints.md	2008-03-18 10:34:57.000000000 +0530
+++ /gcc/config/sh/constraints.md	2008-03-18 10:38:36.000000000 +0530
@@ -35,6 +35,8 @@
 ;;  M: 1
 ;;  N: 0
 ;;  P27: 1 | 2 | 8 | 16
+;;  Pso: 1 | 2 | 4 | 8 | 16 | 32 | 64 | 128
+;;  Psz: ~1 | ~2 | ~4 | ~8 | ~16 | ~32 | ~64 | ~128
 ;; Q: pc relative load operand
 ;; Rxx: reserved for exotic register classes.
 ;; Sxx: extra memory (storage) constraints
@@ -204,6 +206,30 @@
    PIC_DIRECT_ADDR_P."
   (match_test "IS_NON_EXPLICIT_CONSTANT_P (op)"))
 
+(define_constraint "Pso"
+  "Integer constant with a single bit set in its lower 8-bit."
+  (and (match_code "const_int")
+       (ior (match_test "ival == 1")
+	    (match_test "ival == 2")
+	    (match_test "ival == 4")
+	    (match_test "ival == 8")
+	    (match_test "ival == 16")
+	    (match_test "ival == 32")
+	    (match_test "ival == 64")
+	    (match_test "ival == 128"))))
+
+(define_constraint "Psz"
+  "Integer constant with a single zero bit in the lower 8-bit."
+  (and (match_code "const_int")
+       (ior (match_test "~ival == 1")
+	    (match_test "~ival == 2")
+	    (match_test "~ival == 4")
+	    (match_test "~ival == 8")
+	    (match_test "~ival == 16")
+	    (match_test "~ival == 32")
+	    (match_test "~ival == 64")
+	    (match_test "~ival == 128"))))
+
 (define_memory_constraint "Sr0"
   "@internal"
   (and (match_test "memory_operand (op, GET_MODE (op))")

--- /gcc/config/sh/sh.c	2008-03-18 10:39:08.000000000 +0530
+++ /gcc/config/sh/sh.c	2008-03-18 10:38:36.000000000 +0530
@@ -678,6 +678,8 @@ print_operand_address (FILE *stream, rtx
    'd'  print a V2SF reg as dN instead of fpN.
    'm'  print a pair `base,offset' or `base,index', for LD and ST.
    'U'  Likewise for {LD,ST}{HI,LO}.
+   'V'  print the position of a single bit set.
+   'W'  print the position of a single bit cleared.
    'u'  prints the lowest 16 bits of CONST_INT, as an unsigned value.
    'o'  output an operator.  */
 
@@ -884,6 +886,22 @@ print_operand (FILE *stream, rtx x, int 
 	}
       break;
 
+    case 'V':
+      {
+	int num = exact_log2 (INTVAL (x));
+	gcc_assert (num >= 0);
+	fprintf (stream, "#%d", num);
+      }
+      break;
+
+    case 'W':
+      {
+	int num = exact_log2 (~INTVAL (x));
+	gcc_assert (num >= 0);
+	fprintf (stream, "#%d", num);
+      }
+      break;
+
     case 'd':
       gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == V2SFmode);
 
--- /gcc/config/sh/sh.md	2008-03-18 10:39:08.000000000 +0530
+++ /gcc/config/sh/sh.md	2008-03-18 10:38:36.000000000 +0530
@@ -3170,6 +3170,14 @@ label:
 	andi	%1, %2, %0"
   [(set_attr "type" "arith_media")])
 
+(define_insn "*andsi3_bclr"
+  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+	(and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
+		(match_operand:SI 2 "const_int_operand" "Psz")))]
+  "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
+  "bclr\\t%W2,%0"
+  [(set_attr "type" "arith")])
+
 ;; If the constant is 255, then emit an extu.b instruction instead of an
 ;; and, since that will give better code.
 
@@ -3252,6 +3260,14 @@ label:
 	ori	%1, %2, %0"
   [(set_attr "type" "arith_media")])
 
+(define_insn "*iorsi3_bset"
+  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+	(ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
+	(match_operand:SI 2 "const_int_operand" "Pso")))]
+  "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
+  "bset\\t%V2,%0"
+  [(set_attr "type" "arith")])
+
 (define_insn "iordi3"
   [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
 	(ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")

--- /gcc/testsuite/gcc.target/sh/sh2a-bclr.c	1970-01-01 05:30:00.000000000 +0530
+++ /gcc/testsuite/gcc.target/sh/sh2a-bclr.c	2008-03-18 10:40:50.000000000 +0530
@@ -0,0 +1,59 @@
+/* Testcase to check generation of a SH2A specific instruction
+   'BCLR #imm3,Rn'.  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bclr"} }  */
+
+struct a
+{
+  char a, b;
+  short c;
+};
+
+/* This function generates the instruction "BCLR #imm3,Rn" only
+   on using optimization option "-O1" and above.  */
+
+int
+a2 ()
+{
+  volatile int j;
+  volatile static struct a x = {1, 66, ~1}, y = {1, 2, ~2};
+
+  if (j > 1)
+    return (x.a == y.a && (x.b & ~1) == y.b);
+  if (j > 2)
+    return (x.a == y.a && (x.b & ~2) == y.b);
+  if (j > 3)
+    return (x.a == y.a && (x.b & ~4) == y.b);
+  if (j > 4)
+    return (x.a == y.a && (x.b & ~8) == y.b);
+  if (j > 5)
+    return (x.a == y.a && (x.b & ~16) == y.b);
+  if (j > 6)
+    return (x.a == y.a && (x.b & ~32) == y.b);
+  if (j > 7)
+    return (x.a == y.a && (x.b & ~64) == y.b);
+  if (j > 8)
+    return (x.a == y.a && (x.b & ~128) == y.b);
+}
+
+int
+main ()
+{
+  volatile unsigned char x;
+
+  x &= 0xFE;
+  x &= 0xFD;
+  x &= 0xFB;
+  x &= 0xF7;
+  x &= 0xEF;
+  x &= 0xDF;
+  x &= 0xBF;
+  x &= 0x7F;
+
+  if (!a2 ())
+  return 0;
+}
+
+

--- /gcc/testsuite/gcc.target/sh/sh2a-bset.c	1970-01-01 05:30:00.000000000 +0530
+++ /gcc/testsuite/gcc.target/sh/sh2a-bset.c	2008-03-18 10:41:41.000000000 +0530
@@ -0,0 +1,58 @@
+/* Testcase to check generation of a SH2A specific instruction
+  'BSET #imm3,Rn'.  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bclr"} }  */
+
+struct a
+{
+  char a, b;
+  short c;
+};
+
+/* This function generates the instruction "BSET #imm3,Rn" only
+   on using optimization option "-O1" and above.  */
+
+int
+a2 ()
+{
+  volatile int j;
+  volatile static struct a x = {1, 66, ~1}, y = {1, 2, ~2};
+
+  if (j > 1)
+    return (x.a == y.a && (x.b | 1) == y.b);
+  if (j > 2)
+    return (x.a == y.a && (x.b | 2) == y.b);
+  if (j > 3)
+    return (x.a == y.a && (x.b | 4) == y.b);
+  if (j > 4)
+    return (x.a == y.a && (x.b | 8) == y.b);
+  if (j > 5)
+    return (x.a == y.a && (x.b | 16) == y.b);
+  if (j > 6)
+    return (x.a == y.a && (x.b | 32) == y.b);
+  if (j > 7)
+    return (x.a == y.a && (x.b | 64) == y.b);
+  if (j > 8)
+    return (x.a == y.a && (x.b | 128) == y.b);
+}
+
+int
+main ()
+{
+  volatile unsigned char x;
+
+  x |= 0x1;
+  x |= 0x2;
+  x |= 0x4;
+  x |= 0x8;
+  x |= 0x16;
+  x |= 0x32;
+  x |= 0x64;
+  x |= 0x128;
+
+  if (!a2 ())
+  return 0;
+}
+