Re: [PATCH] Fix for PR 37809 and 37807

[Ralph Loader <suckfish@ihug.co.nz>]

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[Sorry for the delay on following up on this]

> The rtlanal.c parts are ok.  I wonder if we ever hit the _or_truncate
> case with vector modes in force_to_mode though - can you check if
> using gen_lowpart instead of gen_lowpart_or_truncate works?

I checked this and gen_lowpart instead of gen_lowpart_or_truncate
appears fine.

Attached is patch modified to use gen_lowpart, and with the test case
cleaned up & changeloged.

Cheers,
Ralph.


> 
> Btw, you missa ChangeLog entry for the testcase for
> testsuite/ChangeLog.
> 
> Thanks,
> Richard.
> 
> > 2008-10-19  Ralph Loader  <suckfish@ihug.co.nz>
> >
> >        PR middle-end/37807, middle-end/37809
> >        * combine.c (force_to_mode): Do not process vector types.
> >
> >        * rtlanal.c (nonzero_bits1): Do not process vector types.
> >        (num_sign_bit_copies1): Likewise.
> >
> > Cheers,
> > Ralph.
> >

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diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 44bb0e5..2dfcce0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2008-11-02  Ralph Loader  <suckfish@ihug.co.nz>
+
+	PR middle-end/37807, middle-end/37809
+	* combine.c (force_to_mode): Do not process vector types.
+
+	* rtlanal.c (nonzero_bits1): Do not process vector types.
+	(num_sign_bit_copies1): Likewise.
+
 2008-10-25  Richard Sandiford  <rdsandiford@googlemail.com>
 
 	* config/mips/mips.h (REG_ALLOC_ORDER): Put call-clobbered registers
diff --git a/gcc/combine.c b/gcc/combine.c
index 55baf37..3fb3cad 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -7321,6 +7321,10 @@ force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
     return gen_lowpart (mode, x);
 
+  /* The arithmetic simplifications here do the wrong thing on vector modes.  */
+  if (VECTOR_MODE_P (mode) || VECTOR_MODE_P (GET_MODE (x)))
+      return gen_lowpart (mode, x);
+
   switch (code)
     {
     case CLOBBER:
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index b2038aa..5d9df2c 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -3681,8 +3681,9 @@ nonzero_bits1 (const_rtx x, enum machine_mode mode, const_rtx known_x,
   enum rtx_code code;
   unsigned int mode_width = GET_MODE_BITSIZE (mode);
 
-  /* For floating-point values, assume all bits are needed.  */
-  if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
+  /* For floating-point and vector values, assume all bits are needed.  */
+  if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode)
+      || VECTOR_MODE_P (GET_MODE (x)) || VECTOR_MODE_P (mode))
     return nonzero;
 
   /* If X is wider than MODE, use its mode instead.  */
@@ -4195,7 +4196,8 @@ num_sign_bit_copies1 (const_rtx x, enum machine_mode mode, const_rtx known_x,
   if (mode == VOIDmode)
     mode = GET_MODE (x);
 
-  if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
+  if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x))
+      || VECTOR_MODE_P (GET_MODE (x)) || VECTOR_MODE_P (mode))
     return 1;
 
   /* For a smaller object, just ignore the high bits.  */
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 886e542..2f8158b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2008-11-02  Ralph Loader  <suckfish@ihug.co.nz>
+
+	PR middle-end/37807, middle-end/37809
+	* gcc/testsuite/gcc.target/i386/mmx-8.c: New test.
+
 2008-10-24  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
 	PR target/37841
diff --git a/gcc/testsuite/gcc.target/i386/mmx-8.c b/gcc/testsuite/gcc.target/i386/mmx-8.c
new file mode 100644
index 0000000..7556693
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/mmx-8.c
@@ -0,0 +1,133 @@
+/* PR middle-end/37809 */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -mmmx" } */
+
+#include <mmintrin.h>
+
+#include "mmx-check.h"
+
+// Various tests of cases where it is incorrect to optimise vectors as if they
+// were integers of the same width.
+
+extern void abort (void);
+
+
+void Sshift()
+{
+    volatile __m64 y = (__m64) 0xffffffffll;
+    __m64 x = y & (__m64) 0xffffffffll;
+    x = _m_psradi (x, 1);
+    x &= (__m64) 0x80000000ll;
+    if (0 == (long long) x)
+        abort();
+}
+
+#define SHIFTU(F,B,S,T)                         \
+    void F()                                    \
+    {                                           \
+        volatile __m64 y = (__m64) 0ll;         \
+        __m64 x = y | (__m64) (1llu << B);      \
+        if (S > 0)                              \
+            x = _m_pslldi (x, S);               \
+        else                                    \
+            x = _m_psrldi (x, -S);              \
+        if (T > 0)                              \
+            x = _m_pslldi (x, T);               \
+        else                                    \
+            x = _m_psrldi (x, -T);              \
+        x &= (__m64) (1llu << (B + S + T));     \
+        if ((long long) x)                      \
+            abort();                            \
+    }
+
+SHIFTU (shiftU1, 31, 1, -1)
+SHIFTU (shiftU2, 32, -1, 1)
+SHIFTU (shiftU3, 31, 1, 0)
+SHIFTU (shiftU4, 32, -1, 0)
+
+void add()
+{
+    volatile long long ONE = 1;
+    long long one = ONE;
+
+    __m64 a = (__m64) one;
+    __m64 b = (__m64) -one;
+    __m64 c = a + b;
+    if (0 == (long long) c)
+        abort();
+}
+
+void add2()
+{
+    volatile long long ONE = 1;
+    long long one = ONE;
+
+    __m64 a = (__m64) one;
+    __m64 b = (__m64) -one;
+    __m64 c = _m_paddd (a, b);
+    if (0 == (long long) c)
+        abort();
+}
+
+
+void mult1()
+{
+    volatile __m64 y = (__m64) 0ll;
+    __m64 x = y | (__m64) (1ll << 32);
+    x = x * (__m64) 1ll;
+    x &= (__m64) (1ll << 32);
+    if (0 != (long long) x)
+        abort();
+}
+
+
+void mult2()
+{
+    volatile int foo = 1;
+    unsigned long long one = foo & 1;
+
+    __m64 x = (__m64) (one << 16);
+    x *= x;
+    x &= (__m64) (1ll << 32);
+    if (0 != (long long) x)
+        abort();
+}
+
+
+void mult3()
+{
+    volatile __m64 y = (__m64) (1ll << 32);
+    __m64 a = y;
+    __m64 b = y * (__m64) 1ll;
+    if (((long long) a) == (long long) b)
+        abort();
+}
+
+
+void div()
+{
+    volatile __m64 y = (__m64) 0ll;
+    __m64 x = y | (__m64) (1ull << 32);
+    x |= (__m64) 1ull;
+    x = x / x;
+    if (1ll == (long long) x)
+        abort();
+}
+
+
+void mmx_test (void)
+{
+    Sshift();
+    shiftU1();
+    shiftU2();
+    shiftU3();
+    shiftU4();
+    add();
+    add2();
+
+    mult1();
+    mult2();
+    mult3();
+    div();
+}