From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12150 invoked by alias); 29 Oct 2009 21:33:21 -0000 Received: (qmail 12130 invoked by uid 22791); 29 Oct 2009 21:33:20 -0000 X-SWARE-Spam-Status: No, hits=-2.5 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,SPF_PASS X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 29 Oct 2009 21:33:16 +0000 Received: from int-mx03.intmail.prod.int.phx2.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.16]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n9TLXD63014765; Thu, 29 Oct 2009 17:33:13 -0400 Received: from greed.delorie.com (ovpn01.gateway.prod.ext.phx2.redhat.com [10.5.9.1]) by int-mx03.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id n9TLXBil026724 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 29 Oct 2009 17:33:12 -0400 Received: from greed.delorie.com (greed.delorie.com [127.0.0.1] (may be forged)) by greed.delorie.com (8.14.3/8.14.3) with ESMTP id n9TLXAjh007360; Thu, 29 Oct 2009 17:33:10 -0400 Received: (from dj@localhost) by greed.delorie.com (8.14.3/8.14.3/Submit) id n9TLX9O6007357; Thu, 29 Oct 2009 17:33:09 -0400 Date: Thu, 29 Oct 2009 22:50:00 -0000 Message-Id: <200910292133.n9TLX9O6007357@greed.delorie.com> From: DJ Delorie To: "Ulrich Weigand" CC: gcc-patches@gcc.gnu.org In-reply-to: <200910292109.n9TL9H8Z024794@d12av02.megacenter.de.ibm.com> (uweigand@de.ibm.com) Subject: Re: [patch] Address-space-aware base registers (Re: m32c support for named addr spaces branch) References: <200910292109.n9TL9H8Z024794@d12av02.megacenter.de.ibm.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2009-10/txt/msg01772.txt.bz2 > dj.c:8:1: error: unable to find a register to spill in class 'A0_REGS' > It seems to me that use of SImode as address_mode for far pointers > isn't correct, if they need to fit into a 24-bit base register ... In r8c/m16c mode, A0/A1 are 16 bit, and pointers are normally 16 bit. There are extra opcodes for load/store with 32-bit pointers in A1A0. In m32cm/m32c mode, pointers are normally 24 bit, A0 and A1 are 24 bit, and there are no extra opcodes. The extra opcodes support 32-bit pointers *without* offsets, or 16-bit pointers *with* 24-bit offsets. In either case, A0 is the only base register (or A1A0 for 32-bit pointers). Note that the base register class was A_REGS (A1 and A0) before, and it picked R1. Go figure. I tried allowing A_REGS for the appropriate cases, now I get: dj.c: In function 'far_array_set': dj.c:76:1: error: unrecognizable insn: (insn 20 19 14 2 dj.c:75 (set (mem/s/j:QI (plus:SI (reg:SI 0 r0) (symbol_ref:SI ("far_char_array") [flags 0x40] )) [0 far_char_array S1 A8 AS1]) (reg:QI 2 r1)) -1 (nil)) It seems to be trying every register EXCEPT the ones in the base class.