Minor SPARC tweaks

Minor SPARC tweaks

[Eric Botcazou]

[-- Attachment #1: Type: text/plain, Size: 430 bytes --]

...that I already wanted to make but never got around to making before.

No functional changes, applied on the mainline.


2009-11-30  Eric Botcazou  <ebotcazou@adacore.com>

	* config/sparc/sparc.c (DF_MODES): Simplify.
	(TF_ONLY_MODES, OF_ONLY_MODES): Delete.
	(TF_MODES, OF_MODES): Adjust for above change.
	(TF_MODES_NO_S, OF_MODES_NO_S): Likewise.
	*  config/sparc/sparc.h (REGNO_REG_CLASS): Move around.


-- 
Eric Botcazou

[-- Attachment #2: p.diff --]
[-- Type: text/x-diff, Size: 3190 bytes --]

Index: config/sparc/sparc.c
===================================================================
--- config/sparc/sparc.c	(revision 154697)
+++ config/sparc/sparc.c	(working copy)
@@ -3733,27 +3733,22 @@ enum sparc_mode_class {
 #define SF_MODES (S_MODES)
 
 /* Modes for double-float and smaller quantities.  */
-#define DF_MODES (S_MODES | D_MODES)
-
-/* Modes for double-float only quantities.  */
-#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
-
-/* Modes for quad-float only quantities.  */
-#define TF_ONLY_MODES (1 << (int) TF_MODE)
+#define DF_MODES (D_MODES)
 
 /* Modes for quad-float and smaller quantities.  */
-#define TF_MODES (DF_MODES | TF_ONLY_MODES)
+#define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
 
-/* Modes for quad-float and double-float quantities.  */
-#define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
+/* Modes for quad-float pairs and smaller quantities.  */
+#define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
 
-/* Modes for quad-float pair only quantities.  */
-#define OF_ONLY_MODES (1 << (int) OF_MODE)
+/* Modes for double-float only quantities.  */
+#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
 
-/* Modes for quad-float pairs and smaller quantities.  */
-#define OF_MODES (TF_MODES | OF_ONLY_MODES)
+/* Modes for quad-float and double-float only quantities.  */
+#define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
 
-#define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
+/* Modes for quad-float pairs and double-float only quantities.  */
+#define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
 
 /* Modes for condition codes.  */
 #define CC_MODES (1 << (int) CC_MODE)
Index: config/sparc/sparc.h
===================================================================
--- config/sparc/sparc.h	(revision 154697)
+++ config/sparc/sparc.h	(working copy)
@@ -1068,6 +1068,15 @@ enum reg_class { NO_REGS, FPCC_REGS, I64
    {-1, -1, -1, 0x20},	/* GENERAL_OR_EXTRA_FP_REGS */	\
    {-1, -1, -1, 0x3f}}	/* ALL_REGS */
 
+/* The same information, inverted:
+   Return the class number of the smallest class containing
+   reg number REGNO.  This could be a conditional expression
+   or could index an array.  */
+
+extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
+
+#define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
+
 /* The following macro defines cover classes for Integrated Register
    Allocator.  Cover classes is a set of non-intersected register
    classes covering all hard registers used for register allocation
@@ -1095,15 +1104,6 @@ enum reg_class { NO_REGS, FPCC_REGS, I64
    && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)		\
    ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
 
-/* The same information, inverted:
-   Return the class number of the smallest class containing
-   reg number REGNO.  This could be a conditional expression
-   or could index an array.  */
-
-extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
-
-#define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
-
 /* This is the order in which to allocate registers normally.
 
    We put %f0-%f7 last among the float registers, so as to make it more