[PATCH] Add VIS intrinsics header for sparc.

[PATCH] Add VIS intrinsics header for sparc.

[David Miller]

I've been meaning to toss something like this together for a while.

If we were going to do this, I wanted to get it out of the way before
adding VIS2 and VIS3 support.

I considered trying to make a set of VIS headers compatible with the
vis_*.h headers Sun provides in medialib and Sun Studio, but that's
not possible since we use fundamentally different types in the
builtins provided by GCC.

Sun uses "double" and "float" in the declarations whereas we use our
vector types.

I even checked various users of Sun's VIS intrinsics and they all just
declare their vector variables as "float" and "double" so it would be
impossible to provide headers that would work out of the box.

Eric, any objections?

2011-09-16  David S. Miller  <davem@davemloft.net>

	* config/sparc/visintrin.h: New file.
	* config.gcc: Add it to extra_headers on sparc.

diff --git a/gcc/config.gcc b/gcc/config.gcc
index e442fa7..7183f26 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -422,6 +422,7 @@ score*-*-*)
 	;;
 sparc*-*-*)
 	cpu_type=sparc
+	extra_headers="visintrin.h"
 	need_64bit_hwint=yes
 	;;
 spu*-*-*)
--- /dev/null	2011-09-11 10:37:28.169997151 -0700
+++ b/gcc/config/sparc/visintrin.h	2011-09-14 21:20:35.000000000 -0700
@@ -0,0 +1,160 @@
+/* Copyright (C) 2011 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _VISINTRIN_H_INCLUDED
+#define _VISINTRIN_H_INCLUDED
+
+typedef int __v2si __attribute__ ((__vector_size__ (8)));
+typedef short __v4hi __attribute__ ((__vector_size__ (8)));
+typedef short __v2hi __attribute__ ((__vector_size__ (4)));
+typedef char __v8qi __attribute__ ((__vector_size__ (8)));
+typedef char __v4qi __attribute__ ((__vector_size__ (4)));
+typedef int __i64 __attribute__ ((__mode__ (DI)));
+
+extern __inline void *
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_alignaddr (void *__A, long __B)
+{
+	return __builtin_vis_alignaddr(__A, __B);
+}
+
+extern __inline __i64
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_faligndatadi (__i64 __A)
+{
+	return __builtin_vis_faligndatadi (__A);
+}
+
+extern __inline __v2si
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_faligndatav2si (__v2si __A)
+{
+	return __builtin_vis_faligndatav2si (__A);
+}
+
+extern __inline __v4hi
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_faligndatav4hi (__v4hi __A)
+{
+	return __builtin_vis_faligndatav4hi (__A);
+}
+
+extern __inline __v8qi
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_faligndatav8qi (__v8qi __A)
+{
+	return __builtin_vis_faligndatav8qi (__A);
+}
+
+extern __inline __v4hi
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_fexpand (__v4qi __A)
+{
+	return __builtin_vis_fexpand (__A);
+}
+
+extern __inline __v4hi
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_fmul8x16 (__v4qi __A, __v4hi __B)
+{
+	return __builtin_vis_fmul8x16 (__A, __B);
+}
+
+extern __inline __v4hi
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_fmul8x16au (__v4qi __A, __v4hi __B)
+{
+	return __builtin_vis_fmul8x16au (__A, __B);
+}
+
+extern __inline __v4hi
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_fmul8x16al (__v4qi __A, __v4hi __B)
+{
+	return __builtin_vis_fmul8x16al (__A, __B);
+}
+
+extern __inline __v4hi
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_fmul8sux16 (__v8qi __A, __v4hi __B)
+{
+	return __builtin_vis_fmul8sux16 (__A, __B);
+}
+
+extern __inline __v4hi
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_fmul8ulx16 (__v8qi __A, __v4hi __B)
+{
+	return __builtin_vis_fmul8ulx16 (__A, __B);
+}
+
+extern __inline __v2si
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_fmuld8sux16 (__v4qi __A, __v2hi __B)
+{
+	return __builtin_vis_fmuld8sux16 (__A, __B);
+}
+
+extern __inline __v2si
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_fmuld8ulx16 (__v4qi __A, __v2hi __B)
+{
+	return __builtin_vis_fmuld8ulx16 (__A, __B);
+}
+
+extern __inline __v4qi
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_fpack16 (__v4hi __A)
+{
+	return __builtin_vis_fpack16 (__A);
+}
+
+extern __inline __v8qi
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_fpack32 (__v2si __A, __v2si __B)
+{
+	return __builtin_vis_fpack32 (__A, __B);
+}
+
+extern __inline __v2hi
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_fpackfix (__v2si __A)
+{
+	return __builtin_vis_fpackfix (__A);
+}
+
+extern __inline __v8qi
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_fpmerge (__v4qi __A, __v4qi __B)
+{
+	return __builtin_vis_fpmerge (__A, __B);
+}
+
+extern __inline __i64
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_pdist (__v8qi __A, __v8qi __B, __i64 __C)
+{
+	return __builtin_vis_pdist (__A, __B, __C);
+}
+
+#endif  /* _VISINTRIN_H_INCLUDED */

Re: [PATCH] Add VIS intrinsics header for sparc.

[Jakub Jelinek]

On Fri, Sep 16, 2011 at 03:02:07PM -0400, David Miller wrote:
> +extern __inline void *
> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
> +__vis_alignaddr (void *__A, long __B)
> +{
> +	return __builtin_vis_alignaddr(__A, __B);

Just formatting nits, two spaces instead of tab to indent and
space in between function name and (.

	Jakub

Re: [PATCH] Add VIS intrinsics header for sparc.

[David Miller]

From: Jakub Jelinek <jakub@redhat.com>
Date: Fri, 16 Sep 2011 21:07:09 +0200

> On Fri, Sep 16, 2011 at 03:02:07PM -0400, David Miller wrote:
>> +extern __inline void *
>> +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
>> +__vis_alignaddr (void *__A, long __B)
>> +{
>> +	return __builtin_vis_alignaddr(__A, __B);
> 
> Just formatting nits, two spaces instead of tab to indent and
> space in between function name and (.

Thanks Jakub, I'll fix those up.

Re: [PATCH] Add VIS intrinsics header for sparc.

[Eric Botcazou]

> I considered trying to make a set of VIS headers compatible with the
> vis_*.h headers Sun provides in medialib and Sun Studio, but that's
> not possible since we use fundamentally different types in the
> builtins provided by GCC.
>
> Sun uses "double" and "float" in the declarations whereas we use our
> vector types.
>
> I even checked various users of Sun's VIS intrinsics and they all just
> declare their vector variables as "float" and "double" so it would be
> impossible to provide headers that would work out of the box.

Yes, I have some recollections of that.

> Eric, any objections?

None, this looks OK to me.

-- 
Eric Botcazou

Re: [PATCH] Add VIS intrinsics header for sparc.

[David Miller]

From: Eric Botcazou <ebotcazou@adacore.com>
Date: Fri, 16 Sep 2011 23:01:56 +0200

>> Eric, any objections?
> 
> None, this looks OK to me.

Thanks Eric, I'll check this in.

Re: [PATCH] Add VIS intrinsics header for sparc.

[Hans-Peter Nilsson]

On Fri, 16 Sep 2011, David Miller wrote:
>
> I've been meaning to toss something like this together for a while.
>
> If we were going to do this, I wanted to get it out of the way before
> adding VIS2 and VIS3 support.

While revisiting VIS, *please* consider fixing a big usability
problem: the pack and aligndata builtins don't take GSR in
account; it has unknown state and might be changed as a
side-effect of a previous VIS insn (well, alignaddr).  The
affected builtins don't have dependencies to GSR or a means to
set it besides in an asm; hardly usable at all.  See PR48974.

brgds, H-P

Re: [PATCH] Add VIS intrinsics header for sparc.

[David Miller]

From: Hans-Peter Nilsson <hp@bitrange.com>
Date: Wed, 21 Sep 2011 21:27:08 -0400 (EDT)

> While revisiting VIS, *please* consider fixing a big usability
> problem: the pack and aligndata builtins don't take GSR in
> account; it has unknown state and might be changed as a
> side-effect of a previous VIS insn (well, alignaddr).  The
> affected builtins don't have dependencies to GSR or a means to
> set it besides in an asm; hardly usable at all.  See PR48974.

I know, see my posting from yesterday:

--------------------
Subject: [PATCH] Use TREE_READONLY on some sparc VIS builtins

While fiddling around with the VIS intrinsic builtins I noticed that
none of them have TREE_READONLY set, so the resulting code can be
terrible.

We can't currently do this for alignaddr and faligndata because we
don't model the way those instructions use the %gsr register.
--------------------

Re: [PATCH] Add VIS intrinsics header for sparc.

[Hans-Peter Nilsson]

On Wed, 21 Sep 2011, David Miller wrote:
> From: Hans-Peter Nilsson <hp@bitrange.com>
> Date: Wed, 21 Sep 2011 21:27:08 -0400 (EDT)
>
> > While revisiting VIS, *please* consider fixing a big usability
> > problem: the pack and aligndata builtins don't take GSR in
> > account; it has unknown state and might be changed as a
> > side-effect of a previous VIS insn (well, alignaddr).  The
> > affected builtins don't have dependencies to GSR or a means to
> > set it besides in an asm; hardly usable at all.  See PR48974.
>
> I know, see my posting from yesterday:
>
> --------------------
> Subject: [PATCH] Use TREE_READONLY on some sparc VIS builtins
>
> While fiddling around with the VIS intrinsic builtins I noticed that
> none of them have TREE_READONLY set, so the resulting code can be
> terrible.
>
> We can't currently do this for alignaddr and faligndata because we
> don't model the way those instructions use the %gsr register.

Minor inconsistency spotted there: the same goes for the fpack
insns but you now set TREE_READONLY for them.  (Not claiming I
caught all of them.)

brgds, H-P

Re: [PATCH] Add VIS intrinsics header for sparc.

[David Miller]

From: Hans-Peter Nilsson <hp@bitrange.com>
Date: Wed, 21 Sep 2011 23:27:38 -0400 (EDT)

> Minor inconsistency spotted there: the same goes for the fpack
> insns but you now set TREE_READONLY for them.  (Not claiming I
> caught all of them.)

Thanks a lot for pointing this out, I'll remove the TREE_READONLY flag
for these operations.

Positive feedback for the fact that someone is at least working on
this stuff at all would be appreciated as well.

Re: [PATCH] Add VIS intrinsics header for sparc.

[Hans-Peter Nilsson]

On Thu, 22 Sep 2011, David Miller wrote:
> Positive feedback for the fact that someone is at least working on
> this stuff at all would be appreciated as well.

Using it or working on it?  Not that much of either, sorry, but
what I found when using it, I put in PR48974 (well, besides the
ICE's, which got separate PR's, of which Eric's been fixing some).

(For VIS, why not make use of fone / fones!)

brgds, H-P

Re: [PATCH] Add VIS intrinsics header for sparc.

[David Miller]

Hans, here is what I'm playing with right now against current
trunk.

I looked at the use cases for making use of the scale factor in the
VIS %gsr register and it's used similar to how rounding modes are
modified in the FPU control register.

You have a function, or family of functions, that want to operate with
a certain scale factor.  And at the top level the first thing you do
is set the %gsr as you want it to be set.

So I've added a GSR register to the sparc backend and then added
__vis_write_gsr() and __vis_read_gsr() functions to facilitate the
use cases I've seen.

This allowed me to describe to the compiler exactly what the alignaddr
instructions do, and thus the unspecs for them are now gone.

The pack and faligndata intrinsics still need to be unspec, and thus I
merely added GSR uses to those patterns which is enough to let the
compiler get the dataflow right.

This all seems sufficient for what things like Sun's medialib and your
RAPP project want to do.

I'll look into your other suggestion in PR48974, namely making use of
fone VIS instructions.

Thanks.

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index d62d5a1..f38ecda 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -329,7 +329,7 @@ char leaf_reg_remap[] =
   72, 73, 74, 75, 76, 77, 78, 79,
   80, 81, 82, 83, 84, 85, 86, 87,
   88, 89, 90, 91, 92, 93, 94, 95,
-  96, 97, 98, 99, 100};
+  96, 97, 98, 99, 100, 101, 102};
 
 /* Vector, indexed by hard register number, which contains 1
    for a register that is allowable in a candidate for leaf
@@ -347,7 +347,7 @@ char sparc_leaf_regs[] =
   1, 1, 1, 1, 1, 1, 1, 1,
   1, 1, 1, 1, 1, 1, 1, 1,
   1, 1, 1, 1, 1, 1, 1, 1,
-  1, 1, 1, 1, 1};
+  1, 1, 1, 1, 1, 1, 1};
 
 struct GTY(()) machine_function
 {
@@ -4036,8 +4036,8 @@ static const int hard_32bit_mode_classes[] = {
   /* %fcc[0123] */
   CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
 
-  /* %icc */
-  CC_MODES
+  /* %icc, %sfp, %gsr */
+  CC_MODES, 0, S_MODES
 };
 
 static const int hard_64bit_mode_classes[] = {
@@ -4061,8 +4061,8 @@ static const int hard_64bit_mode_classes[] = {
   /* %fcc[0123] */
   CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
 
-  /* %icc */
-  CC_MODES
+  /* %icc, %sfp, %gsr */
+  CC_MODES, 0, S_MODES
 };
 
 int sparc_mode_class [NUM_MACHINE_MODES];
@@ -9168,14 +9168,18 @@ sparc_vis_init_builtins (void)
 						      v4hi, v4hi, 0);
   tree si_ftype_v2si_v2si = build_function_type_list (intSI_type_node,
 						      v2si, v2si, 0);
+  tree void_ftype_si = build_function_type_list (void_type_node,
+						 intSI_type_node, 0);
+  tree si_ftype_void = build_function_type_list (intSI_type_node,
+						 void_type_node, 0);
 
   /* Packing and expanding vectors.  */
-  def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis,
-	       v4qi_ftype_v4hi);
-  def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
-	       v8qi_ftype_v2si_v8qi);
-  def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
-	       v2hi_ftype_v2si);
+  def_builtin_const ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis,
+		     v4qi_ftype_v4hi);
+  def_builtin_const ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
+		     v8qi_ftype_v2si_v8qi);
+  def_builtin_const ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
+		     v2hi_ftype_v2si);
   def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis,
 		     v4hi_ftype_v4qi);
   def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis,
@@ -9198,27 +9202,33 @@ sparc_vis_init_builtins (void)
 		     v2si_ftype_v4qi_v2hi);
 
   /* Data aligning.  */
-  def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
-	       v4hi_ftype_v4hi_v4hi);
-  def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
-	       v8qi_ftype_v8qi_v8qi);
-  def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
-	       v2si_ftype_v2si_v2si);
-  def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis,
-	       di_ftype_di_di);
+  def_builtin_const ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis,
+		     v4hi_ftype_v4hi_v4hi);
+  def_builtin_const ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis,
+		     v8qi_ftype_v8qi_v8qi);
+  def_builtin_const ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis,
+		     v2si_ftype_v2si_v2si);
+  def_builtin_const ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis,
+		     di_ftype_di_di);
+
+  def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis,
+	       void_ftype_si);
+  def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis,
+	       si_ftype_void);
+
   if (TARGET_ARCH64)
     {
-      def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
-		   ptr_ftype_ptr_di);
-      def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis,
-		   ptr_ftype_ptr_di);
+      def_builtin_const ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
+			 ptr_ftype_ptr_di);
+      def_builtin_const ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis,
+			 ptr_ftype_ptr_di);
     }
   else
     {
-      def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
-		   ptr_ftype_ptr_si);
-      def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis,
-		   ptr_ftype_ptr_si);
+      def_builtin_const ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis,
+			 ptr_ftype_ptr_si);
+      def_builtin_const ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis,
+			 ptr_ftype_ptr_si);
     }
 
   /* Pixel distance.  */
@@ -9289,32 +9299,47 @@ sparc_expand_builtin (tree exp, rtx target,
   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
   unsigned int icode = DECL_FUNCTION_CODE (fndecl);
   rtx pat, op[4];
-  enum machine_mode mode[4];
   int arg_count = 0;
+  bool nonvoid;
 
-  mode[0] = insn_data[icode].operand[0].mode;
-  if (!target
-      || GET_MODE (target) != mode[0]
-      || ! (*insn_data[icode].operand[0].predicate) (target, mode[0]))
-    op[0] = gen_reg_rtx (mode[0]);
-  else
-    op[0] = target;
+  nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
 
+  if (nonvoid)
+    {
+      enum machine_mode tmode = insn_data[icode].operand[0].mode;
+      if (!target
+	  || GET_MODE (target) != tmode
+	  || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
+	op[0] = gen_reg_rtx (tmode);
+      else
+	op[0] = target;
+    }
   FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
     {
+      const struct insn_operand_data *insn_op;
+
+      if (arg == error_mark_node)
+	return NULL_RTX;
+
       arg_count++;
-      mode[arg_count] = insn_data[icode].operand[arg_count].mode;
+      insn_op = &insn_data[icode].operand[arg_count - !nonvoid];
       op[arg_count] = expand_normal (arg);
 
       if (! (*insn_data[icode].operand[arg_count].predicate) (op[arg_count],
-							      mode[arg_count]))
-	op[arg_count] = copy_to_mode_reg (mode[arg_count], op[arg_count]);
+							      insn_op->mode))
+	op[arg_count] = copy_to_mode_reg (insn_op->mode, op[arg_count]);
     }
 
   switch (arg_count)
     {
+    case 0:
+      pat = GEN_FCN (icode) (op[0]);
+      break;
     case 1:
-      pat = GEN_FCN (icode) (op[0], op[1]);
+      if (nonvoid)
+	pat = GEN_FCN (icode) (op[0], op[1]);
+      else
+	pat = GEN_FCN (icode) (op[1]);
       break;
     case 2:
       pat = GEN_FCN (icode) (op[0], op[1], op[2]);
@@ -9331,7 +9356,10 @@ sparc_expand_builtin (tree exp, rtx target,
 
   emit_insn (pat);
 
-  return op[0];
+  if (nonvoid)
+    return op[0];
+  else
+    return const0_rtx;
 }
 
 static int
@@ -9416,7 +9444,8 @@ sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
 
   if (ignore
       && icode != CODE_FOR_alignaddrsi_vis
-      && icode != CODE_FOR_alignaddrdi_vis)
+      && icode != CODE_FOR_alignaddrdi_vis
+      && icode != CODE_FOR_wrgsr_vis)
     return build_zero_cst (rtype);
 
   switch (icode)
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index afdca1e..77eff2e 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -691,7 +691,7 @@ extern enum cmodel sparc_cmodel;
    Register 100 is used as the integer condition code register.
    Register 101 is used as the soft frame pointer register.  */
 
-#define FIRST_PSEUDO_REGISTER 102
+#define FIRST_PSEUDO_REGISTER 103
 
 #define SPARC_FIRST_FP_REG     32
 /* Additional V9 fp regs.  */
@@ -704,6 +704,7 @@ extern enum cmodel sparc_cmodel;
 #define SPARC_FCC_REG 96
 /* Integer CC reg.  We don't distinguish %icc from %xcc.  */
 #define SPARC_ICC_REG 100
+#define SPARC_GSR_REG 102
 
 /* Nonzero if REGNO is an fp reg.  */
 #define SPARC_FP_REG_P(REGNO) \
@@ -757,7 +758,7 @@ extern enum cmodel sparc_cmodel;
   0, 0, 0, 0, 0, 0, 0, 0,	\
   0, 0, 0, 0, 0, 0, 0, 0,	\
 				\
-  0, 0, 0, 0, 0, 1}
+  0, 0, 0, 0, 0, 1, 1}
 
 /* 1 for registers not available across function calls.
    These must include the FIXED_REGISTERS and also any
@@ -782,7 +783,7 @@ extern enum cmodel sparc_cmodel;
   1, 1, 1, 1, 1, 1, 1, 1,	\
   1, 1, 1, 1, 1, 1, 1, 1,	\
 				\
-  1, 1, 1, 1, 1, 1}
+  1, 1, 1, 1, 1, 1, 1}
 
 /* Return number of consecutive hard regs needed starting at reg REGNO
    to hold something of mode MODE.
@@ -796,11 +797,12 @@ extern enum cmodel sparc_cmodel;
    included in the hard register count).  */
 
 #define HARD_REGNO_NREGS(REGNO, MODE) \
-  (TARGET_ARCH64							\
-   ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM			\
-      ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD	\
-      : (GET_MODE_SIZE (MODE) + 3) / 4)					\
-   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+  ((REGNO) == SPARC_GSR_REG ? 1 :					\
+   (TARGET_ARCH64							\
+    ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM			\
+       ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD	\
+       : (GET_MODE_SIZE (MODE) + 3) / 4)				\
+    : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
 
 /* Due to the ARCH64 discrepancy above we must override this next
    macro too.  */
@@ -985,7 +987,7 @@ enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
    {0, -1, -1, 0},	/* EXTRA_FP_REGS */		\
    {-1, -1, 0, 0x20},	/* GENERAL_OR_FP_REGS */	\
    {-1, -1, -1, 0x20},	/* GENERAL_OR_EXTRA_FP_REGS */	\
-   {-1, -1, -1, 0x3f}}	/* ALL_REGS */
+   {-1, -1, -1, 0x7f}}	/* ALL_REGS */
 
 /* The same information, inverted:
    Return the class number of the smallest class containing
@@ -1046,7 +1048,7 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
   88, 89, 90, 91, 92, 93, 94, 95,	/* %f56-%f63 */ \
   39, 38, 37, 36, 35, 34, 33, 32,	/* %f7-%f0 */   \
   96, 97, 98, 99,			/* %fcc0-3 */   \
-  100, 0, 14, 30, 101}			/* %icc, %g0, %o6, %i6, %sfp */
+  100, 0, 14, 30, 101, 102 }		/* %icc, %g0, %o6, %i6, %sfp, %gsr */
 
 /* This is the order in which to allocate registers for
    leaf functions.  If all registers can fit in the global and
@@ -1085,7 +1087,7 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
   88, 89, 90, 91, 92, 93, 94, 95,	/* %f56-%f63 */	\
   39, 38, 37, 36, 35, 34, 33, 32,	/* %f7-%f0 */	\
   96, 97, 98, 99,			/* %fcc0-3 */	\
-  100, 0, 14, 30, 31, 101}		/* %icc, %g0, %o6, %i6, %i7, %sfp */
+  100, 0, 14, 30, 31, 101, 102 }	/* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */
 
 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
 
@@ -1724,7 +1726,7 @@ do {									   \
  "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47",	\
  "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55",	\
  "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63",	\
- "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
+ "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp", "%gsr" }
 
 /* Define additional names for use in asm clobbers and asm declarations.  */
 
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 588caf3..200846e 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -58,7 +58,7 @@
    (UNSPEC_MUL8UL		46)
    (UNSPEC_MULDUL		47)
    (UNSPEC_ALIGNDATA		48)
-   (UNSPEC_ALIGNADDR		49)
+
    (UNSPEC_PDIST		50)
    (UNSPEC_EDGE8		51)
    (UNSPEC_EDGE8L		52)
@@ -66,7 +66,6 @@
    (UNSPEC_EDGE16L		54)
    (UNSPEC_EDGE32		55)
    (UNSPEC_EDGE32L		56)
-   (UNSPEC_ALIGNADDRL		57)
 
    (UNSPEC_SP_SET		60)
    (UNSPEC_SP_TEST		61)
@@ -176,6 +175,7 @@
   (FCC3_REG			99)
   (CC_REG			100)
   (SFP_REG			101)
+  (GSR_REG			102)
  ])
 
 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
@@ -7752,7 +7752,8 @@
 (define_insn "fpack16_vis"
   [(set (match_operand:V4QI 0 "register_operand" "=f")
         (unspec:V4QI [(match_operand:V4HI 1 "register_operand" "e")]
-		      UNSPEC_FPACK16))]
+		      UNSPEC_FPACK16))
+   (use (reg:SI GSR_REG))]
   "TARGET_VIS"
   "fpack16\t%1, %0"
   [(set_attr "type" "fga")
@@ -7761,7 +7762,8 @@
 (define_insn "fpackfix_vis"
   [(set (match_operand:V2HI 0 "register_operand" "=f")
         (unspec:V2HI [(match_operand:V2SI 1 "register_operand" "e")]
-		      UNSPEC_FPACKFIX))]
+		      UNSPEC_FPACKFIX))
+   (use (reg:SI GSR_REG))]
   "TARGET_VIS"
   "fpackfix\t%1, %0"
   [(set_attr "type" "fga")
@@ -7771,7 +7773,8 @@
   [(set (match_operand:V8QI 0 "register_operand" "=e")
         (unspec:V8QI [(match_operand:V2SI 1 "register_operand" "e")
         	      (match_operand:V8QI 2 "register_operand" "e")]
-                     UNSPEC_FPACK32))]
+                     UNSPEC_FPACK32))
+   (use (reg:SI GSR_REG))]
   "TARGET_VIS"
   "fpack32\t%1, %2, %0"
   [(set_attr "type" "fga")
@@ -7871,6 +7874,18 @@
   [(set_attr "type" "fpmul")
    (set_attr "fptype" "double")])
 
+(define_insn "wrgsr_vis"
+  [(set (reg:SI GSR_REG) (match_operand:SI 0 "arith_operand" "rI"))]
+  "TARGET_VIS"
+  "wr\t%%g0, %0, %%gsr"
+  [(set_attr "type" "multi")])
+
+(define_insn "rdgsr_vis"
+  [(set (match_operand:SI 0 "register_operand" "=r") (reg:SI GSR_REG))]
+  "TARGET_VIS"
+  "rd\t%%gsr, %0"
+  [(set_attr "type" "multi")])
+
 ;; Using faligndata only makes sense after an alignaddr since the choice of
 ;; bytes to take out of each operand is dependent on the results of the last
 ;; alignaddr.
@@ -7878,25 +7893,57 @@
   [(set (match_operand:V64I 0 "register_operand" "=e")
         (unspec:V64I [(match_operand:V64I 1 "register_operand" "e")
                       (match_operand:V64I 2 "register_operand" "e")]
-         UNSPEC_ALIGNDATA))]
+         UNSPEC_ALIGNDATA))
+   (use (reg:SI GSR_REG))]
   "TARGET_VIS"
   "faligndata\t%1, %2, %0"
   [(set_attr "type" "fga")
    (set_attr "fptype" "double")])
 
-(define_insn "alignaddr<P:mode>_vis"
-  [(set (match_operand:P 0 "register_operand" "=r")
-        (unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ")
-                   (match_operand:P 2 "register_or_zero_operand" "rJ")]
-         UNSPEC_ALIGNADDR))]
+(define_insn "alignaddrsi_vis"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (plus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
+                 (match_operand:SI 2 "register_or_zero_operand" "rJ")))
+   (set (reg:SI GSR_REG)
+        (ior:SI (and:SI (reg:SI GSR_REG) (const_int -8))
+                (and:SI (plus:SI (match_dup 1) (match_dup 2))
+                        (const_int 7))))]
   "TARGET_VIS"
   "alignaddr\t%r1, %r2, %0")
 
-(define_insn "alignaddrl<P:mode>_vis"
-  [(set (match_operand:P 0 "register_operand" "=r")
-        (unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ")
-                   (match_operand:P 2 "register_or_zero_operand" "rJ")]
-         UNSPEC_ALIGNADDRL))]
+(define_insn "alignaddrdi_vis"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (plus:DI (match_operand:DI 1 "register_or_zero_operand" "rJ")
+                 (match_operand:DI 2 "register_or_zero_operand" "rJ")))
+   (set (reg:SI GSR_REG)
+        (ior:SI (and:SI (reg:SI GSR_REG) (const_int -8))
+                (and:SI (truncate:SI (plus:DI (match_dup 1) (match_dup 2)))
+                        (const_int 7))))]
+  "TARGET_VIS"
+  "alignaddr\t%r1, %r2, %0")
+
+(define_insn "alignaddrlsi_vis"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (plus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
+                 (match_operand:SI 2 "register_or_zero_operand" "rJ")))
+   (set (reg:SI GSR_REG)
+        (ior:SI (and:SI (reg:SI GSR_REG) (const_int -8))
+                (xor:SI (and:SI (plus:SI (match_dup 1) (match_dup 2))
+                                (const_int 7))
+                        (const_int 7))))]
+  "TARGET_VIS"
+  "alignaddrl\t%r1, %r2, %0")
+
+(define_insn "alignaddrldi_vis"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (plus:DI (match_operand:DI 1 "register_or_zero_operand" "rJ")
+                 (match_operand:DI 2 "register_or_zero_operand" "rJ")))
+   (set (reg:SI GSR_REG)
+        (ior:SI (and:SI (reg:SI GSR_REG) (const_int -8))
+                (xor:SI (and:SI (truncate:SI (plus:DI (match_dup 1)
+                                                      (match_dup 2)))
+                                (const_int 7))
+                        (const_int 7))))]
   "TARGET_VIS"
   "alignaddrl\t%r1, %r2, %0")
 
diff --git a/gcc/config/sparc/visintrin.h b/gcc/config/sparc/visintrin.h
index 4c2fa18..37c1113 100644
--- a/gcc/config/sparc/visintrin.h
+++ b/gcc/config/sparc/visintrin.h
@@ -31,6 +31,20 @@ typedef unsigned char __v8qi __attribute__ ((__vector_size__ (8)));
 typedef unsigned char __v4qi __attribute__ ((__vector_size__ (4)));
 typedef int __i64 __attribute__ ((__mode__ (DI)));
 
+extern __inline void
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_write_gsr (int __A)
+{
+  __builtin_vis_write_gsr (__A);
+}
+
+extern __inline int
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+__vis_read_gsr (void)
+{
+  return __builtin_vis_read_gsr ();
+}
+
 extern __inline void *
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 __vis_alignaddr (void *__A, long __B)

Re: [PATCH] Add VIS intrinsics header for sparc.

[Hans-Peter Nilsson]

On Sat, 24 Sep 2011, David Miller wrote:
> Hans, here is what I'm playing with right now against current
> trunk.

A spot-check review:

> I looked at the use cases for making use of the scale factor in the
> VIS %gsr register and it's used similar to how rounding modes are
> modified in the FPU control register.

It's more of a parameter actually, GSR.scale_factor is the
bit-shift count for the pack insns and GSR.alignaddr_offset the
byte-shift in the aligndata insns.

> You have a function, or family of functions, that want to operate with
> a certain scale factor.  And at the top level the first thing you do
> is set the %gsr as you want it to be set.

Certainly an improvement, but...

> So I've added a GSR register to the sparc backend and then added
> __vis_write_gsr() and __vis_read_gsr() functions to facilitate the
> use cases I've seen.

I'd prefer it as a parameter to the builtins (expanding to two
insns, letting gcc get rid of the redundant ones; let the
initialization value be 0).  I understand you're trying to keep
some kind of compatibility there, but additional builtins would
do the trick and fit nicely: the new builtins expanding to a set
of GSR (GSR field) followed by the "old" insn but fixed as in
this patch.  Besides, the functions that use GSR still can't be
const in this patch.  I guess they never can, when you think of
it, setting and/or using a register that can affect/be affected
something elsewhere, when that something is known to gcc.  Oh well.

Another aspect would be to model the different GSR fields as
different registers; they're used completely differently and
just happen to be set with the same insn.  That might help gcc
getting rid of redundant settings.

> This allowed me to describe to the compiler exactly what the alignaddr
> instructions do, and thus the unspecs for them are now gone.
>
> The pack and faligndata intrinsics still need to be unspec,

FWIW not "need"; IIUC at least faligndata *can* be a vec_select
of a vec_concat of the two vectors, but in practice I don't
think gcc can make use of it yet and all ports use unspec...

While on faligndata, see vec_realign_load_<mode> (sadly
undocumented at present); it'll enable the autovectorizer to...
autovectorize some more.  (Right, I'm working on [yet] another
SIMD back-end, implemented as MIPS COP2 insns.)

> and thus I
> merely added GSR uses to those patterns which is enough to let the
> compiler get the dataflow right.

How about putting it inside the unspec vector?  Those "use"
thingies always gives me the creeps; outside of an insn (no, not
here) they're sometimes lost and at least disconnected to the
insn.  I think practically there's no difference here.

> This all seems sufficient for what things like Sun's medialib and your
> RAPP project want to do.
>
> I'll look into your other suggestion in PR48974, namely making use of
> fone VIS instructions.

One more: please consider adding a
 if (TARGET_VIS) builtin_define ("__VIS__=something") so I as a
user theoretically wouldn't *have* to autoconfiscate for the
changes. ;)

> +  def_builtin_const ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis,
> +		     v4qi_ftype_v4hi);
> +  def_builtin_const ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
> +		     v8qi_ftype_v2si_v8qi);
> +  def_builtin_const ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
> +		     v2hi_ftype_v2si);
>    def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis,
>  		     v4hi_ftype_v4qi);

No, they (and aligndata) can't be const as long as they're
affected by something other than their parameters (GSR); pure
yes but not const.  See extend.texi.


> +      def_builtin_const ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
> +			 ptr_ftype_ptr_di);
> +      def_builtin_const ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis,
> +			 ptr_ftype_ptr_di);

Can't be neither pure nor const; affects something global (GSR).

BTW, vector header files are overrated, at least when there's no
compiler compatibility expected.  They can even be in the way:
there's an ARM NEON PR being stalled because of concern that the
header could be used with another gcc version.  Bah. ...ok I see
visintrin.h is already in.  Never mind then. :)

brgds, H-P

Re: [PATCH] Add VIS intrinsics header for sparc.

[David Miller]

From: Hans-Peter Nilsson <hp@bitrange.com>
Date: Sat, 24 Sep 2011 17:15:06 -0400 (EDT)

> It's more of a parameter actually, GSR.scale_factor is the
> bit-shift count for the pack insns and GSR.alignaddr_offset the
> byte-shift in the aligndata insns.

I realize this.

> I'd prefer it as a parameter to the builtins (expanding to two
> insns, letting gcc get rid of the redundant ones; let the
> initialization value be 0).  I understand you're trying to keep
> some kind of compatibility there, but additional builtins would
> do the trick and fit nicely: the new builtins expanding to a set
> of GSR (GSR field) followed by the "old" insn but fixed as in
> this patch.  Besides, the functions that use GSR still can't be
> const in this patch.  I guess they never can, when you think of
> it, setting and/or using a register that can affect/be affected
> something elsewhere, when that something is known to gcc.  Oh well.

I read this idea in your PR before I did this work and I disagree that
this is a better approach, because then I have to assume that you care
about all the other bits in the %gsr register.

So on the first set I'd have to read it, mask it out, then set the
scale bits.  A needless waste of 20 to 30 cycles on UltraSPARC-III.

If you just call "__vis_write_gsr()" at the beginning of your kernel,
you can tell the compiler that you just want to set the scaling bits
and you don't care about the others at all.

> Another aspect would be to model the different GSR fields as
> different registers; they're used completely differently and
> just happen to be set with the same insn.  That might help gcc
> getting rid of redundant settings.

Again, this doesn't allow the user to say "don't care" about the other
fields like a plain "__vis_write_gsr(2<<3)" call does.

You know what fields actually matter for your code.

> FWIW not "need"; IIUC at least faligndata *can* be a vec_select
> of a vec_concat of the two vectors, but in practice I don't
> think gcc can make use of it yet and all ports use unspec...
> 
> While on faligndata, see vec_realign_load_<mode> (sadly
> undocumented at present); it'll enable the autovectorizer to...
> autovectorize some more.  (Right, I'm working on [yet] another
> SIMD back-end, implemented as MIPS COP2 insns.)

Thanks for these suggestions.

> How about putting it inside the unspec vector?  Those "use"
> thingies always gives me the creeps; outside of an insn (no, not
> here) they're sometimes lost and at least disconnected to the
> insn.  I think practically there's no difference here.

The canonical thing to do is to put them outside of the unspec
so that is what I have done.

> One more: please consider adding a
>  if (TARGET_VIS) builtin_define ("__VIS__=something") so I as a
> user theoretically wouldn't *have* to autoconfiscate for the
> changes. ;)

This is on my todo list as well, I'll try to emit some CPP define
compatible with what Sun uses.  But, thanks for reminding me.

>> +  def_builtin_const ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis,
>> +		     v4qi_ftype_v4hi);
>> +  def_builtin_const ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis,
>> +		     v8qi_ftype_v2si_v8qi);
>> +  def_builtin_const ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis,
>> +		     v2hi_ftype_v2si);
>>    def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis,
>>  		     v4hi_ftype_v4qi);
> 
> No, they (and aligndata) can't be const as long as they're
> affected by something other than their parameters (GSR); pure
> yes but not const.  See extend.texi.

Good catch, I was thinking purely on the RTL level where we do show
the compiler all of the "inputs" but at the tree level this is not
visible.

I'll fix that up for the next revision.

>> +      def_builtin_const ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis,
>> +			 ptr_ftype_ptr_di);
>> +      def_builtin_const ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis,
>> +			 ptr_ftype_ptr_di);
> 
> Can't be neither pure nor const; affects something global (GSR).

Gotcha.

I'd like to revisit this at some point in the future though, maybe we
can legitimately at least mark these things pure.

Re: [PATCH] Add VIS intrinsics header for sparc.

[Hans-Peter Nilsson]

On Sat, 24 Sep 2011, David Miller wrote:
> From: Hans-Peter Nilsson <hp@bitrange.com>
> Date: Sat, 24 Sep 2011 17:15:06 -0400 (EDT)
> > I'd prefer it as a parameter to the builtins (expanding to two
> > insns, letting gcc get rid of the redundant ones; let the
> > initialization value be 0).  I understand you're trying to keep
> > some kind of compatibility there, but additional builtins would
> > do the trick and fit nicely: the new builtins expanding to a set
> > of GSR (GSR field) followed by the "old" insn but fixed as in
> > this patch.  Besides, the functions that use GSR still can't be
> > const in this patch.  I guess they never can, when you think of
> > it, setting and/or using a register that can affect/be affected
> > something elsewhere, when that something is known to gcc.  Oh well.
>
> I read this idea in your PR before I did this work and I disagree that
> this is a better approach, because then I have to assume that you care
> about all the other bits in the %gsr register.

I don't understand what you mean here.  Maybe it doesn't
matter...  My suggestions come from observing what gcc did to
the "faked gsr modelling" I had to use with the current releases
(what moving and eliminating redundant variable settings used in
asms that it did; turned out acceptable FWIW, no redundant
reads), which would map directly to my suggestion.  But I guess
you have a point in that your setting-gsr-then-using-builtins
maps better to the machine insns.

BTW, don't forget to clobber GSR at call insns!

> So on the first set I'd have to read it, mask it out, then set the
> scale bits.  A needless waste of 20 to 30 cycles on UltraSPARC-III.

No, it doesn't have to be read.  If the fields have (useful)
implicit initial values (like scale=7 and align=4) at the
beginning of any function, you wouldn't have to read and mask,
just set.  (Caveat: the port has to have a way to emit a
gsr-setting even if the supposed-initial-values are specified -
like another register or variable, or the initial-value
machinery as I suggested.)

> If you just call "__vis_write_gsr()" at the beginning of your kernel,
> you can tell the compiler that you just want to set the scaling bits
> and you don't care about the others at all.

Don't care how?  They're certainly set by both __vis_write_gsr()
and alignaddr and used by faligndata.  I guess my confusion is
that I don't see what aspect is "don't care" here that'd be
"care" with my suggestion.

> > Another aspect would be to model the different GSR fields as
> > different registers; they're used completely differently and
> > just happen to be set with the same insn.  That might help gcc
> > getting rid of redundant settings.
>
> Again, this doesn't allow the user to say "don't care" about the other
> fields like a plain "__vis_write_gsr(2<<3)" call does.

But that'd set GSR.alignaddr_offset to 0 rather than "don't
care".

> You know what fields actually matter for your code.

A good reason to model them as different registers!

Still, this is a good start and much more workable (and
schedulable) than what's already there, thank you for that.
It doesn't add hurdles for a revisit, if the mechanism is found
unusable or the generated code pessimal!

brgds, H-P

Re: [PATCH] Add VIS intrinsics header for sparc.

[David Miller]

From: Hans-Peter Nilsson <hp@bitrange.com>
Date: Sat, 24 Sep 2011 18:37:33 -0400 (EDT)

> BTW, don't forget to clobber GSR at call insns!

This I explicitly want to avoid and is an explicit design decision.

Like I said the model is like setting the floating point rounding mode
for a family of functions.

You set the floating point rounding mode at the top level, run your
kernel and all the helper functions in that mode.

The %gsr scaling factor is to be used similarly.

You have to control all the functions that get called once you set the
%gsr before a calculation, and they either have to explicitly save and
restore the %gsr around changes to %gsr, or have been designed to use
the %gsr setting made by the callee.

The last thing I want to do is have to teach reload how to handle this
thing, it simply makes no sense to put that much engineering into it
if it is for zero or very little gain.

And it would explicitly prevent the kind of model I see as the most
reasonable for using this register, in that if we clobber it during
a call there is no way for the user to say not to save and restore
%gsr over a call.

>> So on the first set I'd have to read it, mask it out, then set the
>> scale bits.  A needless waste of 20 to 30 cycles on UltraSPARC-III.
> 
> No, it doesn't have to be read.  If the fields have (useful)
> implicit initial values (like scale=7 and align=4) at the
> beginning of any function, you wouldn't have to read and mask,
> just set.

You can't just set.  What about the VIS-2.0 byte-mask at the top
32-bits of the register, are you just going to clobber that when you
change the scale factor?

If we support treating the different fields as different registers we
have to preserve the setting of the other fields of %gsr when we
change one of them.  There are 5 fields currently defined:

1) align address <2:0>
2) scale factor <7:3>
3) interval rounding mode (VIS 2.0) <26:25>
4) interval mode enable <27>
5) Byte mask (VIS 2.0) <63:32>

And also this idea of using get_hard_reg_initial_val() to "optimize"
this kind of usage especially forces us to clobber the %gsr over
function calls which, as stated, I want to avoid if at all possible.

>> Again, this doesn't allow the user to say "don't care" about the other
>> fields like a plain "__vis_write_gsr(2<<3)" call does.
> 
> But that'd set GSR.alignaddr_offset to 0 rather than "don't
> care".

Zero is equivalent to "don't care" in this situation if either
1) you aren't doing any falignaddr operations or 2) you are
then going to subsequently do an "alignaddr" to set that field
up.

Look at the medialib code, that's basically the usage model there
and I think it's quite reasonable.

> It doesn't add hurdles for a revisit, if the mechanism is found
> unusable or the generated code pessimal!

Absolutely, thanks for your review.

Re: [PATCH] Add VIS intrinsics header for sparc.

[David Miller]

From: Hans-Peter Nilsson <hp@bitrange.com>
Date: Sat, 24 Sep 2011 19:32:55 -0400 (EDT)

> PS. gcc-4.7/changes.html?

Also on my TODO list, and Eric made some noise about documenting these
improvements as well, thanks for the reminder.

I'll post and commit the current version of my %gsr changes after my
bootstrap/testsuite run finishes.

Re: [PATCH] Add VIS intrinsics header for sparc.

[Hans-Peter Nilsson]

On Sat, 24 Sep 2011, David Miller wrote:

> From: Hans-Peter Nilsson <hp@bitrange.com>
> Date: Sat, 24 Sep 2011 18:37:33 -0400 (EDT)
>
> > BTW, don't forget to clobber GSR at call insns!
>
> This I explicitly want to avoid and is an explicit design decision.

Aha, now I get it; that's certainly key.  Thanks for taking the time.

Yes, it's certainly more flexible to have the user set GSR than
allowing gcc to clobber it when seeing VIS intrinsics, at the
minor usability cost of the user having to keep track of GSR
separately to when used in the individual intrinsics.

> Like I said the model is like setting the floating point rounding mode
> for a family of functions.

Aha 2: I didn't interpret what you wrote as referring to the
model; I thought you meant the actual function (one of the
usages of the fpack insns being "fixed math").  Sure.

> Zero is equivalent to "don't care" in this situation if either
> 1) you aren't doing any falignaddr operations or 2) you are

(JFTR, "faligndata")

> then going to subsequently do an "alignaddr" to set that field
> up.

brgds, H-P
PS. gcc-4.7/changes.html?

Re: [PATCH] Add VIS intrinsics header for sparc.

[David Miller]

From: David Miller <davem@davemloft.net>
Date: Sat, 24 Sep 2011 20:05:19 -0400 (EDT)

> From: Hans-Peter Nilsson <hp@bitrange.com>
> Date: Sat, 24 Sep 2011 19:32:55 -0400 (EDT)
> 
>> PS. gcc-4.7/changes.html?
> 
> Also on my TODO list, and Eric made some noise about documenting these
> improvements as well, thanks for the reminder.

I just commited an update to the wwwdocs.

Re: [PATCH] Add VIS intrinsics header for sparc.

[David Miller]

From: David Miller <davem@davemloft.net>
Date: Sat, 24 Sep 2011 02:08:32 -0400 (EDT)

> I'll look into your other suggestion in PR48974, namely making use of
> fone VIS instructions.

Hans, just FYI, here is a patch I am regression testing which
implements this.

diff --git a/gcc/config/sparc/constraints.md b/gcc/config/sparc/constraints.md
index cca34ed..317602c 100644
--- a/gcc/config/sparc/constraints.md
+++ b/gcc/config/sparc/constraints.md
@@ -18,7 +18,7 @@
 ;; <http://www.gnu.org/licenses/>.
 
 ;;; Unused letters:
-;;;    ABCD           P         Z
+;;;    AB                       
 ;;;    a        jkl    q  tuvwxyz
 
 
@@ -52,6 +52,10 @@
  (and (match_code "const_double")
       (match_test "const_zero_operand (op, mode)")))
 
+(define_constraint "C"
+ "The floating-point all-ones constant"
+ (and (match_code "const_double")
+      (match_test "const_all_ones_operand (op, mode)")))
 
 ;; Integer constant constraints
 
@@ -95,6 +99,10 @@
  (and (match_code "const_int")
       (match_test "ival == 4096")))
 
+(define_constraint "P"
+ "The integer constant -1"
+ (and (match_code "const_int")
+      (match_test "ival == -1")))
 
 ;; Extra constraints
 ;; Our memory extra constraints have to emulate the behavior of 'm' and 'o',
@@ -146,3 +154,8 @@
  "The vector zero constant"
  (and (match_code "const_vector")
       (match_test "const_zero_operand (op, mode)")))
+
+(define_constraint "Z"
+ "The vector all ones constant"
+ (and (match_code "const_vector")
+      (match_test "const_all_ones_operand (op, mode)")))
diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index 4af960a..21399b5 100644
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -29,6 +29,35 @@
   (and (match_code "const_int,const_double,const_vector")
        (match_test "op == CONST1_RTX (mode)")))
 
+;; Return true if the integer representation of OP is
+;; all-ones.
+(define_predicate "const_all_ones_operand"
+  (match_code "const_int,const_double,const_vector")
+{
+  if (GET_CODE (op) == CONST_INT && INTVAL (op) == -1)
+    return true;
+#if HOST_BITS_PER_WIDE_INT == 32
+  if (GET_CODE (op) == CONST_DOUBLE
+      && GET_MODE (op) == VOIDmode
+      && CONST_DOUBLE_HIGH (op) == ~(HOST_WIDE_INT)0
+      && CONST_DOUBLE_LOW (op) == ~(HOST_WIDE_INT)0)
+    return true;
+#endif
+  if (GET_CODE (op) == CONST_VECTOR)
+    {
+      int i, num_elem = CONST_VECTOR_NUNITS (op);
+
+      for (i = 0; i < num_elem; i++)
+        {
+          rtx n = CONST_VECTOR_ELT (op, i);
+          if (! const_all_ones_operand (n, mode))
+            return false;
+        }
+      return true;
+    }
+  return false;
+})
+
 ;; Return true if OP is the integer constant 4096.
 (define_predicate "const_4096_operand"
   (and (match_code "const_int")
@@ -211,6 +240,12 @@
   (ior (match_operand 0 "register_operand")
        (match_operand 0 "const_zero_operand")))
 
+;; Return true if OP is either the zero constant, the all-ones
+;; constant, or a register.
+(define_predicate "register_or_zero_or_all_ones_operand"
+  (ior (match_operand 0 "register_or_zero_operand")
+       (match_operand 0 "const_all_ones_operand")))
+
 ;; Return true if OP is a register operand in a floating point register.
 (define_predicate "fp_register_operand"
   (match_operand 0 "register_operand")
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index d648e87..3446379 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -1170,9 +1170,11 @@ sparc_expand_move (enum machine_mode mode, rtx *operands)
       if (operands [1] == const0_rtx)
 	operands[1] = CONST0_RTX (mode);
 
-      /* We can clear FP registers if TARGET_VIS, and always other regs.  */
+      /* We can clear or set to all-ones FP registers if TARGET_VIS, and
+	 always other regs.  */
       if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
-	  && const_zero_operand (operands[1], mode))
+	  && (const_zero_operand (operands[1], mode)
+	      || const_all_ones_operand (operands[1], mode)))
 	return false;
 
       if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
@@ -3096,19 +3098,21 @@ sparc_legitimate_constant_p (enum machine_mode mode, rtx x)
         return true;
 
       /* Floating point constants are generally not ok.
-	 The only exception is 0.0 in VIS.  */
+	 The only exception is 0.0 and all-ones in VIS.  */
       if (TARGET_VIS
 	  && SCALAR_FLOAT_MODE_P (mode)
-	  && const_zero_operand (x, mode))
+	  && (const_zero_operand (x, mode)
+	      || const_all_ones_operand (x, mode)))
 	return true;
 
       return false;
 
     case CONST_VECTOR:
       /* Vector constants are generally not ok.
-	 The only exception is 0 in VIS.  */
+	 The only exception is 0 or -1 in VIS.  */
       if (TARGET_VIS
-	  && const_zero_operand (x, mode))
+	  && (const_zero_operand (x, mode)
+	      || const_all_ones_operand (x, mode)))
 	return true;
 
       return false;
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index e5cf821..f830a39 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1303,10 +1303,10 @@
 })
 
 (define_insn "*movsi_insn"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,!f,!f,!m,d")
-	(match_operand:SI 1 "input_operand"   "rI,K,m,rJ,f,m,f,J"))]
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,!f,!f,!m,d,d")
+	(match_operand:SI 1 "input_operand"   "rI,K,m,rJ,f,m,f,J,P"))]
   "(register_operand (operands[0], SImode)
-    || register_or_zero_operand (operands[1], SImode))"
+    || register_or_zero_or_all_ones_operand (operands[1], SImode))"
   "@
    mov\t%1, %0
    sethi\t%%hi(%a1), %0
@@ -1315,8 +1315,9 @@
    fmovs\t%1, %0
    ld\t%1, %0
    st\t%1, %0
-   fzeros\t%0"
-  [(set_attr "type" "*,*,load,store,fpmove,fpload,fpstore,fga")])
+   fzeros\t%0
+   fones\t%0"
+  [(set_attr "type" "*,*,load,store,fpmove,fpload,fpstore,fga,fga")])
 
 (define_insn "*movsi_lo_sum"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1505,11 +1506,11 @@
    (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])
 
 (define_insn "*movdi_insn_sp64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m,?e,?e,?W,b")
-        (match_operand:DI 1 "input_operand"   "rI,N,m,rJ,e,W,e,J"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m,?e,?e,?W,b,b")
+        (match_operand:DI 1 "input_operand"   "rI,N,m,rJ,e,W,e,J,P"))]
   "TARGET_ARCH64
    && (register_operand (operands[0], DImode)
-       || register_or_zero_operand (operands[1], DImode))"
+       || register_or_zero_or_all_ones_operand (operands[1], DImode))"
   "@
    mov\t%1, %0
    sethi\t%%hi(%a1), %0
@@ -1518,9 +1519,10 @@
    fmovd\t%1, %0
    ldd\t%1, %0
    std\t%1, %0
-   fzero\t%0"
-  [(set_attr "type" "*,*,load,store,fpmove,fpload,fpstore,fga")
-   (set_attr "fptype" "*,*,*,*,double,*,*,double")])
+   fzero\t%0
+   fone\t%0"
+  [(set_attr "type" "*,*,load,store,fpmove,fpload,fpstore,fga,fga")
+   (set_attr "fptype" "*,*,*,*,double,*,*,double,double")])
 
 (define_expand "movdi_pic_label_ref"
   [(set (match_dup 3) (high:DI
@@ -1918,16 +1920,16 @@
 })
 
 (define_insn "*movsf_insn"
-  [(set (match_operand:V32 0 "nonimmediate_operand" "=d,f,*r,*r,*r,f,*r,m,m")
-	(match_operand:V32 1 "input_operand"        "GY,f,*rRY,Q,S,m,m,f,*rGY"))]
+  [(set (match_operand:V32 0 "nonimmediate_operand" "=d,d,f,*r,*r,*r,f,*r,m,m")
+	(match_operand:V32 1 "input_operand"        "GY,ZC,f,*rRY,Q,S,m,m,f,*rGY"))]
   "TARGET_FPU
    && (register_operand (operands[0], <V32:MODE>mode)
-       || register_or_zero_operand (operands[1], <V32:MODE>mode))"
+       || register_or_zero_or_all_ones_operand (operands[1], <V32:MODE>mode))"
 {
   if (GET_CODE (operands[1]) == CONST_DOUBLE
-      && (which_alternative == 2
-          || which_alternative == 3
-          || which_alternative == 4))
+      && (which_alternative == 3
+          || which_alternative == 4
+          || which_alternative == 5))
     {
       REAL_VALUE_TYPE r;
       long i;
@@ -1942,24 +1944,26 @@
     case 0:
       return "fzeros\t%0";
     case 1:
-      return "fmovs\t%1, %0";
+      return "fones\t%0";
     case 2:
-      return "mov\t%1, %0";
+      return "fmovs\t%1, %0";
     case 3:
-      return "sethi\t%%hi(%a1), %0";
+      return "mov\t%1, %0";
     case 4:
-      return "#";
+      return "sethi\t%%hi(%a1), %0";
     case 5:
+      return "#";
     case 6:
-      return "ld\t%1, %0";
     case 7:
+      return "ld\t%1, %0";
     case 8:
+    case 9:
       return "st\t%r1, %0";
     default:
       gcc_unreachable ();
     }
 }
-  [(set_attr "type" "fga,fpmove,*,*,*,fpload,load,fpstore,store")])
+  [(set_attr "type" "fga,fga,fpmove,*,*,*,fpload,load,fpstore,store")])
 
 ;; Exactly the same as above, except that all `f' cases are deleted.
 ;; This is necessary to prevent reload from ever trying to use a `f' reg
@@ -2091,15 +2095,16 @@
 
 ;; We have available v9 double floats but not 64-bit integer registers.
 (define_insn "*movdf_insn_sp32_v9"
-  [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,T,W,U,T,f,*r,o")
-        (match_operand:V64 1 "input_operand" "GY,e,W#F,GY,e,T,U,o#F,*roGYDF,*rGYf"))]
+  [(set (match_operand:V64 0 "nonimmediate_operand" "=b,b,e,e,T,W,U,T,f,*r,o")
+        (match_operand:V64 1 "input_operand" "GY,ZC,e,W#F,GY,e,T,U,o#F,*roGYDF,*rGYf"))]
   "TARGET_FPU
    && TARGET_V9
    && ! TARGET_ARCH64
    && (register_operand (operands[0], <V64:MODE>mode)
-       || register_or_zero_operand (operands[1], <V64:MODE>mode))"
+       || register_or_zero_or_all_ones_operand (operands[1], <V64:MODE>mode))"
   "@
   fzero\t%0
+  fone\t%0
   fmovd\t%1, %0
   ldd\t%1, %0
   stx\t%r1, %0
@@ -2109,9 +2114,9 @@
   #
   #
   #"
-  [(set_attr "type" "fga,fpmove,load,store,store,load,store,*,*,*")
-   (set_attr "length" "*,*,*,*,*,*,*,2,2,2")
-   (set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
+  [(set_attr "type" "fga,fga,fpmove,load,store,store,load,store,*,*,*")
+   (set_attr "length" "*,*,*,*,*,*,*,*,2,2,2")
+   (set_attr "fptype" "double,double,double,*,*,*,*,*,*,*,*")])
 
 (define_insn "*movdf_insn_sp32_v9_no_fpu"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
@@ -2132,14 +2137,15 @@
 
 ;; We have available both v9 double floats and 64-bit integer registers.
 (define_insn "*movdf_insn_sp64"
-  [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,W,*r,*r,m,*r")
-        (match_operand:V64 1 "input_operand"    "GY,e,W#F,e,*rGY,m,*rGY,DF"))]
+  [(set (match_operand:V64 0 "nonimmediate_operand" "=b,b,e,e,W,*r,*r,m,*r")
+        (match_operand:V64 1 "input_operand"    "GY,ZC,e,W#F,e,*rGY,m,*rGY,DF"))]
   "TARGET_FPU
    && TARGET_ARCH64
    && (register_operand (operands[0], <V64:MODE>mode)
-       || register_or_zero_operand (operands[1], <V64:MODE>mode))"
+       || register_or_zero_or_all_ones_operand (operands[1], <V64:MODE>mode))"
   "@
   fzero\t%0
+  fone\t%0
   fmovd\t%1, %0
   ldd\t%1, %0
   std\t%1, %0
@@ -2147,9 +2153,9 @@
   ldx\t%1, %0
   stx\t%r1, %0
   #"
-  [(set_attr "type" "fga,fpmove,load,store,*,load,store,*")
-   (set_attr "length" "*,*,*,*,*,*,*,2")
-   (set_attr "fptype" "double,double,*,*,*,*,*,*")])
+  [(set_attr "type" "fga,fga,fpmove,load,store,*,load,store,*")
+   (set_attr "length" "*,*,*,*,*,*,*,*,2")
+   (set_attr "fptype" "double,double,double,*,*,*,*,*,*")])
 
 (define_insn "*movdf_insn_sp64_no_fpu"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")

Re: [PATCH] Add VIS intrinsics header for sparc.

[David Miller]

From: David Miller <davem@davemloft.net>
Date: Sun, 25 Sep 2011 00:45:59 -0400 (EDT)

> From: David Miller <davem@davemloft.net>
> Date: Sat, 24 Sep 2011 02:08:32 -0400 (EDT)
> 
>> I'll look into your other suggestion in PR48974, namely making use of
>> fone VIS instructions.
> 
> Hans, just FYI, here is a patch I am regression testing which
> implements this.

It passed and I committed it to trunk.

For some reason I can't take ownership of your PR and mark it
closed, otherwise I'd do so as well.

I'll add a note about this to gcc-4.7/changes.html along with
the FMAF stuff I'm about to commit.

Re: [PATCH] Add VIS intrinsics header for sparc.

[Hans-Peter Nilsson]

On Sun, 25 Sep 2011, David Miller wrote:
> For some reason I can't take ownership of your PR and mark it
> closed, otherwise I'd do so as well.

Done, thanks.  The most common cause is not using your
gcc.gnu.org account in bugzilla, needed to get those
superpowers.  (For future reference, marking the ChangeLog with
the PR is helpful too.)  BTW, no test-cases.

brgds, H-P

Re: [PATCH] Add VIS intrinsics header for sparc.

[Gerald Pfeifer]

On Sun, 25 Sep 2011, David Miller wrote:
> I'll add a note about this to gcc-4.7/changes.html along with
> the FMAF stuff I'm about to commit.

Thanks for doing that, David.  I believe my automated tester has
naged you over a small markup issue in the patch which I am 
addressing thusly (together with some more markup).

Gerald

Index: changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.32
diff -u -r1.32 changes.html
--- changes.html	25 Sep 2011 22:39:05 -0000	1.32
+++ changes.html	25 Sep 2011 22:47:14 -0000
@@ -322,15 +322,16 @@
             operations.</li>
         <li>The compiler now properly tracks the <code>%gsr</code> register,
             and how it behaves as an input for various VIS instructions.</li>
-        <li>Akin to 'fzero', the compiler can now generate 'fone' instructions
-            in order to set all of the bits of a floating-point register to one.
+        <li>Akin to <code>fzero</code>, the compiler can now generate
+            <code>fone</code> instructions in order to set all of the bits
+            of a floating-point register to one.</li>
         <li>The documentation for the VIS intrinsics in the GCC manual has
             been brought up to date and many inaccuracies were fixed.</li>
       </ul>
     </li>
-    <li>Support for UltraSPARC Fused Multiply-Add Floating-point
+    <li>Support for UltraSPARC Fused Multiply-Add floating-point
         extensions has been added.  These instructions are enabled by
-        default on UltraSPARC T3 (Niagara 3) and later cpus.</li>
+        default on UltraSPARC T3 (Niagara 3) and later CPUs.</li>
   </ul>
 
 <h3 id="picochip">picochip</h3>
> 

Re: [PATCH] Add VIS intrinsics header for sparc.

[David Miller]

From: Gerald Pfeifer <gerald@pfeifer.com>
Date: Mon, 26 Sep 2011 00:50:22 +0200 (CEST)

> On Sun, 25 Sep 2011, David Miller wrote:
>> I'll add a note about this to gcc-4.7/changes.html along with
>> the FMAF stuff I'm about to commit.
> 
> Thanks for doing that, David.  I believe my automated tester has
> naged you over a small markup issue in the patch which I am 
> addressing thusly (together with some more markup).

Thanks a lot Gerald.

Re: [PATCH] Add VIS intrinsics header for sparc.

[David Miller]

From: David Miller <davem@davemloft.net>
Date: Sat, 24 Sep 2011 17:30:57 -0400 (EDT)

> From: Hans-Peter Nilsson <hp@bitrange.com>
> Date: Sat, 24 Sep 2011 17:15:06 -0400 (EDT)
> 
>> One more: please consider adding a
>>  if (TARGET_VIS) builtin_define ("__VIS__=something") so I as a
>> user theoretically wouldn't *have* to autoconfiscate for the
>> changes. ;)
> 
> This is on my todo list as well, I'll try to emit some CPP define
> compatible with what Sun uses.  But, thanks for reminding me.

Hans, I just committed the following regstrapped patch to the trunk.

--------------------
Move target CPP macro handling to C file and add __VIS/__VIS__.

	* config/sparc/sparc-c.c: New file implementing sparc_target_macros,
	which will now define __VIS and __VIS__ when -mvis is enabled.
	* config/sparc/t-sparc: Likewise.
	* config.gcc: Add sparc-c.o to c_target_objs and cxx_target_objs,
	and add t-sparc to tmake_file for all sparc targets.
	* config/sparc/sparc-protos.h (sparc_target_macros): Declare.
	* config/sparc/sparc.h (TARGE_CPU_CPP_BUILTINS): Call it.
---
 gcc/ChangeLog                   |   10 +++++++
 gcc/config.gcc                  |   30 +++++++++++++---------
 gcc/config/sparc/sparc-c.c      |   53 +++++++++++++++++++++++++++++++++++++++
 gcc/config/sparc/sparc-protos.h |    1 +
 gcc/config/sparc/sparc.h        |   20 +--------------
 gcc/config/sparc/t-sparc        |   36 ++++++++++++++++++++++++++
 6 files changed, 119 insertions(+), 31 deletions(-)
 create mode 100644 gcc/config/sparc/sparc-c.c
 create mode 100644 gcc/config/sparc/t-sparc

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 71a8d88..309eca5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2011-09-26  David S. Miller  <davem@davemloft.net>
+
+	* config/sparc/sparc-c.c: New file implementing sparc_target_macros,
+	which will now define __VIS and __VIS__ when -mvis is enabled.
+	* config/sparc/t-sparc: Likewise.
+	* config.gcc: Add sparc-c.o to c_target_objs and cxx_target_objs,
+	and add t-sparc to tmake_file for all sparc targets.
+	* config/sparc/sparc-protos.h (sparc_target_macros): Declare.
+	* config/sparc/sparc.h (TARGE_CPU_CPP_BUILTINS): Call it.
+
 2011-09-26  Georg-Johann Lay  <avr@gjlay.de>
 
 	* config/avr/avr.md (peephole casesi+2): Use -1 instead of 65536.
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7183f26..cf11364 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -422,6 +422,8 @@ score*-*-*)
 	;;
 sparc*-*-*)
 	cpu_type=sparc
+	c_target_objs="sparc-c.o"
+	cxx_target_objs="sparc-c.o"
 	extra_headers="visintrin.h"
 	need_64bit_hwint=yes
 	;;
@@ -2457,32 +2459,32 @@ sparc-*-elf*)
 	tm_file="${tm_file} dbxelf.h elfos.h newlib-stdint.h sparc/sysv4.h sparc/sp-elf.h"
 	case ${target} in
 	    *-leon-*)
-		tmake_file="sparc/t-leon"
+		tmake_file="sparc/t-sparc sparc/t-leon"
 		;;
 	    *-leon[3-9]*)
-		tmake_file="sparc/t-leon3"
+		tmake_file="sparc/t-sparc sparc/t-leon3"
 		;;
 	    *)
-		tmake_file="sparc/t-elf"
+		tmake_file="sparc/t-sparc sparc/t-elf"
 		;;
 	esac
 	;;
 sparc-*-rtems*)
 	tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h sparc/sp-elf.h sparc/rtemself.h rtems.h newlib-stdint.h"
-	tmake_file="sparc/t-elf t-rtems"
+	tmake_file="sparc/t-sparc sparc/t-elf t-rtems"
 	;;
 sparc-*-linux*)
 	tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h"
 	extra_options="${extra_options} sparc/long-double-switch.opt"
 	case ${target} in
 	    *-leon-*)
-		tmake_file="${tmake_file} sparc/t-leon"
+		tmake_file="${tmake_file} sparc/t-sparc sparc/t-leon"
 		;;
 	    *-leon[3-9]*)
-		tmake_file="${tmake_file} sparc/t-leon3"
+		tmake_file="${tmake_file} sparc/t-sparc sparc/t-leon3"
 		;;
 	    *)
-		tmake_file="${tmake_file} sparc/t-linux"
+		tmake_file="${tmake_file} sparc/t-sparc sparc/t-linux"
 		;;
 	esac
 	if test x$enable_targets = xall; then
@@ -2497,6 +2499,7 @@ sparc-*-netbsdelf*)
 	tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h netbsd.h netbsd-elf.h sparc/netbsd-elf.h"
 	extra_options="${extra_options} netbsd.opt netbsd-elf.opt"
 	extra_options="${extra_options} sparc/long-double-switch.opt"
+	tmake_file="${tmake_file} sparc/t-sparc"
 	;;
 sparc*-*-solaris2*)
 	tm_file="sparc/biarch64.h ${tm_file} ${sol2_tm_file} sol2-bi.h"
@@ -2508,25 +2511,26 @@ sparc*-*-solaris2*)
 		test x$with_cpu != x || with_cpu=v9
 		;;
 	esac
-	tmake_file="${tmake_file} sparc/t-sol2-64"
+	tmake_file="${tmake_file} sparc/t-sparc sparc/t-sol2-64"
 	;;
 sparc-wrs-vxworks)
 	tm_file="${tm_file} elfos.h sparc/sysv4.h vx-common.h vxworks.h sparc/vxworks.h"
-	tmake_file="${tmake_file} sparc/t-vxworks"
+	tmake_file="${tmake_file} sparc/t-sparc sparc/t-vxworks"
 	;;
 sparc64-*-elf*)
 	tm_file="${tm_file} dbxelf.h elfos.h newlib-stdint.h sparc/sysv4.h sparc/sp64-elf.h"
 	extra_options="${extra_options} sparc/little-endian.opt"
+	tmake_file="${tmake_file} sparc/t-sparc"
 	;;
 sparc64-*-rtems*)
 	tm_file="${tm_file} dbxelf.h elfos.h newlib-stdint.h sparc/sysv4.h sparc/sp64-elf.h sparc/rtemself.h rtems.h"
 	extra_options="${extra_options} sparc/little-endian.opt"
-	tmake_file="${tmake_file} t-rtems"
+	tmake_file="${tmake_file} sparc/t-sparc t-rtems"
 	;;
 sparc64-*-linux*)
 	tm_file="sparc/biarch64.h ${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h sparc/default-64.h sparc/linux64.h"
 	extra_options="${extra_options} sparc/long-double-switch.opt"
-	tmake_file="${tmake_file} sparc/t-linux sparc/t-linux64"
+	tmake_file="${tmake_file} sparc/t-sparc sparc/t-linux sparc/t-linux64"
 	extra_parts="${extra_parts} crtfastmath.o"
 	;;
 sparc64-*-freebsd*|ultrasparc-*-freebsd*)
@@ -2538,13 +2542,14 @@ sparc64-*-freebsd*|ultrasparc-*-freebsd*)
 		*) echo "$with_cpu not supported for freebsd target"; exit 1 ;;
 	esac
 	extra_parts="${extra_parts} crtfastmath.o"
+	tmake_file="${tmake_file} sparc/t-sparc"
 	;;
 sparc64-*-netbsd*)
 	tm_file="sparc/biarch64.h ${tm_file}"
 	tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h netbsd.h netbsd-elf.h sparc/netbsd-elf.h"
 	extra_options="${extra_options} netbsd.opt netbsd-elf.opt"
 	extra_options="${extra_options} sparc/long-double-switch.opt"
-	tmake_file="${tmake_file} sparc/t-netbsd64"
+	tmake_file="${tmake_file} sparc/t-sparc sparc/t-netbsd64"
 	;;
 sparc64-*-openbsd*)
 	tm_file="sparc/openbsd1-64.h ${tm_file} dbxelf.h elfos.h sparc/sysv4.h sparc/sp64-elf.h"
@@ -2553,6 +2558,7 @@ sparc64-*-openbsd*)
 	extra_options="${extra_options} sparc/little-endian.opt"
 	gas=yes gnu_ld=yes
 	with_cpu=ultrasparc
+	tmake_file="${tmake_file} sparc/t-sparc"
 	;;
 spu-*-elf*)
 	tm_file="dbxelf.h elfos.h spu/spu-elf.h spu/spu.h newlib-stdint.h"
diff --git a/gcc/config/sparc/sparc-c.c b/gcc/config/sparc/sparc-c.c
new file mode 100644
index 0000000..6e30950
--- /dev/null
+++ b/gcc/config/sparc/sparc-c.c
@@ -0,0 +1,53 @@
+/* Subroutines used for macro/preprocessor support on SPARC.
+   Copyright (C) 2011
+   Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "tm_p.h"
+#include "flags.h"
+#include "c-family/c-common.h"
+#include "c-family/c-pragma.h"
+#include "cpplib.h"
+
+void
+sparc_target_macros (void)
+{
+  builtin_define_std ("sparc");
+
+  if (TARGET_64BIT)
+    {
+      cpp_assert (parse_in, "cpu=sparc64");
+      cpp_assert (parse_in, "machine=sparc64");
+    }
+  else
+    {
+      cpp_assert (parse_in, "cpu=sparc");
+      cpp_assert (parse_in, "machine=sparc");
+    }
+
+  if (TARGET_VIS)
+    {
+      cpp_define (parse_in, "__VIS__=0x100");
+      cpp_define (parse_in, "__VIS=0x100");
+    }
+}
diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h
index a5e2587..dfa461a 100644
--- a/gcc/config/sparc/sparc-protos.h
+++ b/gcc/config/sparc/sparc-protos.h
@@ -47,6 +47,7 @@ extern int short_branch (int, int);
 extern void sparc_profile_hook (int);
 extern void sparc_override_options (void);
 extern void sparc_output_scratch_registers (FILE *);
+extern void sparc_target_macros (void);
 
 #ifdef RTX_CODE
 extern enum machine_mode select_cc_mode (enum rtx_code, rtx, rtx);
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index ad1e0ef..cccd444 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -105,25 +105,7 @@ struct processor_costs {
 
 extern const struct processor_costs *sparc_costs;
 
-/* Target CPU builtins.  FIXME: Defining sparc is for the benefit of
-   Solaris only; otherwise just define __sparc__.  Sadly the headers
-   are such a mess there is no Solaris-specific header.  */
-#define TARGET_CPU_CPP_BUILTINS()		\
-  do						\
-    {						\
-	builtin_define_std ("sparc");		\
-	if (TARGET_64BIT)			\
-	  { 					\
-	    builtin_assert ("cpu=sparc64");	\
-	    builtin_assert ("machine=sparc64");	\
-	  }					\
-	else					\
-	  { 					\
-	    builtin_assert ("cpu=sparc");	\
-	    builtin_assert ("machine=sparc");	\
-	  }					\
-    }						\
-  while (0)
+#define TARGET_CPU_CPP_BUILTINS() sparc_target_macros ()
 
 /* Specify this in a cover file to provide bi-architecture (32/64) support.  */
 /* #define SPARC_BI_ARCH */
diff --git a/gcc/config/sparc/t-sparc b/gcc/config/sparc/t-sparc
new file mode 100644
index 0000000..ea9d0e8
--- /dev/null
+++ b/gcc/config/sparc/t-sparc
@@ -0,0 +1,36 @@
+# General rules that all sparc/ targets must have.
+#
+# Copyright (C) 2011 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+sparc.o: $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
+  $(TREE_H) $(RTL_H) $(REGS_H) hard-reg-set.h insn-config.h  \
+  insn-codes.h conditions.h output.h $(INSN_ATTR_H) $(FLAGS_H) \
+  $(FUNCTION_H) $(EXCEPT_H) $(EXPR_H) $(OPTABS_H) $(RECOG_H) \
+  $(DIAGNOSTIC_CORE_H) $(GGC_H) $(TM_P_H) debug.h $(TARGET_H) \
+  $(TARGET_DEF_H) $(COMMON_TARGET_H) $(CFGLAYOUT_H) $(GIMPLE_H) \
+  langhooks.h reload.h $(PARAMS_H) $(DF_H) dwarf2out.h $(OPTS_H) \
+  gt-sparc.h
+
+sparc-c.o: $(srcdir)/config/sparc/sparc-c.c \
+    $(srcdir)/config/sparc/sparc-protos.h \
+    $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) $(FLAGS_H) \
+    $(TM_P_H) coretypes.h $(TM_H) $(TREE_H) \
+    $(C_COMMON_H) $(C_PRAGMA_H)
+	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
+		$(srcdir)/config/sparc/sparc-c.c
-- 
1.7.6.401.g6a319