From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 5417 invoked by alias); 12 Oct 2011 18:26:13 -0000 Received: (qmail 5407 invoked by uid 22791); 12 Oct 2011 18:26:10 -0000 X-SWARE-Spam-Status: No, hits=-6.8 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,SPF_HELO_PASS,TW_ZJ X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 12 Oct 2011 18:25:50 +0000 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p9CIPoXO023649 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 12 Oct 2011 14:25:50 -0400 Received: from tyan-ft48-01.lab.bos.redhat.com (tyan-ft48-01.lab.bos.redhat.com [10.16.42.4]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p9CIPmEL025410 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 12 Oct 2011 14:25:49 -0400 Received: from tyan-ft48-01.lab.bos.redhat.com (tyan-ft48-01.lab.bos.redhat.com [127.0.0.1]) by tyan-ft48-01.lab.bos.redhat.com (8.14.4/8.14.4) with ESMTP id p9CIPmQQ008331; Wed, 12 Oct 2011 20:25:48 +0200 Received: (from jakub@localhost) by tyan-ft48-01.lab.bos.redhat.com (8.14.4/8.14.4/Submit) id p9CIPlsq008329; Wed, 12 Oct 2011 20:25:47 +0200 Date: Wed, 12 Oct 2011 19:16:00 -0000 From: Jakub Jelinek To: Richard Henderson , Uros Bizjak Cc: gcc-patches@gcc.gnu.org Subject: [PATCH] Slightly fix up vgather* patterns (take 2) Message-ID: <20111012182547.GF2210@tyan-ft48-01.lab.bos.redhat.com> Reply-To: Jakub Jelinek References: <20111008154322.GQ19412@tyan-ft48-01.lab.bos.redhat.com> <4E9359F5.5030609@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4E9359F5.5030609@redhat.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-10/txt/msg01024.txt.bz2 On Sun, Oct 09, 2011 at 12:55:40PM +0200, Uros Bizjak wrote: > BTW: No need to use %c modifier: > > /* Meaning of CODE: > L,W,B,Q,S,T -- print the opcode suffix for specified size of operand. > C -- print opcode suffix for set/cmov insn. > c -- like C, but print reversed condition > ... > */ Well, something needs to be used there, because otherwise we get addresses like (%rax, %ymm0, $4) instead of the needed (%rax, %ymm0, 4) I've used %p6 instead of %c6 in the patch below. On Mon, Oct 10, 2011 at 01:47:49PM -0700, Richard Henderson wrote: > The use of match_dup in the clobber is wrong. We should not be > clobbering the user-visible copy of the operand. That does not > make sense when dealing with the user-visible builtin. Ok. > Instead, use (clobber (match_scratch)) and matching constraints with operand 4. Ok. > I think that a (mem (scratch)) as input to the unspec is probably best. > The exact memory usage is almost certainly too complex to describe > in a useful way. Ok, so how about this (so far untested, will bootstrap/regtest it soon)? 2011-10-12 Jakub Jelinek * config/i386/sse.md (avx2_gathersi, avx2_gatherdi, avx2_gatherdi256): Add clobber of match_scratch, change memory_operand to register_operand, add (mem:BLK (scratch)) use. (*avx2_gathersi, *avx2_gatherdi, *avx2_gatherdi256): Add clobber of match_scratch, add earlyclobber to the output operand and match_scratch, add (mem:BLK (scratch)) use, change the other mem to match_operand. Use %p6 instead of %c6 in the pattern. * config/i386/i386.c (ix86_expand_builtin): Adjust for operand 2 being a Pmode register_operand instead of memory_operand. --- gcc/config/i386/i386.c.jj 2011-10-12 16:15:50.000000000 +0200 +++ gcc/config/i386/i386.c 2011-10-12 19:12:15.000000000 +0200 @@ -28862,7 +28862,6 @@ rdrand_step: op4 = expand_normal (arg4); /* Note the arg order is different from the operand order. */ mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; mode2 = insn_data[icode].operand[3].mode; mode3 = insn_data[icode].operand[4].mode; mode4 = insn_data[icode].operand[5].mode; @@ -28876,12 +28875,11 @@ rdrand_step: if (GET_MODE (op1) != Pmode) op1 = convert_to_mode (Pmode, op1, 1); op1 = force_reg (Pmode, op1); - op1 = gen_rtx_MEM (mode1, op1); if (!insn_data[icode].operand[1].predicate (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); - if (!insn_data[icode].operand[2].predicate (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); + if (!insn_data[icode].operand[2].predicate (op1, Pmode)) + op1 = copy_to_mode_reg (Pmode, op1); if (!insn_data[icode].operand[3].predicate (op2, mode2)) op2 = copy_to_mode_reg (mode2, op2); if (!insn_data[icode].operand[4].predicate (op3, mode3)) --- gcc/config/i386/sse.md.jj 2011-10-12 16:16:49.000000000 +0200 +++ gcc/config/i386/sse.md 2011-10-12 19:19:55.000000000 +0200 @@ -12582,55 +12582,61 @@ (define_mode_attr VEC_GATHER_MODE (V8SI "V8SI") (V8SF "V8SI")]) (define_expand "avx2_gathersi" - [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "") - (unspec:VEC_GATHER_MODE - [(match_operand:VEC_GATHER_MODE 1 "register_operand" "") - (match_operand: 2 "memory_operand" "") - (match_operand: 3 "register_operand" "") - (match_operand:VEC_GATHER_MODE 4 "register_operand" "") - (match_operand:SI 5 "const1248_operand " "")] - UNSPEC_GATHER))] + [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "") + (unspec:VEC_GATHER_MODE + [(match_operand:VEC_GATHER_MODE 1 "register_operand" "") + (match_operand 2 "register_operand" "") + (mem:BLK (scratch)) + (match_operand: 3 "register_operand" "") + (match_operand:VEC_GATHER_MODE 4 "register_operand" "") + (match_operand:SI 5 "const1248_operand " "")] + UNSPEC_GATHER)) + (clobber (match_scratch:VEC_GATHER_MODE 6 ""))])] "TARGET_AVX2") (define_insn "*avx2_gathersi" - [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=x") + [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x") (unspec:VEC_GATHER_MODE - [(match_operand:VEC_GATHER_MODE 1 "register_operand" "0") - (mem: - (match_operand:P 2 "register_operand" "r")) - (match_operand: 3 "register_operand" "x") - (match_operand:VEC_GATHER_MODE 4 "register_operand" "x") - (match_operand:SI 5 "const1248_operand" "n")] - UNSPEC_GATHER))] + [(match_operand:VEC_GATHER_MODE 2 "register_operand" "0") + (match_operand:P 3 "register_operand" "r") + (mem:BLK (scratch)) + (match_operand: 4 "register_operand" "x") + (match_operand:VEC_GATHER_MODE 5 "register_operand" "1") + (match_operand:SI 6 "const1248_operand" "n")] + UNSPEC_GATHER)) + (clobber (match_scratch:VEC_GATHER_MODE 1 "=&x"))] "TARGET_AVX2" - "vgatherd\t{%4, (%2, %3, %c5), %0|%0, (%2, %3, %c5), %4}" + "vgatherd\t{%1, (%3, %4, %p6), %0|%0, (%3, %4, %p6), %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "vex") (set_attr "mode" "")]) (define_expand "avx2_gatherdi" - [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "") - (unspec:VEC_GATHER_MODE - [(match_operand:VEC_GATHER_MODE 1 "register_operand" "") - (match_operand: 2 "memory_operand" "") - (match_operand: 3 "register_operand" "") - (match_operand:VEC_GATHER_MODE 4 "register_operand" "") - (match_operand:SI 5 "const1248_operand " "")] - UNSPEC_GATHER))] + [(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "") + (unspec:VEC_GATHER_MODE + [(match_operand:VEC_GATHER_MODE 1 "register_operand" "") + (match_operand 2 "register_operand" "") + (mem:BLK (scratch)) + (match_operand: 3 "register_operand" "") + (match_operand:VEC_GATHER_MODE 4 "register_operand" "") + (match_operand:SI 5 "const1248_operand " "")] + UNSPEC_GATHER)) + (clobber (match_scratch:VEC_GATHER_MODE 6 ""))])] "TARGET_AVX2") (define_insn "*avx2_gatherdi" - [(set (match_operand:AVXMODE48P_DI 0 "register_operand" "=x") + [(set (match_operand:AVXMODE48P_DI 0 "register_operand" "=&x") (unspec:AVXMODE48P_DI - [(match_operand:AVXMODE48P_DI 1 "register_operand" "0") - (mem: - (match_operand:P 2 "register_operand" "r")) - (match_operand: 3 "register_operand" "x") - (match_operand:AVXMODE48P_DI 4 "register_operand" "x") - (match_operand:SI 5 "const1248_operand" "n")] - UNSPEC_GATHER))] + [(match_operand:AVXMODE48P_DI 2 "register_operand" "0") + (match_operand:P 3 "register_operand" "r") + (mem:BLK (scratch)) + (match_operand: 4 "register_operand" "x") + (match_operand:AVXMODE48P_DI 5 "register_operand" "1") + (match_operand:SI 6 "const1248_operand" "n")] + UNSPEC_GATHER)) + (clobber (match_scratch:AVXMODE48P_DI 1 "=&x"))] "TARGET_AVX2" - "vgatherq\t{%4, (%2, %3, %c5), %0|%0, (%2, %3, %c5), %4}" + "vgatherq\t{%1, (%3, %4, %p6), %0|%0, (%3, %4, %p6), %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -12638,28 +12644,31 @@ (define_insn "*avx2_gatherdi" ;; Special handling for VEX.256 with float arguments ;; since there're still xmms as operands (define_expand "avx2_gatherdi256" - [(set (match_operand:VI4F_128 0 "register_operand" "") - (unspec:VI4F_128 - [(match_operand:VI4F_128 1 "register_operand" "") - (match_operand: 2 "memory_operand" "") - (match_operand:V4DI 3 "register_operand" "") - (match_operand:VI4F_128 4 "register_operand" "") - (match_operand:SI 5 "const1248_operand " "")] - UNSPEC_GATHER))] + [(parallel [(set (match_operand:VI4F_128 0 "register_operand" "") + (unspec:VI4F_128 + [(match_operand:VI4F_128 1 "register_operand" "") + (match_operand 2 "register_operand" "") + (mem:BLK (scratch)) + (match_operand:V4DI 3 "register_operand" "") + (match_operand:VI4F_128 4 "register_operand" "") + (match_operand:SI 5 "const1248_operand " "")] + UNSPEC_GATHER)) + (clobber (match_scratch:VI4F_128 6 ""))])] "TARGET_AVX2") (define_insn "*avx2_gatherdi256" [(set (match_operand:VI4F_128 0 "register_operand" "=x") (unspec:VI4F_128 - [(match_operand:VI4F_128 1 "register_operand" "0") - (mem: - (match_operand:P 2 "register_operand" "r")) - (match_operand:V4DI 3 "register_operand" "x") - (match_operand:VI4F_128 4 "register_operand" "x") - (match_operand:SI 5 "const1248_operand" "n")] - UNSPEC_GATHER))] + [(match_operand:VI4F_128 2 "register_operand" "0") + (match_operand:P 3 "register_operand" "r") + (mem:BLK (scratch)) + (match_operand:V4DI 4 "register_operand" "x") + (match_operand:VI4F_128 5 "register_operand" "1") + (match_operand:SI 6 "const1248_operand" "n")] + UNSPEC_GATHER)) + (clobber (match_scratch:VI4F_128 1 "=&x"))] "TARGET_AVX2" - "vgatherq\t{%4, (%2, %3, %c5), %0|%0, (%2, %3, %c5), %4}" + "vgatherq\t{%1, (%3, %4, %p6), %0|%0, (%3, %4, %p6), %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "vex") (set_attr "mode" "")]) Jakub