[PATCH] Add missing fzero/fone cases to DImode move on 32-bit v9 sparc.

[PATCH] Add missing fzero/fone cases to DImode move on 32-bit v9 sparc.

[David Miller]

A good example of a case where this matters is pdist.c in the testsuite.
Before this change we get code for the beginning of function 'foo' like:

        add     %sp, -112, %sp
	std     %o0, [%sp+96]
        stx     %g0, [%sp+104]
        ldd     [%sp+96], %f10
        std     %o2, [%sp+96]
        ldd     [%sp+104], %f8
	ldd     [%sp+96], %f12
	pdist   %f10, %f12, %f8

now it will look like:

        add     %sp, -88, %sp
	fzero   %f8
        std     %o0, [%sp+72]
        ldd     [%sp+72], %f10
        std     %o2, [%sp+72]
        ldd     [%sp+72], %f12
	pdist   %f10, %f12, %f8

And it will get a lot better when the VIS3 moves are available.

Now that we've added this case, we have to make sure the DI mode
const_int --> reg splitter doesn't trigger for float regs.

Committed to trunk.

gcc/

	* config/sparc/sparc.md (*movdi_insn_sp32_v9): Add alternatives for
	generating fzero and fone instructions.
	(DImode const_int --> reg splitter): Only trigger for integer regs.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@180352 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog             |    4 ++++
 gcc/config/sparc/sparc.md |   22 +++++++++++++++-------
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3dc4ba9..be79367 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
 2011-10-23  David S. Miller  <davem@davemloft.net>
 
+	* config/sparc/sparc.md (*movdi_insn_sp32_v9): Add alternatives for
+	generating fzero and fone instructions.
+	(DImode const_int --> reg splitter): Only trigger for integer regs.
+
 	* config/sparc/predicates.md (input_operand): Disallow vector
 	constants other than 0 and -1.
 	* config/sparc/sparc.c (sparc_preferred_reload_class): Return
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index c6454f5..fa27bba 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1488,9 +1488,9 @@
 
 (define_insn "*movdi_insn_sp32_v9"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-					"=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?e,?e,?W")
+					"=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?e,?e,?W,b,b")
         (match_operand:DI 1 "input_operand"
-					" J,J,U,T,r,o,i,r, f, T, o, f, e, W, e"))]
+					" J,J,U,T,r,o,i,r, f, T, o, f, e, W, e,J,P"))]
   "! TARGET_ARCH64
    && TARGET_V9
    && (register_operand (operands[0], DImode)
@@ -1510,10 +1510,12 @@
    #
    fmovd\\t%1, %0
    ldd\\t%1, %0
-   std\\t%1, %0"
-  [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,fpload,fpstore")
-   (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,*,*")
-   (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])
+   std\\t%1, %0
+   fzero\t%0
+   fone\t%0"
+  [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,fpload,fpstore,fga,fga")
+   (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,*,*,*,*")
+   (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*,double,double")])
 
 (define_insn "*movdi_insn_sp64"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m,?e,?e,?W,b,b")
@@ -1757,7 +1759,13 @@
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
         (match_operand:DI 1 "const_int_operand" ""))]
-  "! TARGET_ARCH64 && reload_completed"
+  "! TARGET_ARCH64
+   && ((GET_CODE (operands[0]) == REG
+        && SPARC_INT_REG_P (REGNO (operands[0])))
+       || (GET_CODE (operands[0]) == SUBREG
+           && GET_CODE (SUBREG_REG (operands[0])) == REG
+           && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))
+   && reload_completed"
   [(clobber (const_int 0))]
 {
 #if HOST_BITS_PER_WIDE_INT == 32
-- 
1.7.6.401.g6a319