From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14165 invoked by alias); 30 Jul 2012 15:40:45 -0000 Received: (qmail 14156 invoked by uid 22791); 30 Jul 2012 15:40:43 -0000 X-SWARE-Spam-Status: No, hits=-4.1 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,KHOP_THREADED,MSGID_FROM_MTA_HEADER,RCVD_IN_HOSTKARMA_W,RCVD_IN_HOSTKARMA_WL,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from e06smtp17.uk.ibm.com (HELO e06smtp17.uk.ibm.com) (195.75.94.113) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 30 Jul 2012 15:40:30 +0000 Received: from /spool/local by e06smtp17.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 30 Jul 2012 16:40:29 +0100 Received: from d06nrmr1507.portsmouth.uk.ibm.com (9.149.38.233) by e06smtp17.uk.ibm.com (192.168.101.147) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Mon, 30 Jul 2012 16:40:05 +0100 Received: from d06av02.portsmouth.uk.ibm.com (d06av02.portsmouth.uk.ibm.com [9.149.37.228]) by d06nrmr1507.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q6UFe5983018998 for ; Mon, 30 Jul 2012 16:40:05 +0100 Received: from d06av02.portsmouth.uk.ibm.com (loopback [127.0.0.1]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q6UFe4CN027432 for ; Mon, 30 Jul 2012 09:40:04 -0600 Received: from tuxmaker.boeblingen.de.ibm.com (tuxmaker.boeblingen.de.ibm.com [9.152.85.9]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with SMTP id q6UFe3tk027386; Mon, 30 Jul 2012 09:40:03 -0600 Message-Id: <201207301540.q6UFe3tk027386@d06av02.portsmouth.uk.ibm.com> Received: by tuxmaker.boeblingen.de.ibm.com (sSMTP sendmail emulation); Mon, 30 Jul 2012 17:40:03 +0200 Subject: Re: [CFT] s390: Convert from sync to atomic optabs To: rth@redhat.com (Richard Henderson) Date: Mon, 30 Jul 2012 15:51:00 -0000 From: "Ulrich Weigand" Cc: Andreas.Krebbel@de.ibm.com, gcc-patches@gcc.gnu.org In-Reply-To: <5016A2E4.1050705@redhat.com> from "Richard Henderson" at Jul 30, 2012 08:06:12 AM MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit x-cbid: 12073015-0542-0000-0000-0000029AF1A7 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2012-07/txt/msg01501.txt.bz2 Richard Henderson wrote: > On 2012-07-30 07:09, Ulrich Weigand wrote: > > This seems to disable use of ICM / STCM to perform byte or > > aligned halfword access. Why is this necessary? Those operations > > are supposed to provide the required operand consistency ... > > Because MEM_P for cmp and new_rtx are always false. The expander > always requests register_operand for those. I suppose I could back > out merging those cases into the macro. Right, that's one of the reasons why we had two separate macros for sync_compare_and_swap ... > I presume a good test case to examine for ICM is with such an operand > coming from a global. What about STCM? I don't see the output from > sync_compare_and_swap ever being allowed in memory... Actually, it's only ICM that is of interest here; it should get used when either the comparison value or the "new" value come from a memory location, e.g. a global. Sorry, I was confused about STCM ... > > This seems to force DImode accesses through floating-point > > registers, which is quite inefficient. Why not allow LM/STM? > > Those are supposed to provide doubleword consistency if the > > operand is sufficiently aligned ... > > ... because I only looked at the definition of LM which itself > doesn't mention consistency, and the definition of LPQ which talks > about LM not being suitable for quadword consistency, and came to > the wrong conclusion. > > So now, looking at movdi_31, I see two problems that prevent just > using a "normal" move for the atomic_load/store_di: the o/d and d/b > alternatives which are split. Is there some specific goodness that > those alternatives provide that is not had by reloading into the > Q/S memory patterns? Well, they are there as splitters because reload assumes all moves are handled somewhere, either by the mov pattern or else via a secondary reload. I've implemented all moves that *can* be implemented without an extra register via splitters on the mov pattern, and only those that absolute require the extra register via secondary reload ... Given that, it's probably best to use a separate instruction for the DImode atomic moves after all, but allow GPRs using LM/STM. (Only for Q/S constraint type addresses. For those instructions, we have to reload the address instead of performing two moves.) Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE Ulrich.Weigand@de.ibm.com