Index: gcc/config/rs6000/aix53.h
===================================================================
--- gcc/config/rs6000/aix53.h	(revision 191458)
+++ gcc/config/rs6000/aix53.h	(working copy)
@@ -26,7 +26,7 @@
 do {									\
   if (TARGET_64BIT && ! TARGET_POWERPC64)				\
     {									\
-      target_flags |= MASK_POWERPC64;					\
+      rs6000_isa_flags |= OPTION_MASK_POWERPC64;			\
       warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
     }									\
   if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128)			\
Index: gcc/config/rs6000/linux.h
===================================================================
--- gcc/config/rs6000/linux.h	(revision 191458)
+++ gcc/config/rs6000/linux.h	(working copy)
@@ -109,7 +109,7 @@
    -mrelocatable or -mrelocatable-lib is given.  */
 #undef RELOCATABLE_NEEDS_FIXUP
 #define RELOCATABLE_NEEDS_FIXUP \
-  (target_flags & target_flags_explicit & MASK_RELOCATABLE)
+  (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE)
 
 #define TARGET_POSIX_IO
 
Index: gcc/config/rs6000/t-rs6000
===================================================================
--- gcc/config/rs6000/t-rs6000	(revision 191458)
+++ gcc/config/rs6000/t-rs6000	(working copy)
@@ -26,7 +26,8 @@ rs6000.o: $(CONFIG_H) $(SYSTEM_H) corety
   $(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \
   output.h dbxout.h $(BASIC_BLOCK_H) toplev.h $(GGC_H) $(HASHTAB_H) \
   $(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h gt-rs6000.h \
-  cfgloop.h $(OPTS_H) $(COMMON_TARGET_H)
+  cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) \
+  $(srcdir)/config/rs6000/rs6000-cpus.def
 
 rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c \
     $(srcdir)/config/rs6000/rs6000-protos.h \
Index: gcc/config/rs6000/aix43.h
===================================================================
--- gcc/config/rs6000/aix43.h	(revision 191458)
+++ gcc/config/rs6000/aix43.h	(working copy)
@@ -26,7 +26,7 @@
 do {									\
   if (TARGET_64BIT && ! TARGET_POWERPC64)				\
     {									\
-      target_flags |= MASK_POWERPC64;					\
+      rs6000_isa_flags |= OPTION_MASK_POWERPC64;			\
       warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
     }									\
   if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128)			\
Index: gcc/config/rs6000/darwin.opt
===================================================================
--- gcc/config/rs6000/darwin.opt	(revision 191458)
+++ gcc/config/rs6000/darwin.opt	(working copy)
@@ -34,9 +34,9 @@ findirect-data
 Driver RejectNegative Alias(mfix-and-continue)
 
 m64
-Target RejectNegative Negative(m32) Mask(64BIT)
+Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags)
 Generate 64-bit code
 
 m32
-Target RejectNegative Negative(m64) InverseMask(64BIT)
+Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags)
 Generate 32-bit code
Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- gcc/config/rs6000/rs6000.opt	(revision 191458)
+++ gcc/config/rs6000/rs6000.opt	(working copy)
@@ -22,6 +22,17 @@
 HeaderInclude
 config/rs6000/rs6000-opts.h
 
+;; ISA flag bits (on/off)
+Variable
+HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT
+
+TargetSave
+HOST_WIDE_INT x_rs6000_isa_flags
+
+;; Miscellaneous flag bits that were set explicitly by the user
+TargetSave
+HOST_WIDE_INT x_rs6000_isa_flags_explicit
+
 ;; Current processor
 TargetVariable
 enum processor_type rs6000_cpu = PROCESSOR_PPC603
@@ -80,86 +91,82 @@ unsigned int rs6000_recip_control
 
 ;; Mask of what builtin functions are allowed
 TargetVariable
-unsigned int rs6000_builtin_mask
+HOST_WIDE_INT rs6000_builtin_mask
 
 ;; Debug flags
 TargetVariable
 unsigned int rs6000_debug
 
-;; Save for target_flags_explicit
-TargetSave
-int rs6000_target_flags_explicit
-
 ;; This option existed in the past, but now is always on.
 mpowerpc
 Target RejectNegative Undocumented Ignore
 
 mpowerpc64
-Target Report Mask(POWERPC64)
+Target Report Mask(POWERPC64) Var(rs6000_isa_flags)
 Use PowerPC-64 instruction set
 
 mpowerpc-gpopt
-Target Report Mask(PPC_GPOPT) Save
+Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
 Use PowerPC General Purpose group optional instructions
 
 mpowerpc-gfxopt
-Target Report Mask(PPC_GFXOPT) Save
+Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
 Use PowerPC Graphics group optional instructions
 
 mmfcrf
-Target Report Mask(MFCRF) Save
+Target Report Mask(MFCRF) Var(rs6000_isa_flags)
 Use PowerPC V2.01 single field mfcr instruction
 
 mpopcntb
-Target Report Mask(POPCNTB) Save
+Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
 Use PowerPC V2.02 popcntb instruction
 
 mfprnd
-Target Report Mask(FPRND) Save
+Target Report Mask(FPRND) Var(rs6000_isa_flags)
 Use PowerPC V2.02 floating point rounding instructions
 
 mcmpb
-Target Report Mask(CMPB) Save
+Target Report Mask(CMPB) Var(rs6000_isa_flags)
 Use PowerPC V2.05 compare bytes instruction
 
 mmfpgpr
-Target Report Mask(MFPGPR) Save
+Target Report Mask(MFPGPR) Var(rs6000_isa_flags)
 Use extended PowerPC V2.05 move floating point to/from GPR instructions
 
 maltivec
-Target Report Mask(ALTIVEC) Save
+Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
 Use AltiVec instructions
 
 mhard-dfp
-Target Report Mask(DFP) Save
+Target Report Mask(DFP) Var(rs6000_isa_flags)
 Use decimal floating point instructions
 
 mmulhw
-Target Report Mask(MULHW) Save
+Target Report Mask(MULHW) Var(rs6000_isa_flags)
 Use 4xx half-word multiply instructions
 
 mdlmzb
-Target Report Mask(DLMZB) Save
+Target Report Mask(DLMZB) Var(rs6000_isa_flags)
 Use 4xx string-search dlmzb instruction
 
 mmultiple
-Target Report Mask(MULTIPLE) Save
+Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
 Generate load/store multiple instructions
 
 mstring
-Target Report Mask(STRING) Save
+Target Report Mask(STRING) Var(rs6000_isa_flags)
 Generate string instructions for block moves
 
 msoft-float
-Target Report RejectNegative Mask(SOFT_FLOAT)
+Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
 Do not use hardware floating point
 
 mhard-float
-Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
+Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
 Use hardware floating point
 
 mpopcntd
-Target Report Mask(POPCNTD) Save
+Target Report Mask(POPCNTD) Var(rs6000_isa_flags)
 Use PowerPC V2.06 popcntd instruction
 
 mfriz
@@ -171,7 +178,7 @@ Target RejectNegative Joined Var(rs6000_
 Vector library ABI to use
 
 mvsx
-Target Report Mask(VSX) Save
+Target Report Mask(VSX) Var(rs6000_isa_flags)
 Use vector/scalar (VSX) instructions
 
 mvsx-scalar-double
@@ -211,11 +218,11 @@ Target Undocumented Report Var(TARGET_VE
 ; Explicitly control whether we vectorize the builtins or not.
 
 mno-update
-Target Report RejectNegative Mask(NO_UPDATE) Save
+Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
 Do not generate load/store with update instructions
 
 mupdate
-Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE)
+Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
 Generate load/store with update instructions
 
 msingle-pic-base
@@ -258,7 +265,7 @@ Target Report RejectNegative Joined Var(
 Generate software reciprocal divide and square root for better throughput.
 
 mrecip-precision
-Target Report Mask(RECIP_PRECISION) Save
+Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
 Assume that the reciprocal estimate instructions provide more accuracy.
 
 mno-fp-in-toc
@@ -285,7 +292,7 @@ Place symbol+offset constants in TOC
 ;   This is at the cost of having 2 extra loads and one extra store per
 ;   function, and one less allocable register.
 mminimal-toc
-Target Report Mask(MINIMAL_TOC)
+Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
 Use only one TOC entry per procedure
 
 mfull-toc
@@ -309,7 +316,7 @@ Target Report Var(rs6000_block_move_inli
 Specify how many bytes should be moved inline before calling out to memcpy/memmove
 
 misel
-Target Report Mask(ISEL) Save
+Target Report Mask(ISEL) Var(rs6000_isa_flags)
 Generate isel instructions
 
 misel=no
Index: gcc/config/rs6000/rs6000-c.c
===================================================================
--- gcc/config/rs6000/rs6000-c.c	(revision 191458)
+++ gcc/config/rs6000/rs6000-c.c	(working copy)
@@ -285,38 +285,42 @@ rs6000_define_or_undefine_macro (bool de
    have both the target flags and the builtin flags as arguments.  */
 
 void
-rs6000_target_modify_macros (bool define_p, int flags, unsigned bu_mask)
+rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
+			     HOST_WIDE_INT bu_mask)
 {
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
-    fprintf (stderr, "rs6000_target_modify_macros (%s, 0x%x, 0x%x)\n",
+    fprintf (stderr,
+	     "rs6000_target_modify_macros (%s, "
+	     HOST_WIDE_INT_PRINT_HEX ", "
+	     HOST_WIDE_INT_PRINT_HEX ")\n",
 	     (define_p) ? "define" : "undef",
-	     (unsigned) flags, bu_mask);
+	     flags, bu_mask);
 
-  /* target_flags based options.  */
+  /* rs6000_isa_flags based options.  */
   rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
-  if ((flags & MASK_PPC_GPOPT) != 0)
+  if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
-  if ((flags & MASK_PPC_GFXOPT) != 0)
+  if ((flags & OPTION_MASK_PPC_GFXOPT) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
-  if ((flags & MASK_POWERPC64) != 0)
+  if ((flags & OPTION_MASK_POWERPC64) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
-  if ((flags & MASK_MFCRF) != 0)
+  if ((flags & OPTION_MASK_MFCRF) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
-  if ((flags & MASK_POPCNTB) != 0)
+  if ((flags & OPTION_MASK_POPCNTB) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
-  if ((flags & MASK_FPRND) != 0)
+  if ((flags & OPTION_MASK_FPRND) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
-  if ((flags & MASK_CMPB) != 0)
+  if ((flags & OPTION_MASK_CMPB) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
-  if ((flags & MASK_MFPGPR) != 0)
+  if ((flags & OPTION_MASK_MFPGPR) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");
-  if ((flags & MASK_POPCNTD) != 0)
+  if ((flags & OPTION_MASK_POPCNTD) != 0)
     rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
-  if ((flags & MASK_SOFT_FLOAT) != 0)
+  if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
     rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
-  if ((flags & MASK_RECIP_PRECISION) != 0)
+  if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
     rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__");
-  if ((flags & MASK_ALTIVEC) != 0)
+  if ((flags & OPTION_MASK_ALTIVEC) != 0)
     {
       const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__";
       rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__");
@@ -326,7 +330,7 @@ rs6000_target_modify_macros (bool define
       if (!flag_iso)
 	rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__");
     }
-  if ((flags & MASK_VSX) != 0)
+  if ((flags & OPTION_MASK_VSX) != 0)
     rs6000_define_or_undefine_macro (define_p, "__VSX__");
 
   /* options from the builtin masks.  */
@@ -342,7 +346,7 @@ void
 rs6000_cpu_cpp_builtins (cpp_reader *pfile)
 {
   /* Define all of the common macros.  */
-  rs6000_target_modify_macros (true, target_flags,
+  rs6000_target_modify_macros (true, rs6000_isa_flags,
 			       rs6000_builtin_mask_calculate ());
 
   if (TARGET_FRE)
Index: gcc/config/rs6000/linux64.h
===================================================================
--- gcc/config/rs6000/linux64.h	(revision 191458)
+++ gcc/config/rs6000/linux64.h	(working copy)
@@ -81,7 +81,7 @@ extern int dot_symbols;
    -mrelocatable or -mrelocatable-lib is given.  */
 #undef RELOCATABLE_NEEDS_FIXUP
 #define RELOCATABLE_NEEDS_FIXUP \
-  (target_flags & target_flags_explicit & MASK_RELOCATABLE)
+  (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE)
 
 #undef	RS6000_ABI_NAME
 #define	RS6000_ABI_NAME "linux"
@@ -103,14 +103,14 @@ extern int dot_symbols;
 	      error (INVALID_64BIT, "call");			\
 	    }							\
 	  dot_symbols = !strcmp (rs6000_abi_name, "aixdesc");	\
-	  if (target_flags & MASK_RELOCATABLE)			\
+	  if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE)	\
 	    {							\
-	      target_flags &= ~MASK_RELOCATABLE;		\
+	      rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE;	\
 	      error (INVALID_64BIT, "relocatable");		\
 	    }							\
-	  if (target_flags & MASK_EABI)				\
+	  if (rs6000_isa_flags & OPTION_MASK_EABI)		\
 	    {							\
-	      target_flags &= ~MASK_EABI;			\
+	      rs6000_isa_flags &= ~OPTION_MASK_EABI;		\
 	      error (INVALID_64BIT, "eabi");			\
 	    }							\
 	  if (TARGET_PROTOTYPE)					\
@@ -118,12 +118,13 @@ extern int dot_symbols;
 	      target_prototype = 0;				\
 	      error (INVALID_64BIT, "prototype");		\
 	    }							\
-	  if ((target_flags & MASK_POWERPC64) == 0)		\
+	  if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0)	\
 	    {							\
-	      target_flags |= MASK_POWERPC64;			\
+	      rs6000_isa_flags |= OPTION_MASK_POWERPC64;	\
 	      error ("-m64 requires a PowerPC64 cpu");		\
 	    }							\
-	  if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0)	\
+	  if ((rs6000_isa_flags_explicit			\
+	       & OPTION_MASK_MINIMAL_TOC) != 0)			\
 	    {							\
 	      if (global_options_set.x_rs6000_current_cmodel	\
 		  && rs6000_current_cmodel != CMODEL_SMALL)	\
@@ -213,20 +214,20 @@ extern int dot_symbols;
 #ifndef RS6000_BI_ARCH
 
 /* 64-bit PowerPC Linux is always big-endian.  */
-#undef	TARGET_LITTLE_ENDIAN
-#define TARGET_LITTLE_ENDIAN	0
+#undef	OPTION_LITTLE_ENDIAN
+#define OPTION_LITTLE_ENDIAN	0
 
 /* 64-bit PowerPC Linux always has a TOC.  */
 #undef  TARGET_TOC
 #define	TARGET_TOC		1
 
 /* Some things from sysv4.h we don't do when 64 bit.  */
-#undef	TARGET_RELOCATABLE
-#define	TARGET_RELOCATABLE	0
-#undef	TARGET_EABI
-#define	TARGET_EABI		0
-#undef	TARGET_PROTOTYPE
-#define	TARGET_PROTOTYPE	0
+#undef	OPTION_RELOCATABLE
+#define	OPTION_RELOCATABLE	0
+#undef	OPTION_EABI
+#define	OPTION_EABI		0
+#undef	OPTION_PROTOTYPE
+#define	OPTION_PROTOTYPE	0
 #undef RELOCATABLE_NEEDS_FIXUP
 #define RELOCATABLE_NEEDS_FIXUP 0
 
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 191458)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -213,7 +213,7 @@ static GTY(()) section *toc_section;
 
 struct builtin_description
 {
-  const unsigned int mask;
+  const HOST_WIDE_INT mask;
   const enum insn_code icode;
   const char *const name;
   const enum rs6000_builtins code;
@@ -287,7 +287,7 @@ typedef rtx (*gen_2arg_fn_t) (rtx, rtx, 
 /* Pointer to function (in rs6000-c.c) that can define or undefine target
    macros that have changed.  Languages that don't support the preprocessor
    don't link in rs6000-c.c, so we can't call it directly.  */
-void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned);
+void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
 
 
 /* Target cpu costs.  */
@@ -893,7 +893,7 @@ struct processor_costs ppca2_cost = {
 struct rs6000_builtin_info_type {
   const char *name;
   const enum insn_code icode;
-  const unsigned mask;
+  const HOST_WIDE_INT mask;
   const unsigned attr;
 };
 
@@ -1015,6 +1015,8 @@ bool (*rs6000_cannot_change_mode_class_p
 
 const int INSN_NOT_AVAILABLE = -1;
 
+static void rs6000_print_isa_options (FILE *, HOST_WIDE_INT);
+
 /* Hash table stuff for keeping track of TOC entries.  */
 
 struct GTY(()) toc_hash_struct
@@ -1115,7 +1117,8 @@ static const struct attribute_spec rs600
   { NULL,        0, 0, false, false, false, NULL, false }
 };
 
-#ifndef MASK_STRICT_ALIGN
+#ifndef OPTION_MASK_STRICT_ALIGN
+#define OPTION_MASK_STRICT_ALIGN 0
 #define MASK_STRICT_ALIGN 0
 #endif
 #ifndef TARGET_PROFILE_KERNEL
@@ -1458,53 +1461,12 @@ static const struct attribute_spec rs600
 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
 
 
-/* Simplifications for entries below.  */
-
-enum {
-  POWERPC_7400_MASK = MASK_PPC_GFXOPT | MASK_ALTIVEC
-};
-
-/* Some OSs don't support saving the high part of 64-bit registers on context
-   switch.  Other OSs don't support saving Altivec registers.  On those OSs, we
-   don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants
-   either, the user must explicitly specify them and we won't interfere with
-   the user's specification.  */
-
-enum {
-  POWERPC_MASKS = (MASK_PPC_GPOPT | MASK_STRICT_ALIGN
-		   | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
-		   | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
-		   | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP
-		   | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE
-		   | MASK_RECIP_PRECISION)
-};
-
-/* Masks for instructions set at various powerpc ISAs.  */
-enum {
-  ISA_2_1_MASKS = MASK_MFCRF,
-  ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB),
-  ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND),
-
-  /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
-     ALTIVEC, since in general it isn't a win on power6.  In ISA 2.04, fsel,
-     fre, fsqrt, etc. were no longer documented as optional.  Group masks by
-     server and embedded. */
-  ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION
-			    | MASK_PPC_GFXOPT | MASK_PPC_GPOPT),
-  ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP),
-
-  /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
-     altivec is a win so enable it.  */
-  ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD),
-  ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC
-			  | MASK_VSX)
-};
-
+/* Processor table.  */
 struct rs6000_ptt
 {
   const char *const name;		/* Canonical processor name.  */
   const enum processor_type processor;	/* Processor type enum value.  */
-  const int target_enable;		/* Target flags to enable.  */
+  const HOST_WIDE_INT target_enable;	/* Target flags to enable.  */
 };
 
 static struct rs6000_ptt const processor_target_table[] =
@@ -1715,9 +1677,12 @@ rs6000_debug_reg_print (int first_regno,
     }
 }
 
-#define DEBUG_FMT_D "%-32s= %d\n"
-#define DEBUG_FMT_X "%-32s= 0x%x\n"
-#define DEBUG_FMT_S "%-32s= %s\n"
+#define DEBUG_FMT_ID "%-32s= "
+#define DEBUG_FMT_D   DEBUG_FMT_ID "%d\n"
+#define DEBUG_FMT_X   DEBUG_FMT_ID "%#x\n"
+#define DEBUG_FMT_WX  DEBUG_FMT_ID HOST_WIDE_INT_PRINT_HEX ": "
+#define DEBUG_FMT_WX2 DEBUG_FMT_ID HOST_WIDE_INT_PRINT_HEX "\n"
+#define DEBUG_FMT_S   DEBUG_FMT_ID "%s\n"
 
 /* Print various interesting information with -mdebug=reg.  */
 static void
@@ -1728,11 +1693,13 @@ rs6000_debug_reg_global (void)
   int m;
   char costly_num[20];
   char nop_num[20];
+  char flags_buffer[40];
   const char *costly_str;
   const char *nop_str;
   const char *trace_str;
   const char *abi_str;
   const char *cmodel_str;
+  struct cl_target_option cl_opts;
 
   /* Map enum rs6000_vector to string.  */
   static const char *rs6000_debug_vector_unit[] = {
@@ -1812,12 +1779,69 @@ rs6000_debug_reg_global (void)
     }
 
   if (rs6000_cpu_index >= 0)
-    fprintf (stderr, DEBUG_FMT_S, "cpu",
-	     processor_target_table[rs6000_cpu_index].name);
+    {
+      const char *name = processor_target_table[rs6000_cpu_index].name;
+      fprintf (stderr, DEBUG_FMT_S, "cpu", name);
+      sprintf (flags_buffer, "%s cpu flags", name);
+
+      if (processor_target_table[rs6000_cpu_index].target_enable)
+	{
+	  HOST_WIDE_INT flags
+	    = processor_target_table[rs6000_cpu_index].target_enable;
+	  fprintf (stderr, DEBUG_FMT_WX, flags_buffer, flags);
+	  rs6000_print_isa_options (stderr, flags);
+	}
+      else
+	fprintf (stderr, DEBUG_FMT_S, flags_buffer, "<none>");
+    }
+  else
+    fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
 
   if (rs6000_tune_index >= 0)
-    fprintf (stderr, DEBUG_FMT_S, "tune",
-	     processor_target_table[rs6000_tune_index].name);
+    {
+      const char *name = processor_target_table[rs6000_tune_index].name;
+      fprintf (stderr, DEBUG_FMT_S, "tune", name);
+      sprintf (flags_buffer, "%s tune flags", name);
+
+      if (processor_target_table[rs6000_tune_index].target_enable)
+	{
+	  HOST_WIDE_INT flags
+	    = processor_target_table[rs6000_tune_index].target_enable;
+	  fprintf (stderr, DEBUG_FMT_WX, flags_buffer, flags);
+	  rs6000_print_isa_options (stderr, flags);
+	}
+      else
+	fprintf (stderr, DEBUG_FMT_S, flags_buffer, "<none>");
+    }
+  else
+    fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
+
+  cl_target_option_save (&cl_opts, &global_options);
+  if (rs6000_isa_flags)
+    {
+      fprintf (stderr, DEBUG_FMT_WX, "rs6000_isa_flags", rs6000_isa_flags);
+      rs6000_print_isa_options (stderr, rs6000_isa_flags);
+    }
+  else
+    fprintf (stderr, DEBUG_FMT_S, "rs6000_isa_flags", "<none>");
+
+  if (rs6000_isa_flags_explicit)
+    {
+      fprintf (stderr, DEBUG_FMT_WX, "rs6000_isa_flags_explicit",
+	       rs6000_isa_flags_explicit);
+      rs6000_print_isa_options (stderr, rs6000_isa_flags_explicit);
+    }
+  else
+    fprintf (stderr, DEBUG_FMT_S, "rs6000_isa_flags_explicit", "<none>");
+
+  if (rs6000_builtin_mask)
+    {
+      fprintf (stderr, DEBUG_FMT_WX, "rs6000_builtin_mask",
+	       rs6000_builtin_mask);
+      rs6000_print_isa_options (stderr, rs6000_builtin_mask);
+    }
+  else
+    fprintf (stderr, DEBUG_FMT_S, "rs6000_builtin_mask", "<none>");
 
   switch (rs6000_sched_costly_dep)
     {
@@ -1935,7 +1959,15 @@ rs6000_debug_reg_global (void)
   if (rs6000_float_gprs)
     fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
 
+  if (TARGET_LINK_STACK)
+    fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
+
+  fprintf (stderr, DEBUG_FMT_S, "plt-format",
+	   TARGET_SECURE_PLT ? "secure" : "bss");
+  fprintf (stderr, DEBUG_FMT_S, "struct-return",
+	   aix_struct_return ? "aix" : "sysv");
   fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
+  fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
   fprintf (stderr, DEBUG_FMT_S, "align_branch",
 	   tf[!!rs6000_align_branch_targets]);
   fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
@@ -1947,7 +1979,6 @@ rs6000_debug_reg_global (void)
 	   (int)END_BUILTINS);
   fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
 	   (int)RS6000_BUILTIN_COUNT);
-  fprintf (stderr, DEBUG_FMT_X, "Builtin mask", rs6000_builtin_mask);
 }
 
 /* Initialize the various global tables that are based on register size.  */
@@ -2311,21 +2342,21 @@ darwin_rs6000_override_options (void)
 
   if (TARGET_64BIT && ! TARGET_POWERPC64)
     {
-      target_flags |= MASK_POWERPC64;
+      rs6000_isa_flags |= OPTION_MASK_POWERPC64;
       warning (0, "-m64 requires PowerPC64 architecture, enabling");
     }
   if (flag_mkernel)
     {
       rs6000_default_long_calls = 1;
-      target_flags |= MASK_SOFT_FLOAT;
+      rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
     }
 
   /* Make -m64 imply -maltivec.  Darwin's 64-bit ABI includes
      Altivec.  */
   if (!flag_mkernel && !flag_apple_kext
       && TARGET_64BIT
-      && ! (target_flags_explicit & MASK_ALTIVEC))
-    target_flags |= MASK_ALTIVEC;
+      && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
+    rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
 
   /* Unless the user (not the configurer) has explicitly overridden
      it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
@@ -2333,10 +2364,10 @@ darwin_rs6000_override_options (void)
   if (!flag_mkernel
       && !flag_apple_kext
       && strverscmp (darwin_macosx_version_min, "10.5") >= 0
-      && ! (target_flags_explicit & MASK_ALTIVEC)
+      && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
       && ! global_options_set.x_rs6000_cpu_index)
     {
-      target_flags |= MASK_ALTIVEC;
+      rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
     }
 }
 #endif
@@ -2353,7 +2384,7 @@ darwin_rs6000_override_options (void)
    bits, and some options like SPE and PAIRED are no longer in
    target_flags.  */
 
-unsigned
+HOST_WIDE_INT
 rs6000_builtin_mask_calculate (void)
 {
   return (((TARGET_ALTIVEC)		    ? RS6000_BTM_ALTIVEC  : 0)
@@ -2380,7 +2411,7 @@ rs6000_option_override_internal (bool gl
   /* The default cpu requested at configure time, if any.  */
   const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT;
 
-  int set_masks;
+  HOST_WIDE_INT set_masks;
   int cpu_index;
   int tune_index;
   struct cl_target_option *main_target_opt
@@ -2417,18 +2448,24 @@ rs6000_option_override_internal (bool gl
       rs6000_pointer_size = 32;
     }
 
-  set_masks = POWERPC_MASKS | MASK_SOFT_FLOAT;
+  /* Some OSs don't support saving the high part of 64-bit registers on context
+     switch.  Other OSs don't support saving Altivec registers.  On those OSs,
+     we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
+     if the user wants either, the user must explicitly specify them and we
+     won't interfere with the user's specification.  */
+
+  set_masks = POWERPC_MASKS;
 #ifdef OS_MISSING_POWERPC64
   if (OS_MISSING_POWERPC64)
-    set_masks &= ~MASK_POWERPC64;
+    set_masks &= ~OPTION_MASK_POWERPC64;
 #endif
 #ifdef OS_MISSING_ALTIVEC
   if (OS_MISSING_ALTIVEC)
-    set_masks &= ~MASK_ALTIVEC;
+    set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX);
 #endif
 
   /* Don't override by the processor default if given explicitly.  */
-  set_masks &= ~target_flags_explicit;
+  set_masks &= ~rs6000_isa_flags_explicit;
 
   /* Process the -mcpu=<xxx> and -mtune=<xxx> argument.  If the user changed
      the cpu in a target attribute or pragma, but did not specify a tuning
@@ -2457,9 +2494,9 @@ rs6000_option_override_internal (bool gl
 
   gcc_assert (cpu_index >= 0);
 
-  target_flags &= ~set_masks;
-  target_flags |= (processor_target_table[cpu_index].target_enable
-		   & set_masks);
+  rs6000_isa_flags &= ~set_masks;
+  rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
+		       & set_masks);
 
   if (rs6000_tune_index >= 0)
     tune_index = rs6000_tune_index;
@@ -2544,7 +2581,8 @@ rs6000_option_override_internal (bool gl
      use instructions that would be microcoded on the Cell, use the
      load/store multiple and string instructions.  */
   if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
-    target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
+    rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE
+						      | OPTION_MASK_STRING);
 
   /* Don't allow -mmultiple or -mstring on little endian systems
      unless the cpu is a 750, because the hardware doesn't support the
@@ -2556,15 +2594,15 @@ rs6000_option_override_internal (bool gl
     {
       if (TARGET_MULTIPLE)
 	{
-	  target_flags &= ~MASK_MULTIPLE;
-	  if ((target_flags_explicit & MASK_MULTIPLE) != 0)
+	  rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
+	  if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
 	    warning (0, "-mmultiple is not supported on little endian systems");
 	}
 
       if (TARGET_STRING)
 	{
-	  target_flags &= ~MASK_STRING;
-	  if ((target_flags_explicit & MASK_STRING) != 0)
+	  rs6000_isa_flags &= ~OPTION_MASK_STRING;
+	  if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0)
 	    warning (0, "-mstring is not supported on little endian systems");
 	}
     }
@@ -2576,10 +2614,10 @@ rs6000_option_override_internal (bool gl
       if (!TARGET_HARD_FLOAT || !TARGET_FPRS
 	  || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
 	{
-	  if (target_flags_explicit & MASK_VSX)
+	  if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
 	    msg = N_("-mvsx requires hardware floating point");
 	  else
-	    target_flags &= ~ MASK_VSX;
+	    rs6000_isa_flags &= ~ OPTION_MASK_VSX;
 	}
       else if (TARGET_PAIRED_FLOAT)
 	msg = N_("-mvsx and -mpaired are incompatible");
@@ -2590,9 +2628,10 @@ rs6000_option_override_internal (bool gl
 	msg = N_("-mvsx used with little endian code");
       else if (TARGET_AVOID_XFORM > 0)
 	msg = N_("-mvsx needs indexed addressing");
-      else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC))
+      else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
+				   & OPTION_MASK_ALTIVEC))
         {
-	  if (target_flags_explicit & MASK_VSX)
+	  if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
 	    msg = N_("-mvsx and -mno-altivec are incompatible");
 	  else
 	    msg = N_("-mno-altivec disables vsx");
@@ -2601,27 +2640,27 @@ rs6000_option_override_internal (bool gl
       if (msg)
 	{
 	  warning (0, msg);
-	  target_flags &= ~ MASK_VSX;
-	  target_flags_explicit |= MASK_VSX;
+	  rs6000_isa_flags &= ~ OPTION_MASK_VSX;
+	  rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
 	}
     }
 
   /* For the newer switches (vsx, dfp, etc.) set some of the older options,
      unless the user explicitly used the -mno-<option> to disable the code.  */
   if (TARGET_VSX)
-    target_flags |= (ISA_2_6_MASKS_SERVER & ~target_flags_explicit);
+    rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit);
   else if (TARGET_POPCNTD)
-    target_flags |= (ISA_2_6_MASKS_EMBEDDED & ~target_flags_explicit);
+    rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);
   else if (TARGET_DFP)
-    target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit);
+    rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~rs6000_isa_flags_explicit);
   else if (TARGET_CMPB)
-    target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit);
+    rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);
   else if (TARGET_FPRND)
-    target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit);
+    rs6000_isa_flags |= (ISA_2_4_MASKS & ~rs6000_isa_flags_explicit);
   else if (TARGET_POPCNTB)
-    target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit);
+    rs6000_isa_flags |= (ISA_2_2_MASKS & ~rs6000_isa_flags_explicit);
   else if (TARGET_ALTIVEC)
-    target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit);
+    rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit);
 
   /* E500mc does "better" if we inline more aggressively.  Respect the
      user's opinion, though.  */
@@ -2700,7 +2739,8 @@ rs6000_option_override_internal (bool gl
      unless the altivec ABI was set.  This is set by default for 64-bit, but
      not for 32-bit.  */
   if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
-    target_flags &= ~((MASK_VSX | MASK_ALTIVEC) & ~target_flags_explicit);
+    rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC)
+			  & ~rs6000_isa_flags_explicit);
 
   /* Enable Altivec ABI for AIX -maltivec.  */
   if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
@@ -2782,14 +2822,14 @@ rs6000_option_override_internal (bool gl
       rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
       rs6000_double_float = TARGET_E500_DOUBLE;
 
-      target_flags &= ~MASK_STRING;
+      rs6000_isa_flags &= ~OPTION_MASK_STRING;
 
       break;
 
     default:
 
-      if (have_cpu && !(target_flags_explicit & MASK_ISEL))
-	target_flags &= ~MASK_ISEL;
+      if (have_cpu && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL))
+	rs6000_isa_flags &= ~OPTION_MASK_ISEL;
 
       break;
     }
@@ -3166,11 +3206,12 @@ rs6000_option_override_internal (bool gl
      target_flags.  */
   rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
   if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
-    fprintf (stderr, "new builtin mask = 0x%x%s%s%s%s\n", rs6000_builtin_mask,
-	     (rs6000_builtin_mask & RS6000_BTM_ALTIVEC) ? ", altivec" : "",
-	     (rs6000_builtin_mask & RS6000_BTM_VSX)     ? ", vsx"     : "",
-	     (rs6000_builtin_mask & RS6000_BTM_PAIRED)  ? ", paired"  : "",
-	     (rs6000_builtin_mask & RS6000_BTM_SPE)     ? ", spe" : "");
+    {
+      fprintf (stderr,
+	       "new builtin mask = " HOST_WIDE_INT_PRINT_HEX ", ",
+	       rs6000_builtin_mask);
+      rs6000_print_isa_options (stderr, rs6000_builtin_mask);
+    }
 
   /* Initialize all of the registers.  */
   rs6000_init_hard_regno_mode_ok (global_init_p);
@@ -10407,7 +10448,7 @@ altivec_expand_dst_builtin (tree exp, rt
 			    bool *expandedp)
 {
   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
-  unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
+  enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
   tree arg0, arg1, arg2;
   enum machine_mode mode0, mode1;
   rtx pat, op0, op1, op2;
@@ -10809,7 +10850,7 @@ static rtx
 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
 {
   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
-  unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
+  enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
   const struct builtin_description *d;
   size_t i;
 
@@ -10874,7 +10915,7 @@ spe_expand_builtin (tree exp, rtx target
 {
   tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
   tree arg1, arg0;
-  unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
+  enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
   enum insn_code icode;
   enum machine_mode tmode, mode0;
   rtx pat, op0;
@@ -11239,7 +11280,7 @@ rs6000_invalid_builtin (enum rs6000_buil
 {
   size_t uns_fncode = (size_t)fncode;
   const char *name = rs6000_builtin_info[uns_fncode].name;
-  unsigned fnmask = rs6000_builtin_info[uns_fncode].mask;
+  HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
 
   gcc_assert (name != NULL);
   if ((fnmask & RS6000_BTM_CELL) != 0)
@@ -11276,7 +11317,7 @@ rs6000_expand_builtin (tree exp, rtx tar
   size_t i;
   rtx ret;
   bool success;
-  unsigned mask = rs6000_builtin_info[uns_fcode].mask;
+  HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
   bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
 
   if (TARGET_DEBUG_BUILTIN)
@@ -11637,7 +11678,7 @@ rs6000_init_builtins (void)
 static tree
 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
 {
-  unsigned fnmask;
+  HOST_WIDE_INT fnmask;
 
   if (code >= RS6000_BUILTIN_COUNT)
     return error_mark_node;
@@ -12509,7 +12550,7 @@ rs6000_common_init_builtins (void)
   tree v2si_ftype_qi = NULL_TREE;
   tree v2si_ftype_v2si_qi = NULL_TREE;
   tree v2si_ftype_int_qi = NULL_TREE;
-  unsigned builtin_mask = rs6000_builtin_mask;
+  HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
 
   if (!TARGET_PAIRED_FLOAT)
     {
@@ -12531,7 +12572,7 @@ rs6000_common_init_builtins (void)
   for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
     {
       tree type;
-      unsigned mask = d->mask;
+      HOST_WIDE_INT mask = d->mask;
 
       if ((mask & builtin_mask) != mask)
 	{
@@ -12572,7 +12613,7 @@ rs6000_common_init_builtins (void)
     {
       enum machine_mode mode0, mode1, mode2;
       tree type;
-      unsigned mask = d->mask;
+      HOST_WIDE_INT mask = d->mask;
 
       if ((mask & builtin_mask) != mask)
 	{
@@ -12635,7 +12676,7 @@ rs6000_common_init_builtins (void)
     {
       enum machine_mode mode0, mode1;
       tree type;
-      unsigned mask = d->mask;
+      HOST_WIDE_INT mask = d->mask;
 
       if ((mask & builtin_mask) != mask)
 	{
@@ -25200,7 +25241,7 @@ rs6000_darwin_file_start (void)
   {
     const char *arg;
     const char *name;
-    int if_set;
+    HOST_WIDE_INT if_set;
   } mapping[] = {
     { "ppc64", "ppc64", MASK_64BIT },
     { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
@@ -25239,7 +25280,7 @@ rs6000_darwin_file_start (void)
   i = 0;
   while (mapping[i].arg != NULL
 	 && strcmp (mapping[i].arg, cpu_id) != 0
-	 && (mapping[i].if_set & target_flags) == 0)
+	 && (mapping[i].if_set & rs6000_isa_flags) == 0)
     i++;
 
   fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
@@ -27333,55 +27374,55 @@ rs6000_final_prescan_insn (rtx insn, rtx
 
 struct rs6000_opt_mask {
   const char *name;		/* option name */
-  int mask;			/* mask to set */
+  HOST_WIDE_INT mask;		/* mask to set */
   bool invert;			/* invert sense of mask */
   bool valid_target;		/* option is a target option */
 };
 
 static struct rs6000_opt_mask const rs6000_opt_masks[] =
 {
-  { "altivec",		MASK_ALTIVEC,		false, true  },
-  { "cmpb",		MASK_CMPB,		false, true  },
-  { "dlmzb",		MASK_DLMZB,		false, true  },
-  { "fprnd",		MASK_FPRND,		false, true  },
-  { "hard-dfp",		MASK_DFP,		false, true  },
-  { "isel",		MASK_ISEL,		false, true  },
-  { "mfcrf",		MASK_MFCRF,		false, true  },
-  { "mfpgpr",		MASK_MFPGPR,		false, true  },
-  { "mulhw",		MASK_MULHW,		false, true  },
-  { "multiple",		MASK_MULTIPLE,		false, true  },
-  { "update",		MASK_NO_UPDATE,		true , true  },
-  { "popcntb",		MASK_POPCNTB,		false, true  },
-  { "popcntd",		MASK_POPCNTD,		false, true  },
-  { "powerpc-gfxopt",	MASK_PPC_GFXOPT,	false, true  },
-  { "powerpc-gpopt",	MASK_PPC_GPOPT,		false, true  },
-  { "recip-precision",	MASK_RECIP_PRECISION,	false, true  },
-  { "string",		MASK_STRING,		false, true  },
-  { "vsx",		MASK_VSX,		false, true  },
-#ifdef MASK_64BIT
+  { "altivec",			OPTION_MASK_ALTIVEC,		false, true  },
+  { "cmpb",			OPTION_MASK_CMPB,		false, true  },
+  { "dlmzb",			OPTION_MASK_DLMZB,		false, true  },
+  { "fprnd",			OPTION_MASK_FPRND,		false, true  },
+  { "hard-dfp",			OPTION_MASK_DFP,		false, true  },
+  { "isel",			OPTION_MASK_ISEL,		false, true  },
+  { "mfcrf",			OPTION_MASK_MFCRF,		false, true  },
+  { "mfpgpr",			OPTION_MASK_MFPGPR,		false, true  },
+  { "mulhw",			OPTION_MASK_MULHW,		false, true  },
+  { "multiple",			OPTION_MASK_MULTIPLE,		false, true  },
+  { "update",			OPTION_MASK_NO_UPDATE,		true , true  },
+  { "popcntb",			OPTION_MASK_POPCNTB,		false, true  },
+  { "popcntd",			OPTION_MASK_POPCNTD,		false, true  },
+  { "powerpc-gfxopt",		OPTION_MASK_PPC_GFXOPT,		false, true  },
+  { "powerpc-gpopt",		OPTION_MASK_PPC_GPOPT,		false, true  },
+  { "recip-precision",		OPTION_MASK_RECIP_PRECISION,	false, true  },
+  { "string",			OPTION_MASK_STRING,		false, true  },
+  { "vsx",			OPTION_MASK_VSX,		false, true  },
+#ifdef OPTION_MASK_64BIT
 #if TARGET_AIX_OS
-  { "aix64",		MASK_64BIT,		false, false },
-  { "aix32",		MASK_64BIT,		true,  false },
+  { "aix64",			OPTION_MASK_64BIT,		false, false },
+  { "aix32",			OPTION_MASK_64BIT,		true,  false },
 #else
-  { "64",		MASK_64BIT,		false, false },
-  { "32",		MASK_64BIT,		true,  false },
+  { "64",			OPTION_MASK_64BIT,		false, false },
+  { "32",			OPTION_MASK_64BIT,		true,  false },
 #endif
 #endif
-#ifdef MASK_EABI
-  { "eabi",		MASK_EABI,		false, false },
+#ifdef OPTION_MASK_EABI
+  { "eabi",			OPTION_MASK_EABI,		false, false },
 #endif
-#ifdef MASK_LITTLE_ENDIAN
-  { "little",		MASK_LITTLE_ENDIAN,	false, false },
-  { "big",		MASK_LITTLE_ENDIAN,	true,  false },
+#ifdef OPTION_MASK_LITTLE_ENDIAN
+  { "little",			OPTION_MASK_LITTLE_ENDIAN,	false, false },
+  { "big",			OPTION_MASK_LITTLE_ENDIAN,	true,  false },
 #endif
-#ifdef MASK_RELOCATABLE
-  { "relocatable",	MASK_RELOCATABLE,	false, false },
+#ifdef OPTION_MASK_RELOCATABLE
+  { "relocatable",		OPTION_MASK_RELOCATABLE,	false, false },
 #endif
-#ifdef MASK_STRICT_ALIGN
-  { "strict-align",	MASK_STRICT_ALIGN,	false, false },
+#ifdef OPTION_MASK_STRICT_ALIGN
+  { "strict-align",		OPTION_MASK_STRICT_ALIGN,	false, false },
 #endif
-  { "soft-float",	MASK_SOFT_FLOAT,	false, false },
-  { "string",		MASK_STRING,		false, false },
+  { "soft-float",		OPTION_MASK_SOFT_FLOAT,		false, false },
+  { "string",			OPTION_MASK_STRING,		false, false },
 };
 
 /* Builtin mask mapping for printing the flags.  */
@@ -27485,27 +27526,27 @@ rs6000_inner_target_options (tree args, 
 	      for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
 		if (strcmp (r, rs6000_opt_masks[i].name) == 0)
 		  {
-		    int mask = rs6000_opt_masks[i].mask;
+		    HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
 
 		    if (!rs6000_opt_masks[i].valid_target)
 		      not_valid_p = true;
 		    else
 		      {
 			error_p = false;
-			target_flags_explicit |= mask;
+			rs6000_isa_flags_explicit |= mask;
 
 			/* VSX needs altivec, so -mvsx automagically sets
 			   altivec.  */
-			if (mask == MASK_VSX && !invert)
-			  mask |= MASK_ALTIVEC;
+			if (mask == OPTION_MASK_VSX && !invert)
+			  mask |= OPTION_MASK_ALTIVEC;
 
 			if (rs6000_opt_masks[i].invert)
 			  invert = !invert;
 
 			if (invert)
-			  target_flags &= ~mask;
+			  rs6000_isa_flags &= ~mask;
 			else
-			  target_flags |= mask;
+			  rs6000_isa_flags |= mask;
 		      }
 		    break;
 		  }
@@ -27709,8 +27750,8 @@ rs6000_pragma_target_parse (tree args, t
   tree prev_tree = build_target_option_node ();
   tree cur_tree;
   struct cl_target_option *prev_opt, *cur_opt;
-  unsigned prev_bumask, cur_bumask, diff_bumask;
-  int prev_flags, cur_flags, diff_flags;
+  HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
+  HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
 
   if (TARGET_DEBUG_TARGET)
     {
@@ -27760,14 +27801,14 @@ rs6000_pragma_target_parse (tree args, t
     {
       prev_opt    = TREE_TARGET_OPTION (prev_tree);
       prev_bumask = prev_opt->x_rs6000_builtin_mask;
-      prev_flags  = prev_opt->x_target_flags;
+      prev_flags  = prev_opt->x_rs6000_isa_flags;
 
       cur_opt     = TREE_TARGET_OPTION (cur_tree);
-      cur_flags   = cur_opt->x_target_flags;
+      cur_flags   = cur_opt->x_rs6000_isa_flags;
       cur_bumask  = cur_opt->x_rs6000_builtin_mask;
 
       diff_bumask = (prev_bumask ^ cur_bumask);
-      diff_flags  = (prev_flags  ^ cur_flags);
+      diff_flags  = (prev_flags ^ cur_flags);
 
       if ((diff_flags != 0) || (diff_bumask != 0))
 	{
@@ -27870,7 +27911,8 @@ rs6000_set_current_function (tree fndecl
 static void
 rs6000_function_specific_save (struct cl_target_option *ptr)
 {
-  ptr->rs6000_target_flags_explicit = target_flags_explicit;
+  ptr->x_rs6000_isa_flags = rs6000_isa_flags;
+  ptr->x_rs6000_isa_flags_explicit = rs6000_isa_flags_explicit;
 }
 
 /* Restore the current options */
@@ -27878,47 +27920,62 @@ rs6000_function_specific_save (struct cl
 static void
 rs6000_function_specific_restore (struct cl_target_option *ptr)
 {
-  target_flags_explicit = ptr->rs6000_target_flags_explicit;
+  rs6000_isa_flags = ptr->x_rs6000_isa_flags;
+  rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
   (void) rs6000_option_override_internal (false);
 }
 
-/* Print the current options */
+/* Helper function to print the current isa or misc options on a line.  */
 
 static void
-rs6000_function_specific_print (FILE *file, int indent,
-				struct cl_target_option *ptr)
+rs6000_print_isa_or_misc_options (FILE *file,
+				  HOST_WIDE_INT flags,
+				  const struct rs6000_opt_mask *opts,
+				  size_t num_elements)
 {
   size_t i;
-  int flags = ptr->x_target_flags;
-  unsigned bu_mask = ptr->x_rs6000_builtin_mask;
+  const char *comma  = "";
+  const char *suffix = "<none>\n";
 
   /* Print the various mask options.  */
-  for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
-    if ((flags & rs6000_opt_masks[i].mask) != 0)
+  for (i = 0; i < num_elements; i++)
+    if ((flags & opts[i].mask) != 0)
       {
-	flags &= ~ rs6000_opt_masks[i].mask;
-	fprintf (file, "%*s-m%s%s\n", indent, "",
+	flags &= ~ opts[i].mask;
+	fprintf (file, "%s-m%s%s", comma,
 		 rs6000_opt_masks[i].invert ? "no-" : "",
 		 rs6000_opt_masks[i].name);
+	comma = ", ";
+	suffix = "\n";
       }
 
-  /* Print the various options that are variables.  */
-  for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
-    {
-      size_t j = rs6000_opt_vars[i].target_offset;
-      if (((signed char *) ptr)[j])
-	fprintf (file, "%*s-m%s\n", indent, "",
-		 rs6000_opt_vars[i].name);
-    }
+  fputs (suffix, file);
+}
 
-  /* Print the various builtin flags.  */
-  fprintf (file, "%*sbuiltin mask = 0x%x\n", indent, "", bu_mask);
-  for (i = 0; i < ARRAY_SIZE (rs6000_builtin_mask_names); i++)
-    if ((bu_mask & rs6000_builtin_mask_names[i].mask) != 0)
-      {
-	fprintf (file, "%*s%s builtins supported\n", indent, "",
-		 rs6000_builtin_mask_names[i].name);
-      }
+/* Helper function to print the current isa options on a line.  */
+
+static void
+rs6000_print_isa_options (FILE *file, HOST_WIDE_INT flags)
+{
+  rs6000_print_isa_or_misc_options (file, flags, &rs6000_opt_masks[0],
+				    ARRAY_SIZE (rs6000_opt_masks));
+}
+
+/* Print the current options */
+
+static void
+rs6000_function_specific_print (FILE *file, int indent,
+				struct cl_target_option *ptr)
+{
+  fprintf (file,
+	   "%*sOptions (" HOST_WIDE_INT_PRINT_HEX "): ",
+	   indent, "", ptr->x_rs6000_isa_flags);
+  rs6000_print_isa_options (file, ptr->x_rs6000_isa_flags);
+
+  fprintf (file,
+	   "%*sExplict (" HOST_WIDE_INT_PRINT_HEX "): ",
+	   indent, "", ptr->x_rs6000_isa_flags_explicit);
+  rs6000_print_isa_options (file, ptr->x_rs6000_isa_flags_explicit);
 }
 
 
@@ -27948,8 +28005,8 @@ rs6000_can_inline_p (tree caller, tree c
       /* Callee's options should a subset of the caller's, i.e. a vsx function
 	 can inline an altivec function but a non-vsx function can't inline a
 	 vsx function.  */
-      if ((caller_opts->x_target_flags & callee_opts->x_target_flags)
-	  == callee_opts->x_target_flags)
+      if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
+	  == callee_opts->x_rs6000_isa_flags)
 	ret = true;
     }
 
Index: gcc/config/rs6000/aix52.h
===================================================================
--- gcc/config/rs6000/aix52.h	(revision 191458)
+++ gcc/config/rs6000/aix52.h	(working copy)
@@ -26,7 +26,7 @@
 do {									\
   if (TARGET_64BIT && ! TARGET_POWERPC64)				\
     {									\
-      target_flags |= MASK_POWERPC64;					\
+      rs6000_isa_flags |= OPTION_MASK_POWERPC64;			\
       warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
     }									\
   if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128)			\
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h	(revision 191458)
+++ gcc/config/rs6000/rs6000.h	(working copy)
@@ -218,55 +218,55 @@ extern const char *host_detect_local_cpu
    optional field operand for mfcr.  */
 
 #ifndef HAVE_AS_MFCRF
-#undef  TARGET_MFCRF
-#define TARGET_MFCRF 0
+#undef  OPTION_MFCRF
+#define OPTION_MFCRF 0
 #endif
 
 /* Define TARGET_POPCNTB if the target assembler does not support the
    popcount byte instruction.  */
 
 #ifndef HAVE_AS_POPCNTB
-#undef  TARGET_POPCNTB
-#define TARGET_POPCNTB 0
+#undef  OPTION_POPCNTB
+#define OPTION_POPCNTB 0
 #endif
 
 /* Define TARGET_FPRND if the target assembler does not support the
    fp rounding instructions.  */
 
 #ifndef HAVE_AS_FPRND
-#undef  TARGET_FPRND
-#define TARGET_FPRND 0
+#undef  OPTION_FPRND
+#define OPTION_FPRND 0
 #endif
 
 /* Define TARGET_CMPB if the target assembler does not support the
    cmpb instruction.  */
 
 #ifndef HAVE_AS_CMPB
-#undef  TARGET_CMPB
-#define TARGET_CMPB 0
+#undef  OPTION_CMPB
+#define OPTION_CMPB 0
 #endif
 
 /* Define TARGET_MFPGPR if the target assembler does not support the
    mffpr and mftgpr instructions. */
 
 #ifndef HAVE_AS_MFPGPR
-#undef  TARGET_MFPGPR
-#define TARGET_MFPGPR 0
+#undef  OPTION_MFPGPR
+#define OPTION_MFPGPR 0
 #endif
 
 /* Define TARGET_DFP if the target assembler does not support decimal
    floating point instructions.  */
 #ifndef HAVE_AS_DFP
-#undef  TARGET_DFP
-#define TARGET_DFP 0
+#undef  OPTION_DFP
+#define OPTION_DFP 0
 #endif
 
 /* Define TARGET_POPCNTD if the target assembler does not support the
    popcount word and double word instructions.  */
 
 #ifndef HAVE_AS_POPCNTD
-#undef  TARGET_POPCNTD
-#define TARGET_POPCNTD 0
+#undef  OPTION_POPCNTD
+#define OPTION_POPCNTD 0
 #endif
 
 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync.  If
@@ -465,6 +465,93 @@ extern int rs6000_vector_align[];
 #define TARGET_FCTIDUZ	TARGET_POPCNTD
 #define TARGET_FCTIWUZ	TARGET_POPCNTD
 
+/* Map OPTION_<xxx> back into TARGET_<xxx> options in rs6000_isa_flags.  */
+#define TARGET_ALTIVEC			OPTION_ALTIVEC
+#define TARGET_CMPB			OPTION_CMPB
+#define TARGET_DFP			OPTION_DFP
+#define TARGET_DLMZB			OPTION_DLMZB
+#define TARGET_EABI			OPTION_EABI
+#define TARGET_FPRND			OPTION_FPRND
+#define TARGET_HARD_FLOAT		OPTION_HARD_FLOAT
+#define TARGET_ISEL			OPTION_ISEL
+#define TARGET_MFCRF			OPTION_MFCRF
+#define TARGET_MFPGPR			OPTION_MFPGPR
+#define TARGET_MULHW			OPTION_MULHW
+#define TARGET_MULTIPLE			OPTION_MULTIPLE
+#define TARGET_NO_UPDATE		OPTION_NO_UPDATE
+#define TARGET_POPCNTB			OPTION_POPCNTB
+#define TARGET_POPCNTD			OPTION_POPCNTD
+#define TARGET_PPC_GFXOPT		OPTION_PPC_GFXOPT
+#define TARGET_PPC_GPOPT		OPTION_PPC_GPOPT
+#define TARGET_RECIP_PRECISION		OPTION_RECIP_PRECISION
+#define TARGET_SOFT_FLOAT		OPTION_SOFT_FLOAT
+#define TARGET_STRICT_ALIGN		OPTION_STRICT_ALIGN
+#define TARGET_STRING			OPTION_STRING
+#define TARGET_UPDATE			OPTION_UPDATE
+#define TARGET_VSX			OPTION_VSX
+
+#define MASK_ALTIVEC			OPTION_MASK_ALTIVEC
+#define MASK_CMPB			OPTION_MASK_CMPB
+#define MASK_DFP			OPTION_MASK_DFP
+#define MASK_DLMZB			OPTION_MASK_DLMZB
+#define MASK_EABI			OPTION_MASK_EABI
+#define MASK_FPRND			OPTION_MASK_FPRND
+#define MASK_HARD_FLOAT			OPTION_MASK_HARD_FLOAT
+#define MASK_ISEL			OPTION_MASK_ISEL
+#define MASK_MFCRF			OPTION_MASK_MFCRF
+#define MASK_MFPGPR			OPTION_MASK_MFPGPR
+#define MASK_MULHW			OPTION_MASK_MULHW
+#define MASK_MULTIPLE			OPTION_MASK_MULTIPLE
+#define MASK_NO_UPDATE			OPTION_MASK_NO_UPDATE
+#define MASK_POPCNTB			OPTION_MASK_POPCNTB
+#define MASK_POPCNTD			OPTION_MASK_POPCNTD
+#define MASK_PPC_GFXOPT			OPTION_MASK_PPC_GFXOPT
+#define MASK_PPC_GPOPT			OPTION_MASK_PPC_GPOPT
+#define MASK_RECIP_PRECISION		OPTION_MASK_RECIP_PRECISION
+#define MASK_SOFT_FLOAT			OPTION_MASK_SOFT_FLOAT
+#define MASK_STRICT_ALIGN		OPTION_MASK_STRICT_ALIGN
+#define MASK_STRING			OPTION_MASK_STRING
+#define MASK_UPDATE			OPTION_MASK_UPDATE
+#define MASK_VSX			OPTION_MASK_VSX
+
+#ifndef IN_LIBGCC2
+#define TARGET_POWERPC64		OPTION_POWERPC64
+#define MASK_POWERPC64			OPTION_MASK_POWERPC64
+#endif
+
+#ifdef OPTION_64BIT
+#define TARGET_64BIT			OPTION_64BIT
+#define MASK_64BIT			OPTION_MASK_64BIT
+#endif
+
+#ifdef OPTION_RELOCATABLE
+#define TARGET_RELOCATABLE		OPTION_RELOCATABLE
+#define MASK_RELOCATABLE		OPTION_MASK_RELOCATABLE
+#endif
+
+#ifdef OPTION_LITTLE_ENDIAN
+#define TARGET_LITTLE_ENDIAN		OPTION_LITTLE_ENDIAN
+#define MASK_LITTLE_ENDIAN		OPTION_MASK_LITTLE_ENDIAN
+#endif
+
+#ifdef OPTION_MINIMAL_TOC
+#define TARGET_MINIMAL_TOC		OPTION_MINIMAL_TOC
+#define MASK_MINIMAL_TOC		OPTION_MASK_MINIMAL_TOC
+#endif
+
+#ifdef OPTION_REGNAMES
+#define TARGET_REGNAMES			OPTION_REGNAMES
+#define MASK_REGNAMES			OPTION_MASK_REGNAMES
+#endif
+
+#ifdef OPTION_PROTOTYPE
+#define TARGET_PROTOTYPE		OPTION_PROTOTYPE
+#define MASK_PROTOTYPE		OPTION_MASK_PROTOTYPE
+#endif
+
+/* Explicit ISA options that were set.  */
+#define rs6000_isa_flags_explicit	global_options_set.x_rs6000_isa_flags
+
 /* For power systems, we want to enable Altivec and VSX builtins even if the
    user did not use -maltivec or -mvsx to allow the builtins to be used inside
    of #pragma GCC target or the target attribute to change the code level for a
Index: gcc/config/rs6000/aix64.opt
===================================================================
--- gcc/config/rs6000/aix64.opt	(revision 191458)
+++ gcc/config/rs6000/aix64.opt	(working copy)
@@ -20,11 +20,11 @@
 ; <http://www.gnu.org/licenses/>.
 
 maix64
-Target Report RejectNegative Negative(maix32) Mask(64BIT)
+Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags)
 Compile for 64-bit pointers
 
 maix32
-Target Report RejectNegative Negative(maix64) InverseMask(64BIT)
+Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags)
 Compile for 32-bit pointers
 
 mpe
Index: gcc/config/rs6000/freebsd64.h
===================================================================
--- gcc/config/rs6000/freebsd64.h	(revision 191458)
+++ gcc/config/rs6000/freebsd64.h	(working copy)
@@ -57,7 +57,7 @@ extern int dot_symbols;
    -mrelocatable or -mrelocatable-lib is given.  */
 #undef RELOCATABLE_NEEDS_FIXUP
 #define RELOCATABLE_NEEDS_FIXUP \
-  (target_flags & target_flags_explicit & MASK_RELOCATABLE)
+  (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE)
 
 #undef  RS6000_ABI_NAME
 #define RS6000_ABI_NAME "freebsd"
@@ -79,14 +79,14 @@ extern int dot_symbols;
 	      error (INVALID_64BIT, "call");			\
 	    }							\
 	  dot_symbols = !strcmp (rs6000_abi_name, "aixdesc");	\
-	  if (target_flags & MASK_RELOCATABLE)			\
+	  if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE)	\
 	    {							\
-	      target_flags &= ~MASK_RELOCATABLE;		\
+	      rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE;	\
 	      error (INVALID_64BIT, "relocatable");		\
 	    }							\
-	  if (target_flags & MASK_EABI)				\
+	  if (rs6000_isa_flags & OPTION_MASK_EABI)		\
 	    {							\
-	      target_flags &= ~MASK_EABI;			\
+	      rs6000_isa_flags &= ~OPTION_MASK_EABI;		\
 	      error (INVALID_64BIT, "eabi");			\
 	    }							\
 	  if (TARGET_PROTOTYPE)					\
@@ -94,12 +94,13 @@ extern int dot_symbols;
 	      target_prototype = 0;				\
 	      error (INVALID_64BIT, "prototype");		\
 	    }							\
-	  if ((target_flags & MASK_POWERPC64) == 0)		\
+	  if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0)	\
 	    {							\
-	      target_flags |= MASK_POWERPC64;			\
+	      rs6000_isa_flags |= OPTION_MASK_POWERPC64;	\
 	      error ("-m64 requires a PowerPC64 cpu");		\
 	    }							\
-	   if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0)	\
+	   if ((rs6000_isa_flags_explicit			\
+		& OPTION_MASK_MINIMAL_TOC) != 0)		\
 	    {							\
 	      if (global_options_set.x_rs6000_current_cmodel	\
 		  && rs6000_current_cmodel != CMODEL_SMALL)	\
Index: gcc/config/rs6000/aix61.h
===================================================================
--- gcc/config/rs6000/aix61.h	(revision 191458)
+++ gcc/config/rs6000/aix61.h	(working copy)
@@ -26,7 +26,7 @@
 do {									\
   if (TARGET_64BIT && ! TARGET_POWERPC64)				\
     {									\
-      target_flags |= MASK_POWERPC64;					\
+      rs6000_isa_flags |= OPTION_MASK_POWERPC64;			\
       warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
     }									\
   if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128)			\
Index: gcc/config/rs6000/sysv4.opt
===================================================================
--- gcc/config/rs6000/sysv4.opt	(revision 191458)
+++ gcc/config/rs6000/sysv4.opt	(working copy)
@@ -49,12 +49,12 @@ Target Report Var(TARGET_NO_BITFIELD_TYP
 Align to the base type of the bit-field
 
 mstrict-align
-Target Report Mask(STRICT_ALIGN)
+Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags)
 Align to the base type of the bit-field
 Don't assume that unaligned accesses are handled by the system
 
 mrelocatable
-Target Report Mask(RELOCATABLE)
+Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags)
 Produce code relocatable at runtime
 
 mrelocatable-lib
@@ -62,19 +62,19 @@ Target
 Produce code relocatable at runtime
 
 mlittle-endian
-Target Report RejectNegative Mask(LITTLE_ENDIAN)
+Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
 Produce little endian code
 
 mlittle
-Target Report RejectNegative Mask(LITTLE_ENDIAN)
+Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
 Produce little endian code
 
 mbig-endian
-Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
+Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
 Produce big endian code
 
 mbig
-Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
+Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
 Produce big endian code
 
 ;; FIXME: This does nothing.  What should be done?
@@ -96,7 +96,7 @@ Target RejectNegative
 no description yet
 
 meabi
-Target Report Mask(EABI)
+Target Report Mask(EABI) Var(rs6000_isa_flags)
 Use EABI
 
 mbit-word
@@ -138,11 +138,11 @@ Target RejectNegative
 no description yet
 
 m64
-Target Report RejectNegative Negative(m32) Mask(64BIT)
+Target Report RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags)
 Generate 64-bit code
 
 m32
-Target Report RejectNegative Negative(m64) InverseMask(64BIT)
+Target Report RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags)
 Generate 32-bit code
 
 mnewlib
Index: gcc/config/rs6000/rs6000-cpus.def
===================================================================
--- gcc/config/rs6000/rs6000-cpus.def	(revision 191458)
+++ gcc/config/rs6000/rs6000-cpus.def	(working copy)
@@ -18,6 +18,57 @@
    along with GCC; see the file COPYING3.  If not see
    <http://www.gnu.org/licenses/>.  */
 
+/* ISA masks.  */
+#ifndef ISA_2_1_MASKS
+#define ISA_2_1_MASKS		OPTION_MASK_MFCRF
+#define ISA_2_2_MASKS		(ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
+#define ISA_2_4_MASKS		(ISA_2_2_MASKS | OPTION_MASK_FPRND)
+
+  /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
+     ALTIVEC, since in general it isn't a win on power6.  In ISA 2.04, fsel,
+     fre, fsqrt, etc. were no longer documented as optional.  Group masks by
+     server and embedded. */
+#define ISA_2_5_MASKS_EMBEDDED	(ISA_2_2_MASKS				\
+				 | OPTION_MASK_CMPB			\
+				 | OPTION_MASK_RECIP_PRECISION		\
+				 | OPTION_MASK_PPC_GFXOPT		\
+				 | OPTION_MASK_PPC_GPOPT)
+
+#define ISA_2_5_MASKS_SERVER	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)
+
+  /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
+     altivec is a win so enable it.  */
+#define ISA_2_6_MASKS_EMBEDDED	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
+#define ISA_2_6_MASKS_SERVER	(ISA_2_5_MASKS_SERVER			\
+				 | OPTION_MASK_POPCNTD			\
+				 | OPTION_MASK_ALTIVEC			\
+				 | OPTION_MASK_VSX)
+
+#define POWERPC_7400_MASK	(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
+
+/* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
+#define POWERPC_MASKS		(OPTION_MASK_ALTIVEC			\
+				 | OPTION_MASK_CMPB			\
+				 | OPTION_MASK_DFP			\
+				 | OPTION_MASK_DLMZB			\
+				 | OPTION_MASK_FPRND			\
+				 | OPTION_MASK_ISEL			\
+				 | OPTION_MASK_MFCRF			\
+				 | OPTION_MASK_MFPGPR			\
+				 | OPTION_MASK_MULHW			\
+				 | OPTION_MASK_NO_UPDATE		\
+				 | OPTION_MASK_POPCNTB			\
+				 | OPTION_MASK_POPCNTD			\
+				 | OPTION_MASK_POWERPC64		\
+				 | OPTION_MASK_PPC_GFXOPT		\
+				 | OPTION_MASK_PPC_GPOPT		\
+				 | OPTION_MASK_RECIP_PRECISION		\
+				 | OPTION_MASK_SOFT_FLOAT		\
+				 | OPTION_MASK_STRICT_ALIGN		\
+				 | OPTION_MASK_VSX)
+
+#endif
+
 /* This table occasionally claims that a processor does not support a
    particular feature even though it does, but the feature is slower than the
    alternative.  Thus, it shouldn't be relied on as a complete description of
Index: gcc/config/rs6000/freebsd.h
===================================================================
--- gcc/config/rs6000/freebsd.h	(revision 191458)
+++ gcc/config/rs6000/freebsd.h	(working copy)
@@ -72,7 +72,7 @@
    -mrelocatable or -mrelocatable-lib is given.  */
 #undef RELOCATABLE_NEEDS_FIXUP
 #define RELOCATABLE_NEEDS_FIXUP \
-  (target_flags & target_flags_explicit & MASK_RELOCATABLE)
+  (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE)
 
 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
 
Index: gcc/config/rs6000/option-defaults.h
===================================================================
--- gcc/config/rs6000/option-defaults.h	(revision 191458)
+++ gcc/config/rs6000/option-defaults.h	(working copy)
@@ -35,11 +35,12 @@
 #define OPT_32 "m32"
 #endif
 
-#ifndef MASK_64BIT
+#ifndef OPTION_MASK_64BIT
+#define OPTION_MASK_64BIT 0
 #define MASK_64BIT 0
 #endif
 
-#if TARGET_DEFAULT & MASK_64BIT
+#if TARGET_DEFAULT & OPTION_MASK_64BIT
 #define OPT_ARCH64 "!"OPT_32
 #define OPT_ARCH32 OPT_32
 #else
Index: gcc/config/rs6000/rs6000-protos.h
===================================================================
--- gcc/config/rs6000/rs6000-protos.h	(revision 191458)
+++ gcc/config/rs6000/rs6000-protos.h	(working copy)
@@ -176,7 +176,7 @@ extern void rs6000_call_indirect_aix (rt
 extern void rs6000_aix_asm_output_dwarf_table_ref (char *);
 extern void get_ppc476_thunk_name (char name[32]);
 extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins);
-extern unsigned rs6000_builtin_mask_calculate (void);
+extern HOST_WIDE_INT rs6000_builtin_mask_calculate (void);
 
 /* Declare functions in rs6000-c.c */
 
@@ -185,8 +185,9 @@ extern void rs6000_cpu_cpp_builtins (str
 #ifdef TREE_CODE
 extern bool rs6000_pragma_target_parse (tree, tree);
 #endif
-extern void rs6000_target_modify_macros (bool, int, unsigned);
-extern void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned);
+extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT, HOST_WIDE_INT);
+extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT,
+						HOST_WIDE_INT);
 
 #if TARGET_MACHO
 char *output_call (rtx, rtx *, int, int);
Index: gcc/config/rs6000/aix51.h
===================================================================
--- gcc/config/rs6000/aix51.h	(revision 191458)
+++ gcc/config/rs6000/aix51.h	(working copy)
@@ -26,7 +26,7 @@
 do {									\
   if (TARGET_64BIT && ! TARGET_POWERPC64)				\
     {									\
-      target_flags |= MASK_POWERPC64;					\
+      rs6000_isa_flags |= OPTION_MASK_POWERPC64;			\
       warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
     }									\
   if (TARGET_POWERPC64 && ! TARGET_64BIT)				\
Index: gcc/config/rs6000/sysv4.h
===================================================================
--- gcc/config/rs6000/sysv4.h	(revision 191458)
+++ gcc/config/rs6000/sysv4.h	(working copy)
@@ -40,9 +40,10 @@
 #undef	ASM_DEFAULT_SPEC
 #define	ASM_DEFAULT_SPEC "-mppc"
 
-#define	TARGET_TOC		((target_flags & MASK_64BIT)		\
-				 || ((target_flags & (MASK_RELOCATABLE	\
-						      | MASK_MINIMAL_TOC)) \
+#define	TARGET_TOC		((rs6000_isa_flags & OPTION_MASK_64BIT)	\
+				 || ((rs6000_isa_flags			\
+				      & (OPTION_MASK_RELOCATABLE	\
+					 | OPTION_MASK_MINIMAL_TOC))	\
 				     && flag_pic > 1)			\
 				 || DEFAULT_ABI == ABI_AIX)
 
@@ -77,13 +78,13 @@ do {									\
   else if (!strcmp (rs6000_abi_name, "sysv-noeabi"))			\
     {									\
       rs6000_current_abi = ABI_V4;					\
-      target_flags &= ~ MASK_EABI;					\
+      rs6000_isa_flags &= ~ OPTION_MASK_EABI;				\
     }									\
   else if (!strcmp (rs6000_abi_name, "sysv-eabi")			\
 	   || !strcmp (rs6000_abi_name, "eabi"))			\
     {									\
       rs6000_current_abi = ABI_V4;					\
-      target_flags |= MASK_EABI;					\
+      rs6000_isa_flags |= OPTION_MASK_EABI;				\
     }									\
   else if (!strcmp (rs6000_abi_name, "aixdesc"))			\
     rs6000_current_abi = ABI_AIX;					\
@@ -102,8 +103,8 @@ do {									\
   else if (!strcmp (rs6000_abi_name, "i960-old"))			\
     {									\
       rs6000_current_abi = ABI_V4;					\
-      target_flags |= (MASK_LITTLE_ENDIAN | MASK_EABI);			\
-      target_flags &= ~MASK_STRICT_ALIGN;				\
+      rs6000_isa_flags |= (OPTION_MASK_LITTLE_ENDIAN | OPTION_MASK_EABI); \
+      rs6000_isa_flags &= ~OPTION_MASK_STRICT_ALIGN;			\
       TARGET_NO_BITFIELD_WORD = 1;					\
     }									\
   else									\
@@ -168,13 +169,13 @@ do {									\
 									\
   if (TARGET_RELOCATABLE && !TARGET_MINIMAL_TOC)			\
     {									\
-      target_flags |= MASK_MINIMAL_TOC;					\
+      rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;			\
       error ("-mrelocatable and -mno-minimal-toc are incompatible");	\
     }									\
 									\
   if (TARGET_RELOCATABLE && rs6000_current_abi == ABI_AIX)		\
     {									\
-      target_flags &= ~MASK_RELOCATABLE;				\
+      rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE;			\
       error ("-mrelocatable and -mcall-%s are incompatible",		\
 	     rs6000_abi_name);						\
     }									\
@@ -188,7 +189,7 @@ do {									\
 									\
   if (rs6000_current_abi == ABI_AIX && TARGET_LITTLE_ENDIAN)		\
     {									\
-      target_flags &= ~MASK_LITTLE_ENDIAN;				\
+      rs6000_isa_flags &= ~OPTION_MASK_LITTLE_ENDIAN;			\
       error ("-mcall-aixdesc must be big endian");			\
     }									\
 									\
@@ -200,7 +201,7 @@ do {									\
   /* Treat -fPIC the same as -mrelocatable.  */				\
   if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX)				\
     {									\
-      target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;		\
+      rs6000_isa_flags |= OPTION_MASK_RELOCATABLE | OPTION_MASK_MINIMAL_TOC; \
       TARGET_NO_FP_IN_TOC = 1;						\
     }									\
 									\
@@ -212,9 +213,9 @@ do {									\
 #ifndef RS6000_BI_ARCH
 # define SUBSUBTARGET_OVERRIDE_OPTIONS					\
 do {									\
-  if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)			\
+  if ((TARGET_DEFAULT ^ rs6000_isa_flags) & OPTION_MASK_64BIT)		\
     error ("-m%s not supported in this configuration",			\
-	   (target_flags & MASK_64BIT) ? "64" : "32");			\
+	   (rs6000_isa_flags & OPTION_MASK_64BIT) ? "64" : "32");	\
 } while (0)
 #endif
 
@@ -500,8 +501,8 @@ extern int fixuplabelno;
 #define TARGET_OS_SYSV_CPP_BUILTINS()		\
   do						\
     {						\
-      if (target_flags_explicit			\
-	  & MASK_RELOCATABLE)			\
+      if (rs6000_isa_flags_explicit		\
+	  & OPTION_MASK_RELOCATABLE)		\
 	builtin_define ("_RELOCATABLE");	\
     }						\
   while (0)
Index: gcc/common/config/rs6000/rs6000-common.c
===================================================================
--- gcc/common/config/rs6000/rs6000-common.c	(revision 191458)
+++ gcc/common/config/rs6000/rs6000-common.c	(working copy)
@@ -82,23 +82,23 @@ rs6000_handle_option (struct gcc_options
   switch (code)
     {
     case OPT_mfull_toc:
-      opts->x_target_flags &= ~MASK_MINIMAL_TOC;
+      opts->x_rs6000_isa_flags &= ~OPTION_MASK_MINIMAL_TOC;
       opts->x_TARGET_NO_FP_IN_TOC = 0;
       opts->x_TARGET_NO_SUM_IN_TOC = 0;
-      opts_set->x_target_flags |= MASK_MINIMAL_TOC;
+      opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
 #ifdef TARGET_USES_SYSV4_OPT
       /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
 	 just the same as -mminimal-toc.  */
-      opts->x_target_flags |= MASK_MINIMAL_TOC;
-      opts_set->x_target_flags |= MASK_MINIMAL_TOC;
+      opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
+      opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
 #endif
       break;
 
 #ifdef TARGET_USES_SYSV4_OPT
     case OPT_mtoc:
       /* Make -mtoc behave like -mminimal-toc.  */
-      opts->x_target_flags |= MASK_MINIMAL_TOC;
-      opts_set->x_target_flags |= MASK_MINIMAL_TOC;
+      opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
+      opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
       break;
 #endif
 
@@ -107,9 +107,10 @@ rs6000_handle_option (struct gcc_options
 #else
     case OPT_m64:
 #endif
-      opts->x_target_flags |= MASK_POWERPC64;
-      opts->x_target_flags |= ~opts_set->x_target_flags & MASK_PPC_GFXOPT;
-      opts_set->x_target_flags |= MASK_POWERPC64;
+      opts->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64;
+      opts->x_rs6000_isa_flags |= (~opts_set->x_rs6000_isa_flags
+				   & OPTION_MASK_PPC_GFXOPT);
+      opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64;
       break;
 
 #ifdef TARGET_USES_AIX64_OPT
@@ -117,8 +118,8 @@ rs6000_handle_option (struct gcc_options
 #else
     case OPT_m32:
 #endif
-      opts->x_target_flags &= ~MASK_POWERPC64;
-      opts_set->x_target_flags |= MASK_POWERPC64;
+      opts->x_rs6000_isa_flags &= ~OPTION_MASK_POWERPC64;
+      opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64;
       break;
 
     case OPT_mminimal_toc:
@@ -181,8 +182,8 @@ rs6000_handle_option (struct gcc_options
     case OPT_mrelocatable:
       if (value == 1)
 	{
-	  opts->x_target_flags |= MASK_MINIMAL_TOC;
-	  opts_set->x_target_flags |= MASK_MINIMAL_TOC;
+	  opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
+	  opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
 	  opts->x_TARGET_NO_FP_IN_TOC = 1;
 	}
       break;
@@ -190,14 +191,16 @@ rs6000_handle_option (struct gcc_options
     case OPT_mrelocatable_lib:
       if (value == 1)
 	{
-	  opts->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
-	  opts_set->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
+	  opts->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE
+				       | OPTION_MASK_MINIMAL_TOC);
+	  opts_set->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE
+					   | OPTION_MASK_MINIMAL_TOC);
 	  opts->x_TARGET_NO_FP_IN_TOC = 1;
 	}
       else
 	{
-	  opts->x_target_flags &= ~MASK_RELOCATABLE;
-	  opts_set->x_target_flags |= MASK_RELOCATABLE;
+	  opts->x_rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE;
+	  opts_set->x_rs6000_isa_flags |= OPTION_MASK_RELOCATABLE;
 	}
       break;
 #endif
@@ -227,15 +230,15 @@ rs6000_handle_option (struct gcc_options
 		    "-msingle-float option equivalent to -mhard-float");
       /* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */
       opts->x_rs6000_double_float = 0;
-      opts->x_target_flags &= ~MASK_SOFT_FLOAT;
-      opts_set->x_target_flags |= MASK_SOFT_FLOAT;
+      opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
+      opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
       break;
 
     case OPT_mdouble_float:
       /* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */
       opts->x_rs6000_single_float = 1;
-      opts->x_target_flags &= ~MASK_SOFT_FLOAT;
-      opts_set->x_target_flags |= MASK_SOFT_FLOAT;
+      opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
+      opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
       break;
 
     case OPT_msimple_fpu:
@@ -259,8 +262,8 @@ rs6000_handle_option (struct gcc_options
 	{
 	  /* If -mfpu is not none, then turn off SOFT_FLOAT, turn on
 	     HARD_FLOAT. */
-	  opts->x_target_flags &= ~MASK_SOFT_FLOAT;
-	  opts_set->x_target_flags |= MASK_SOFT_FLOAT;
+	  opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
+	  opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
 	  opts->x_rs6000_xilinx_fpu = 1;
 	  if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL) 
 	    opts->x_rs6000_single_float = 1;
@@ -272,8 +275,8 @@ rs6000_handle_option (struct gcc_options
       else
 	{
 	  /* -mfpu=none is equivalent to -msoft-float.  */
-	  opts->x_target_flags |= MASK_SOFT_FLOAT;
-	  opts_set->x_target_flags |= MASK_SOFT_FLOAT;
+	  opts->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
+	  opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
 	  opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0;
 	}
       break;
@@ -297,8 +300,4 @@ rs6000_handle_option (struct gcc_options
 #undef TARGET_OPTION_OPTIMIZATION_TABLE
 #define TARGET_OPTION_OPTIMIZATION_TABLE rs6000_option_optimization_table
 
-#undef TARGET_DEFAULT_TARGET_FLAGS
-#define TARGET_DEFAULT_TARGET_FLAGS \
-  (TARGET_DEFAULT)
-
 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;