This patch adds new builtins for power8.

Code generation support for the new VSX logical instructions (xxleqv, xxlnand,
and xxlorc) is added.

In reworking the patch for posting in smaller chunks, I discvered a bug in the
int_reg_operand operand added in a previous patch, and I have fixed it here.

In addition, it reworks the VSX logical operations to generate code when a GPR
is selected instead of a VSX register when quad memory instructions are enabled
in a future patch.

The next patch will provide the tests for this patch (#4) and the previous
patch (#3).

As before, it bootstraps, and has no regressions.  Is it ok to check in once
the previous 3 patches have been applied?

2013-05-21  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
	Document new power8 builtins.

	* config/rs6000/vector.md (gpr move splitter): Do not split direct
	moves or quad word load/stores.
	(and<mode>3): Add a clobber/scratch of a condition code register,
	so TImode logical operations can be done either in VSX registers
	or GPRs.
	(eqv<mode>3): Add expanders for power8 xxleqv, xxlnand, xxlorc,
	vclz*, and vpopcnt* vector instructions.

	* config/rs6000/rs6000-builtin.def (xscvspdpn): Add new power8
	builtin functions.
	(xscvdpspn): Likewise.
	(vclzb): Likewise.
	(vclzh): Likewise.
	(vclzw): Likewise.
	(vclzd): Likewise.
	(vpopcntb): Likewise.
	(vpopcnth): Likewise.
	(vpopcntw): Likewise.
	(vpopcntd): Likewise.
	(vgbbd): Likewise.
	(vmrgew): Likewise.
	(vmrgow): Likewise.
	(eqv_v16qi3): Likewise.
	(eqv_v8hi3): Likewise.
	(eqv_v4si3): Likewise.
	(eqv_v2di3): Likewise.
	(eqv_v4sf3): Likewise.
	(eqv_v2df3): Likewise.
	(nand_v16qi3): Likewise.
	(nand_v8hi3): Likewise.
	(nand_v4si3): Likewise.
	(nand_v2di3): Likewise.
	(nand_v4sf3): Likewise.
	(nand_v2df3): Likewise.
	(orc_v16qi3): Likewise.
	(orc_v8hi3): Likewise.
	(orc_v4si3): Likewise.
	(orc_v2di3): Likewise.
	(orc_v4sf3): Likewise.
	(orc_v2df3): Likewise.
	(vclz): Likewise.
	(vclzb): Likewise.
	(vclzh): Likewise.
	(vclzw): Likewise.
	(vclzd): Likewise.
	(vpopcnt): Likewise.
	(vpopcntb): Likewise.
	(vpopcnth): Likewise.
	(vpopcntw): Likewise.
	(vpopcntd): Likewise.
	(vgbbd): Likewise.
	(eqv): Likewise.
	(nand): Likewise.
	(orc): Likewise.
	(vmrgew): Likewise.
	(vmrgow): Likewise.

	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
	support for new power8 builtins.

	* config/rs6000/rs6000.c (rs6000_option_override_internal): Only
	allow power8 quad mode in 64-bit.  Turn off splitting wide types
	if we have quad mode.
	(rs6000_builtin_vectorized_function): Vectorize count leading
	zeros, population count builtins.
	(rs6000_expand_vector_init): On power8 use xscvdpspn to form V4SF
	vectors instead of xscvdpsp to avoid IEEE related traps.
	(builtin_function_type): Add vgbbd builtin function which takes an
	unsigned argument.
	(altivec_expand_vec_perm_const): Add support for new power8 merge
	instructions.

	* config/rs6000/vsx.md (VSX_M2): New iterator that includes
	TImode.
	(UNSPEC_VSX_CVSPDPN): Support for power8 xscvdpspn and xscvspdpn
	instructions.
	(UNSPEC_VSX_CVDPSPN): Likewise.
	(vsx_xscvdpspn): Likewise.
	(vsx_xscvspdpn): Likewise.
	(vsx_xscvdpspn_scalar): Likewise.
	(vsx_xscvspdpn_directmove): Likewise.
	(vsx_and<mode>3): Add support to do logical operations on TImode
	as well as VSX vector types.  Allow logical operations to be done
	in either VSX registers or in general purpose registers if we
	support quad mode in GPRs.  Add splitters if GPRs were used.  For
	and, add clobber of CCmode to allow use of ANDI on GPRs.
	(vsx_or_gpr_and<mode>3): Likewise.
	(vsx_ior<mode>3): Likewise.
	(vsx_or_gpr_ior<mode>3): Likewise.
	(vsx_xor<mode>3): Likewise.
	(vsx_or_gpr_xor<mode>3): Likewise.
	(vsx_one_cmpl<mode>2): Likewise.
	(vsx_or_gpr_one_cmpl<mode>2): Likewise.
	(vsx_nor<mode>3): Likewise.
	(vsx_or_gpr_nor<mode>3): Likewise.
	(vsx_andc<mode>3): Likewise.
	(vsx_or_gpr_andc<mode>3): Likewise.
	(vsx_eqv<mode>3): Add support for power8 xxleqv, xxlnand, and
	xxlorc instructions.
	(vsx_or_gpr_eqv<mode>3): Likewise.
	(vsx_nand<mode>3): Likewise.
	(vsx_or_gpr_nand<mode>3): Likewise.
	(vsx_orc<mode>3): Likewise.
	(vsx_or_gpr_orc<mode>3): Likewise.

	* config/rs6000/altivec.md (p8_vmrgew): Add power8 vmrgew and
	vmrgow instructions.
	(p8_vmrgow): Likewise.
	(altivec_and<mode>3): Add clobber of CCmode to allow AND using
	GPRs to be split under VSX.
	(p8v_clz<mode>2): Add power8 count leading zero support.
	(p8v_popcount<mode>2): Add power8 population count support.
	(p8v_vgbbd): Add power8 gather bits by bytes by doubleword
	support.

	* config/rs6000/altivec.h (vec_eqv): Add defines to export power8
	builtin functions.
	(vec_nand): Likewise.
	(vec_vclz): Likewise.
	(vec_vclzb): Likewise.
	(vec_vclzd): Likewise.
	(vec_vclzh): Likewise.
	(vec_vclzw): Likewise.
	(vec_vgbbd): Likewise.
	(vec_vmrgew): Likewise.
	(vec_vmrgow): Likewise.
	(vec_vpopcnt): Likewise.
	(vec_vpopcntb): Likewise.
	(vec_vpopcntd): Likewise.
	(vec_vpopcnth): Likewise.
	(vec_vpopcntw): Likewise.

	* config/rs6000/predicates.md (int_reg_operand): Rework tests so
	that only the GPRs are recognized.

	* config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Only allow logical
	operations in GPRs if we are supporting quad memory mode.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797