Re: [PATCH, rs6000] power8 patches, patch #4, new power8 builtins

[Michael Meissner <meissner@linux.vnet.ibm.com>]

On Sat, May 25, 2013 at 12:03:51AM -0400, David Edelsohn wrote:
> On Tue, May 21, 2013 at 7:47 PM, Michael Meissner
> <meissner@linux.vnet.ibm.com> wrote:
> 
> 
> >         * config/rs6000/rs6000.c (rs6000_option_override_internal): Only
> >         allow power8 quad mode in 64-bit.  Turn off splitting wide types
> >         if we have quad mode.
> 
> Completely turning off splitting wide types seems like an
> unnecessarily large hammer to prevent splitting a value across
> registers within logical atomic operations.  I think we need to
> examine other alternatives.

Ok, I tracked down what the problem is.  We never implemented the EQV, ORC, or
NAND insns in the GPRs.  When I added the power8 vector versions, the split
wide types pass tried to do its thing in the GPRs, it creates a bad insn. I
originally saw it in the atomic ops, because I was testing all of the
combinations provided, but I can reproduce it just by using __int128_t.

In looking at the code, we don't seem to implement nor of two values either.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797