From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31253 invoked by alias); 30 May 2013 23:26:18 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 31243 invoked by uid 89); 30 May 2013 23:26:17 -0000 X-Spam-SWARE-Status: No, score=-3.7 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,RCVD_IN_HOSTKARMA_W,RCVD_IN_HOSTKARMA_WL autolearn=ham version=3.3.1 Received: from e9.ny.us.ibm.com (HELO e9.ny.us.ibm.com) (32.97.182.139) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Thu, 30 May 2013 23:26:16 +0000 Received: from /spool/local by e9.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 30 May 2013 19:26:15 -0400 Received: from d01dlp03.pok.ibm.com (9.56.250.168) by e9.ny.us.ibm.com (192.168.1.109) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Thu, 30 May 2013 19:26:13 -0400 Received: from d01relay04.pok.ibm.com (d01relay04.pok.ibm.com [9.56.227.236]) by d01dlp03.pok.ibm.com (Postfix) with ESMTP id 2F5F1C90026 for ; Thu, 30 May 2013 19:26:12 -0400 (EDT) Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by d01relay04.pok.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r4UNQCoo290688 for ; Thu, 30 May 2013 19:26:12 -0400 Received: from d03av02.boulder.ibm.com (loopback [127.0.0.1]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r4UNQBNa010398 for ; Thu, 30 May 2013 17:26:11 -0600 Received: from ibm-tiger.the-meissners.org (dhcp-9-32-77-206.usma.ibm.com [9.32.77.206]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id r4UNQA5T010346; Thu, 30 May 2013 17:26:10 -0600 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 1484842664; Thu, 30 May 2013 19:26:09 -0400 (EDT) Date: Thu, 30 May 2013 23:26:00 -0000 From: Michael Meissner To: David Edelsohn Cc: Michael Meissner , GCC Patches , Pat Haugen , Peter Bergner Subject: Re: [PATCH, rs6000] power8 patches, patch #4, new power8 builtins Message-ID: <20130530232609.GA32097@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , David Edelsohn , GCC Patches , Pat Haugen , Peter Bergner References: <20130520204053.GA21090@ibm-tiger.the-meissners.org> <20130521234717.GA27879@ibm-tiger.the-meissners.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13053023-7182-0000-0000-0000070A0C3E X-SW-Source: 2013-05/txt/msg01820.txt.bz2 On Sat, May 25, 2013 at 12:03:51AM -0400, David Edelsohn wrote: > On Tue, May 21, 2013 at 7:47 PM, Michael Meissner > wrote: > > > > * config/rs6000/rs6000.c (rs6000_option_override_internal): Only > > allow power8 quad mode in 64-bit. Turn off splitting wide types > > if we have quad mode. > > Completely turning off splitting wide types seems like an > unnecessarily large hammer to prevent splitting a value across > registers within logical atomic operations. I think we need to > examine other alternatives. Ok, I tracked down what the problem is. We never implemented the EQV, ORC, or NAND insns in the GPRs. When I added the power8 vector versions, the split wide types pass tried to do its thing in the GPRs, it creates a bad insn. I originally saw it in the atomic ops, because I was testing all of the combinations provided, but I can reproduce it just by using __int128_t. In looking at the code, we don't seem to implement nor of two values either. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797