I revised this patch for power8 to add new miscellaneous vector instructions to not turn off splitting wide moves. In doing the patch, I discovered that we never supported the 'eqv' instruction, and I have added support for eqv in the GPR registers. I also fixed the issue David raised in patch #2, that I did not protect the crypt tests in case an assembler that does not understand ISA 2.07 instructions was used to build the compiler. I brought in the changes to target-supports.exp from patch #5 to fix this. This patch bootstraps and causes no regressions, is it ok to check in? [gcc] 2013-06-04 Michael Meissner Pat Haugen Peter Bergner * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Document new power8 builtins. * config/rs6000/vector.md (and3): Add a clobber/scratch of a condition code register, so TImode logical operations can be done either in VSX registers or GPRs. (nor3): Use the canonical form for nor. (eqv3): Add expanders for power8 xxleqv, xxlnand, xxlorc, vclz*, and vpopcnt* vector instructions. (nand3): Likewise. (orc3): Likewise. (clz2): LIkewise. (popcount2): Likewise. * config/rs6000/predicates.md (int_reg_operand): Rework tests so that only the GPRs are recognized. * config/rs6000/rs6000-builtin.def (xscvspdpn): Add new power8 builtin functions. (xscvdpspn): Likewise. (vclzb): Likewise. (vclzh): Likewise. (vclzw): Likewise. (vclzd): Likewise. (vpopcntb): Likewise. (vpopcnth): Likewise. (vpopcntw): Likewise. (vpopcntd): Likewise. (vgbbd): Likewise. (vmrgew): Likewise. (vmrgow): Likewise. (eqv_v16qi3): Likewise. (eqv_v8hi3): Likewise. (eqv_v4si3): Likewise. (eqv_v2di3): Likewise. (eqv_v4sf3): Likewise. (eqv_v2df3): Likewise. (nand_v16qi3): Likewise. (nand_v8hi3): Likewise. (nand_v4si3): Likewise. (nand_v2di3): Likewise. (nand_v4sf3): Likewise. (nand_v2df3): Likewise. (orc_v16qi3): Likewise. (orc_v8hi3): Likewise. (orc_v4si3): Likewise. (orc_v2di3): Likewise. (orc_v4sf3): Likewise. (orc_v2df3): Likewise. (vclz): Likewise. (vclzb): Likewise. (vclzh): Likewise. (vclzw): Likewise. (vclzd): Likewise. (vpopcnt): Likewise. (vpopcntb): Likewise. (vpopcnth): Likewise. (vpopcntw): Likewise. (vpopcntd): Likewise. (vgbbd): Likewise. (eqv): Likewise. (nand): Likewise. (orc): Likewise. (vmrgew): Likewise. (vmrgow): Likewise. * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add support for new power8 builtins. * config/rs6000/rs6000.c (rs6000_option_override_internal): Only allow power8 quad mode in 64-bit. (rs6000_builtin_vectorized_function): Vectorize count leading zeros, population count builtins. (rs6000_expand_vector_init): On power8 use xscvdpspn to form V4SF vectors instead of xscvdpsp to avoid IEEE related traps. (builtin_function_type): Add vgbbd builtin function which takes an unsigned argument. (altivec_expand_vec_perm_const): Add support for new power8 merge instructions. * config/rs6000/vsx.md (VSX_L2): New iterator for 128-bit types, that does not include TImdoe for use with 32-bit. (UNSPEC_VSX_CVSPDPN): Support for power8 xscvdpspn and xscvspdpn instructions. (UNSPEC_VSX_CVDPSPN): Likewise. (vsx_xscvdpspn): Likewise. (vsx_xscvspdpn): Likewise. (vsx_xscvdpspn_scalar): Likewise. (vsx_xscvspdpn_directmove): Likewise. (vsx_and3): Split logical operations into 32-bit and 64-bit. Add support to do logical operations on TImode as well as VSX vector types. Allow logical operations to be done in either VSX registers or in general purpose registers in 64-bit mode. Add splitters if GPRs were used. For and, add clobber of CCmode to allow use of ANDI on GPRs. (vsx_and3_32bit): Likewise. (vsx_and3_64bit): Likewise. (vsx_ior3): Likewise. (vsx_ior3_32bit): Likewise. (vsx_ior3_64bit): Likewise. (vsx_xor3): Likewise. (vsx_xor3_32bit): Likewise. (vsx_xor3_64bit): Likewise. (vsx_one_cmpl2): Likewise. (vsx_one_cmpl2_32bit): Likewise. (vsx_one_cmpl2_64bit): Likewise. (vsx_nor3): Likewise. (vsx_nor3_32bit): Likewise. (vsx_nor3_64bit): Likewise. (vsx_andc3): Likewise. (vsx_andc3_32bit): Likewise. (vsx_andc3_64bit): Likewise. (vsx_eqv3_32bit): Add support for power8 xxleqv, xxlnand, and xxlorc instructions. (vsx_eqv3_64bit): Likewise. (vsx_nand3_32bit): Likewise. (vsx_nand3_64bit): Likewise. (vsx_orc3_32bit): Likewise. (vsx_orc3_64bit): Likewise. * config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Update comment. * config/rs6000/altivec.md (UNSPEC_VGBBD): Add power8 vgbbd instruction. (p8_vmrgew): Add power8 vmrgew and vmrgow instructions. (p8_vmrgow): Likewise. (altivec_and3): Add clobber of CCmode to allow AND using GPRs to be split under VSX. (p8v_clz2): Add power8 count leading zero support. (p8v_popcount2): Add power8 population count support. (p8v_vgbbd): Add power8 gather bits by bytes by doubleword support. * config/rs6000/rs6000.md (eqv3): Add support for powerp eqv instruction. * config/rs6000/altivec.h (vec_eqv): Add defines to export power8 builtin functions. (vec_nand): Likewise. (vec_vclz): Likewise. (vec_vclzb): Likewise. (vec_vclzd): Likewise. (vec_vclzh): Likewise. (vec_vclzw): Likewise. (vec_vgbbd): Likewise. (vec_vmrgew): Likewise. (vec_vmrgow): Likewise. (vec_vpopcnt): Likewise. (vec_vpopcntb): Likewise. (vec_vpopcntd): Likewise. (vec_vpopcnth): Likewise. (vec_vpopcntw): Likewise. [gcc/testsuite] 2013-06-04 Michael Meissner Pat Haugen Peter Bergner * gcc.target/powerpc/bool.c: New file, add eqv, nand, nor tests. * gcc.target/powerpc/crypto-builtin-1.c: Use effective target powerpc_p8vector_ok instead of powerpc_vsx_ok. * lib/target-supports.exp (check_p8vector_hw_available) Add power8 support. (check_effective_target_powerpc_p8vector_ok): Likewise. (is-effective-target): Likewise. (check_vect_support_and_set_flags): Likewise. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797