From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 3619 invoked by alias); 9 Apr 2014 02:56:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 3609 invoked by uid 89); 9 Apr 2014 02:56:45 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gate.crashing.org Received: from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 09 Apr 2014 02:56:43 +0000 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id s392uaom022719; Tue, 8 Apr 2014 21:56:37 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id s392uaFa022718; Tue, 8 Apr 2014 21:56:36 -0500 Date: Wed, 09 Apr 2014 02:56:00 -0000 From: segher@kernel.crashing.org To: Pat Haugen Cc: GCC Patches , David Edelsohn Subject: Re: [PATCH, rs6000] Improve TImode add/sub Message-ID: <20140409025635.GA22176@gate.crashing.org> References: <53448F22.6000309@linux.vnet.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <53448F22.6000309@linux.vnet.ibm.com> User-Agent: Mutt/1.4.2.3i X-IsSubscribed: yes X-SW-Source: 2014-04/txt/msg00404.txt.bz2 Hello, On Tue, Apr 08, 2014 at 07:06:58PM -0500, Pat Haugen wrote: > The following patch improves the code generated for TImode add/sub so > that we now generate a 2 insn sequence which makes use of the carry bit. > +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ > +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ Please leave out the default arguments. Why does this need skipping on Darwin? > +;; Define the TImode operations that can be done in a small number > +;; of instructions. The & constraints are to prevent the register > +;; allocator from allocating registers that overlap with the inputs > +;; (for example, having an input in 7,8 and an output in 6,7). We > +;; also allow for the output being the same as one of the inputs. > + > +(define_insn "addti3" > + [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r") > + (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0") > + (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))] > + "TARGET_POWERPC64" That's not the correct condition: the carry bit is set based on the 32-bit carry in 32-bit mode, so the condition has to be TARGET_64BIT. The adddi3 pattern has !TARGET_POWERPC64 since a 64-bit addition can be done without addc on a 64-bit machine, no matter what mode the CPU is in. > + "* > +{ Might as well leave out this stuff on new code, just use the braces :-) Segher