From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23502 invoked by alias); 8 Jul 2014 11:14:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 23478 invoked by uid 89); 8 Jul 2014 11:14:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f175.google.com Received: from mail-wi0-f175.google.com (HELO mail-wi0-f175.google.com) (209.85.212.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 08 Jul 2014 11:14:17 +0000 Received: by mail-wi0-f175.google.com with SMTP id ho1so776470wib.2 for ; Tue, 08 Jul 2014 04:14:14 -0700 (PDT) X-Received: by 10.180.218.72 with SMTP id pe8mr3088844wic.63.1404818053899; Tue, 08 Jul 2014 04:14:13 -0700 (PDT) Received: from msticlxl57.ims.intel.com ([192.55.55.41]) by mx.google.com with ESMTPSA id pq9sm95709761wjc.35.2014.07.08.04.14.11 for (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Jul 2014 04:14:13 -0700 (PDT) Date: Tue, 08 Jul 2014 11:14:00 -0000 From: Kirill Yukhin To: Marc Glisse Cc: GCC Patches , Uros Bizjak Subject: Re: [i386] Replace builtins with vector extensions Message-ID: <20140708111402.GB14139@msticlxl57.ims.intel.com> References: <20140703101605.GA12583@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes X-SW-Source: 2014-07/txt/msg00534.txt.bz2 Hello Marc. On 04 Jul 21:11, Marc Glisse wrote: > On Thu, 3 Jul 2014, Kirill Yukhin wrote: > like combining 2 shuffles unless the result is the identity. And > expanding shuffles that can be done in a single instruction works > well. > > But I am happy not doing them yet. To be very specific, could you > list which intrinsics you would like to remove from the posted > patch? I am not a x86 maintainer, however while such a replacements produce correct semantics and probably enable optimizations, I support your patch. Probably you could try such your approach on AVX2, AVX-512 whose intrinsics are well covered by tests? > >On the over hand, updated in such a way intrinsic > >may actually generate different instruction then intended (e.g. FMA case). > > It is the same with scalars, we have -ffp-contract for that. Agreed. -- Thanks, K