* [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices at dwf_regno
@ 2014-07-08 2:42 rohitarulraj
2014-07-22 7:28 ` rohitarulraj
2014-07-24 16:54 ` [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno Ulrich Weigand
0 siblings, 2 replies; 28+ messages in thread
From: rohitarulraj @ 2014-07-08 2:42 UTC (permalink / raw)
To: gcc-patches; +Cc: Edmar Wienskoski, dje.gcc, Alan Modra, Jakub Jelinek
[-- Attachment #1: Type: text/plain, Size: 702 bytes --]
Hello All,
This is related to the following bug:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60102
I have tried to fix the e500v2 build on GCC v4.9.0 with the attached patch.
Can you please review and comment on the changes especially DWARF_FRAME_REGNUM, DWARF_REG_TO_UNWIND_COLUMN definitions?
Tested this patch on trunk [r212120] with ppc64 and didn't find any new regressions.
Back ported this patch on GCC v4.8.2 e500v2 and tested with no new regressions
Note:
With GCC v4.9.0, to build the e500v2 bareboard version the attached patch is enough.
With GCC v4.9.0. to build the e500v2 linux version along with the attached patch please add pr60735 patch too.
Regards,
Rohit
[-- Attachment #2: pr60102.patch --]
[-- Type: application/octet-stream, Size: 14584 bytes --]
Index: libgcc/config/rs6000/linux-unwind.h
===================================================================
--- libgcc/config/rs6000/linux-unwind.h (revision 212339)
+++ libgcc/config/rs6000/linux-unwind.h (working copy)
@@ -274,8 +274,8 @@ ppc_fallback_frame_state (struct _Unwind
#ifdef __SPE__
for (i = 14; i < 32; i++)
{
- fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].how = REG_SAVED_OFFSET;
- fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].loc.offset
+ fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].how = REG_SAVED_OFFSET;
+ fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].loc.offset
= (long) ®s->vregs - new_cfa + 4 * i;
}
#endif
Index: gcc/testsuite/gcc.target/powerpc/pr60102.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr60102.c (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr60102.c (revision 0)
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+/* { dg-options "-mcpu=8548 -mspe -mabi=spe -g -mfloat-gprs=double" } */
+
+double
+pr60102 (double x, int m)
+{
+ double y;
+ y = m % 2 ? x : 1;
+ return y;
+}
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 212339)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -30930,13 +30930,13 @@ rs6000_dwarf_register_span (rtx reg)
{
if (BYTES_BIG_ENDIAN)
{
- parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
+ parts[2 * i] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
}
else
{
parts[2 * i] = gen_rtx_REG (SImode, regno);
- parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
+ parts[2 * i + 1] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
}
}
@@ -30956,7 +30956,7 @@ rs6000_init_dwarf_reg_sizes_extra (tree
rtx mem = gen_rtx_MEM (BLKmode, addr);
rtx value = gen_int_mode (4, mode);
- for (i = 1201; i < 1232; i++)
+ for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++)
{
int column = DWARF_REG_TO_UNWIND_COLUMN (i);
HOST_WIDE_INT offset
@@ -31013,9 +31013,8 @@ rs6000_dbx_register_number (unsigned int
return 99;
if (regno == SPEFSCR_REGNO)
return 612;
- /* SPE high reg number. We get these values of regno from
- rs6000_dwarf_register_span. */
- gcc_assert (regno >= 1200 && regno < 1232);
+ if (SPE_HIGH_REGNO_P (regno))
+ return regno - FIRST_SPE_HIGH_REGNO + 1200;
return regno;
}
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h (revision 212339)
+++ gcc/config/rs6000/rs6000.h (working copy)
@@ -929,13 +929,14 @@ enum data_align { align_abi, align_opt,
The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
-#define FIRST_PSEUDO_REGISTER 117
+#define FIRST_PSEUDO_REGISTER 149
/* This must be included for pre gcc 3.0 glibc compatibility. */
#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
-/* Add 32 dwarf columns for synthetic SPE registers. */
-#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32)
+/* SPE high registers added as hard regs.
+ The 3 HTM registers aren't included in DWARF_FRAME_REGISTERS */
+#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
/* The SPE has an additional 32 synthetic registers, with DWARF debug
info numbering for these registers starting at 1200. While eh_frame
@@ -951,13 +952,14 @@ enum data_align { align_abi, align_opt,
We must map them here to avoid huge unwinder tables mostly consisting
of unused space. */
#define DWARF_REG_TO_UNWIND_COLUMN(r) \
- ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
+ ((r) >= FIRST_SPE_HIGH_REGNO ? ((r) - FIRST_SPE_HIGH_REGNO + (DWARF_FRAME_REGISTERS - 32)) : (r))
/* Use standard DWARF numbering for DWARF debugging information. */
#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
/* Use gcc hard register numbering for eh_frame. */
-#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
+#define DWARF_FRAME_REGNUM(REGNO) \
+ ((REGNO) >= 1200 ? ((REGNO) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (REGNO))
/* Map register numbers held in the call frame info that gcc has
collected using DWARF_FRAME_REGNUM to those that should be output in
@@ -991,7 +993,10 @@ enum data_align { align_abi, align_opt,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \
- , 1, 1, 1, 1, 1, 1 \
+ , 1, 1, 1, 1, 1, 1, \
+ /* SPE High registers. */ \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
}
/* 1 for registers not available across function calls.
@@ -1011,7 +1016,10 @@ enum data_align { align_abi, align_opt,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \
- , 1, 1, 1, 1, 1, 1 \
+ , 1, 1, 1, 1, 1, 1, \
+ /* SPE High registers. */ \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
}
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -1030,7 +1038,10 @@ enum data_align { align_abi, align_opt,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0 \
- , 0, 0, 0, 0, 0, 0 \
+ , 0, 0, 0, 0, 0, 0, \
+ /* SPE High registers. */ \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
}
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
@@ -1113,7 +1124,10 @@ enum data_align { align_abi, align_opt,
96, 95, 94, 93, 92, 91, \
108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
109, 110, \
- 111, 112, 113, 114, 115, 116 \
+ 111, 112, 113, 114, 115, 116, \
+ 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \
+ 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \
+ 141, 142, 143, 144, 145, 146, 147, 148 \
}
/* True if register is floating-point. */
@@ -1135,6 +1149,9 @@ enum data_align { align_abi, align_opt,
/* PAIRED SIMD registers are just the FPRs. */
#define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
+/* True if register is an SPE High register. */
+#define SPE_HIGH_REGNO_P(N) ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO)
+
/* True if register is the CA register. */
#define CA_REGNO_P(N) ((N) == CA_REGNO)
@@ -1348,6 +1365,7 @@ enum reg_class
CR_REGS,
NON_FLOAT_REGS,
CA_REGS,
+ SPE_HIGH_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -1379,6 +1397,7 @@ enum reg_class
"CR_REGS", \
"NON_FLOAT_REGS", \
"CA_REGS", \
+ "SPE_HIGH_REGS", \
"ALL_REGS" \
}
@@ -1386,30 +1405,31 @@ enum reg_class
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
-#define REG_CLASS_CONTENTS \
-{ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
- { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
- { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
- { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
- { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
- { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, /* SPR_REGS */ \
- { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
- { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
- { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
- { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
- { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */ \
- { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
- { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
- { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
- { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \
- { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \
- { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } /* ALL_REGS */ \
+#define REG_CLASS_CONTENTS \
+{ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
+ { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, /* BASE_REGS */ \
+ { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, /* GENERAL_REGS */ \
+ { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
+ { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, /* ALTIVEC_REGS */ \
+ { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, /* VSX_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, /* VRSAVE_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, /* VSCR_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, /* SPE_ACC_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, /* SPEFSCR_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, /* SPR_REGS */ \
+ { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, /* NON_SPECIAL_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, /* LINK_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, /* CTR_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, /* SPECIAL_REGS */ \
+ { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, /* CR0_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, /* CR_REGS */ \
+ { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, /* NON_FLOAT_REGS */ \
+ { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, /* CA_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0xfff00000, 0x000fffff }, /* SPE_HIGH_REGS */ \
+ { 0xffffffff, 0xffffffff, 0xfffffffe, 0xfff7ffff, 0x000fffff } /* ALL_REGS */ \
}
/* The same information, inverted:
@@ -2341,6 +2361,39 @@ extern char rs6000_reg_names[][8]; /* re
&rs6000_reg_names[114][0], /* tfhar */ \
&rs6000_reg_names[115][0], /* tfiar */ \
&rs6000_reg_names[116][0], /* texasr */ \
+ \
+ &rs6000_reg_names[117][0], /* SPE rh0 */ \
+ &rs6000_reg_names[118][0], /* SPE rh1 */ \
+ &rs6000_reg_names[119][0], /* SPE rh2 */ \
+ &rs6000_reg_names[120][0], /* SPE rh3 */ \
+ &rs6000_reg_names[121][0], /* SPE rh4 */ \
+ &rs6000_reg_names[122][0], /* SPE rh5 */ \
+ &rs6000_reg_names[123][0], /* SPE rh6 */ \
+ &rs6000_reg_names[124][0], /* SPE rh7 */ \
+ &rs6000_reg_names[125][0], /* SPE rh8 */ \
+ &rs6000_reg_names[126][0], /* SPE rh9 */ \
+ &rs6000_reg_names[127][0], /* SPE rh10 */ \
+ &rs6000_reg_names[128][0], /* SPE rh11 */ \
+ &rs6000_reg_names[129][0], /* SPE rh12 */ \
+ &rs6000_reg_names[130][0], /* SPE rh13 */ \
+ &rs6000_reg_names[131][0], /* SPE rh14 */ \
+ &rs6000_reg_names[132][0], /* SPE rh15 */ \
+ &rs6000_reg_names[133][0], /* SPE rh16 */ \
+ &rs6000_reg_names[134][0], /* SPE rh17 */ \
+ &rs6000_reg_names[135][0], /* SPE rh18 */ \
+ &rs6000_reg_names[136][0], /* SPE rh19 */ \
+ &rs6000_reg_names[137][0], /* SPE rh20 */ \
+ &rs6000_reg_names[138][0], /* SPE rh21 */ \
+ &rs6000_reg_names[139][0], /* SPE rh22 */ \
+ &rs6000_reg_names[140][0], /* SPE rh22 */ \
+ &rs6000_reg_names[141][0], /* SPE rh24 */ \
+ &rs6000_reg_names[142][0], /* SPE rh25 */ \
+ &rs6000_reg_names[143][0], /* SPE rh26 */ \
+ &rs6000_reg_names[144][0], /* SPE rh27 */ \
+ &rs6000_reg_names[145][0], /* SPE rh28 */ \
+ &rs6000_reg_names[146][0], /* SPE rh29 */ \
+ &rs6000_reg_names[147][0], /* SPE rh30 */ \
+ &rs6000_reg_names[148][0], /* SPE rh31 */ \
}
/* Table of additional register names to use in user input. */
@@ -2396,7 +2449,17 @@ extern char rs6000_reg_names[][8]; /* re
{"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
{"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
/* Transactional Memory Facility (HTM) Registers. */ \
- {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116} }
+ {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \
+ /* SPE high registers */ \
+ {"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \
+ {"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \
+ {"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \
+ {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \
+ {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \
+ {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \
+ {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \
+ {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \
+}
/* This is how to output an element of a case-vector that is relative. */
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 212339)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -56,6 +56,8 @@
(TFHAR_REGNO 114)
(TFIAR_REGNO 115)
(TEXASR_REGNO 116)
+ (FIRST_SPE_HIGH_REGNO 117)
+ (LAST_SPE_HIGH_REGNO 148)
])
;;
^ permalink raw reply [flat|nested] 28+ messages in thread* RE: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices at dwf_regno 2014-07-08 2:42 [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices at dwf_regno rohitarulraj @ 2014-07-22 7:28 ` rohitarulraj 2014-07-24 16:54 ` [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno Ulrich Weigand 1 sibling, 0 replies; 28+ messages in thread From: rohitarulraj @ 2014-07-22 7:28 UTC (permalink / raw) To: gcc-patches Cc: Edmar Wienskoski, dje.gcc, Alan Modra, Jakub Jelinek, rohitarulraj Ping! > -----Original Message----- > From: Dharmakan Rohit-B30502 > Sent: Tuesday, July 08, 2014 8:13 AM > To: gcc-patches@gcc.gnu.org > Cc: Wienskoski Edmar-RA8797; dje.gcc@gmail.com; Alan Modra; Jakub Jelinek > Subject: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices at > dwf_regno > > Hello All, > > This is related to the following bug: > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60102 > > I have tried to fix the e500v2 build on GCC v4.9.0 with the attached patch. > Can you please review and comment on the changes especially > DWARF_FRAME_REGNUM, DWARF_REG_TO_UNWIND_COLUMN definitions? > > Tested this patch on trunk [r212120] with ppc64 and didn't find any new > regressions. > Back ported this patch on GCC v4.8.2 e500v2 and tested with no new > regressions > > Note: > With GCC v4.9.0, to build the e500v2 bareboard version the attached patch is > enough. > With GCC v4.9.0. to build the e500v2 linux version along with the attached > patch please add pr60735 patch too. > > Regards, > Rohit > ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-07-08 2:42 [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices at dwf_regno rohitarulraj 2014-07-22 7:28 ` rohitarulraj @ 2014-07-24 16:54 ` Ulrich Weigand 2014-07-31 18:23 ` rohitarulraj 1 sibling, 1 reply; 28+ messages in thread From: Ulrich Weigand @ 2014-07-24 16:54 UTC (permalink / raw) To: rohitarulraj Cc: gcc-patches, Edmar Wienskoski, dje.gcc, Alan Modra, Jakub Jelinek Rohit wrote: > This is related to the following bug: > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D60102 > > I have tried to fix the e500v2 build on GCC v4.9.0 with the attached patch. > Can you please review and comment on the changes especially DWARF_FRAME_REG= > NUM, DWARF_REG_TO_UNWIND_COLUMN definitions? David asked me to comment on the use of DWARF register numbers in this patch. There's a number of register number "address spaces" in play here: (A) GCC hard register numbers (B) DWARF register numbers used in .debug_info etc. (C) DWARF CFI register numbers (GCC internal) (D) DWARF CFI register numbers as used in .debug_frame (E) DWARF CFI register numbers as used in .eh_frame (F) DWARF CFI unwind column numbers These are a number of macros to convert between them: DBX_REGISTER_NUMBER: (A) -> (B) DWARF_FRAME_REGNUM: (A) -> (C) DWARF2_FRAME_REG_OUT: (C) -> (D) / (E) DWARF_REG_TO_UNWIND_COLUMN: (E) -> (F) Note that some of these seem to be used incorrectly in current rs6000.c: for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++) { int column = DWARF_REG_TO_UNWIND_COLUMN (i); HOST_WIDE_INT offset = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode); This should rather be int column = DWARF_REG_TO_UNWIND_COLUMN (DWARF_FRAME_REGNUM (i)); HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode); which doesn't show up as problem currently since DWARF_FRAME_REGNUM is defined as the identity mapping, but will show up once you have to actually define a nontrivial mapping in DWARF_FRAME_REGNUM. [ To be fully correct, I guess it actually should be int column = DWARF_REG_TO_UNWIND_COLUMN (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true)); but DWARF2_FRAME_REG_OUT (..., true) is the identity map as well ... ] Now, if I understand the SPE situation correctly, you had previously: - no GCC hard register numbers (however, rs6000_dwarf_register_span, which is supposed to return a hard register number, returned numbers in the 1200..1231 range) - used the 1200..1231 range for (B), (C), (D), and (E) - used the 113..145 range for (F) Now, you need to introduce new GCC hard register numbers (A). However, in order to preserve compatibility with DWARF info in existing binaries, none of (B), (D), (E) or (F) is allowed to change. [ (C) could change in theory, but it's probably best not to change it either. ] Your patch now defines the new GCC hard register numbers in the 117..149 range, which seems reasonable. However, you ought to the leave the other mappings unchanged. For (B) this looks OK due to the rs6000_dbx_register_number change. However (C), (D), and (E) *do* change with your patch: > -#define DWARF_FRAME_REGNUM(REGNO) (REGNO) > +#define DWARF_FRAME_REGNUM(REGNO) \ > + ((REGNO) >= 1200 ? ((REGNO) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (REGNO)) This isn't OK; the input to DWARF_FRAME_REGNUM is a GCC hard register number, which will never be in the 1200... range. On the other hand, you can now get hard register numbers in the 117..149 range, which you need to map *back* to the 1200..1231 range, or else CFI register numbers will be wrong. So you should have something like: #define DWARF_FRAME_REGNUM(REGNO) \ (SPE_HIGH_REGNO_P(REGNO)? ((REGNO) - FIRST_SPE_HIGH_REGNO + 1200) : (REGNO)) On the other hand, the DWARF_REG_TO_UNWIND_COLUMN macro needs to map that 1200..1231 range back to the 113..145 range, so it should just stay as-is. Note that (F) ends up being OK with your patch as-is, since the two bugs in DWARF_FRAME_REGNUM and DWARF_REG_TO_UNWIND_COLUMN cancel each other out. A couple of further comments on the patch: > Index: libgcc/config/rs6000/linux-unwind.h > =================================================================== > --- libgcc/config/rs6000/linux-unwind.h (revision 212339) > +++ libgcc/config/rs6000/linux-unwind.h (working copy) > @@ -274,8 +274,8 @@ ppc_fallback_frame_state (struct _Unwind > #ifdef __SPE__ > for (i = 14; i < 32; i++) > { > - fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].how = REG_SAVED_OFFSET; > - fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].loc.offset > + fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].how = REG_SAVED_OFFSET; > + fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].loc.offset This is a change to current behaviour, but that was probably intended since the old behaviour seems broken (apparently wasn't updated after the introduction of the three HTM registers). > Index: gcc/config/rs6000/rs6000.c > =================================================================== > --- gcc/config/rs6000/rs6000.c (revision 212339) > +++ gcc/config/rs6000/rs6000.c (working copy) > @@ -30956,7 +30956,7 @@ rs6000_init_dwarf_reg_sizes_extra (tree > rtx mem = gen_rtx_MEM (BLKmode, addr); > rtx value = gen_int_mode (4, mode); > > - for (i = 1201; i < 1232; i++) > + for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++) Again this seems to change behaviour, but the old seems broken (didn't initialize the first SPE high register). > -/* Add 32 dwarf columns for synthetic SPE registers. */ > -#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32) > +/* SPE high registers added as hard regs. > + The 3 HTM registers aren't included in DWARF_FRAME_REGISTERS */ > +#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) This is OK, but the comment is confusing: the -4 is because *four* registers aren't included in DWARF_FRAME_REGISTER, namely the 3 HTM registers *and the sfp register*. > /* The SPE has an additional 32 synthetic registers, with DWARF debug > info numbering for these registers starting at 1200. While eh_frame > @@ -951,13 +952,14 @@ enum data_align { align_abi, align_opt, > We must map them here to avoid huge unwinder tables mostly consisting > of unused space. */ > #define DWARF_REG_TO_UNWIND_COLUMN(r) \ > - ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) > + ((r) >= FIRST_SPE_HIGH_REGNO ? ((r) - FIRST_SPE_HIGH_REGNO + (DWARF_FRAME_REGISTERS - 32)) : (r)) As discussed above, this shouldn't change. > /* Use gcc hard register numbering for eh_frame. */ > -#define DWARF_FRAME_REGNUM(REGNO) (REGNO) > +#define DWARF_FRAME_REGNUM(REGNO) \ > + ((REGNO) >= 1200 ? ((REGNO) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (REGNO)) As discussed above, this is wrong. > + { 0x00000000, 0x00000000, 0x00000000, 0xfff00000, 0x000fffff }, /* SPE_HIGH_REGS */ \ > + { 0xffffffff, 0xffffffff, 0xfffffffe, 0xfff7ffff, 0x000fffff } /* ALL_REGS */ \ This looks wrong to me; the SPE high regs have hard register numbers in the 117..149 range. 117 is not a multiple of 4, so there cannot be just "f" hex characters in the map for SPE_HIGH_REGS. > + &rs6000_reg_names[117][0], /* SPE rh0 */ \ > + &rs6000_reg_names[118][0], /* SPE rh1 */ \ > + &rs6000_reg_names[119][0], /* SPE rh2 */ \ You need to actually initialize those rs6000_reg_names field in rs6000.c if you refer to them here. Bye, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain Ulrich.Weigand@de.ibm.com ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-07-24 16:54 ` [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno Ulrich Weigand @ 2014-07-31 18:23 ` rohitarulraj 2014-08-01 14:29 ` Ulrich Weigand 0 siblings, 1 reply; 28+ messages in thread From: rohitarulraj @ 2014-07-31 18:23 UTC (permalink / raw) To: Ulrich Weigand Cc: gcc-patches, Edmar Wienskoski, dje.gcc, Alan Modra, Jakub Jelinek, rohitarulraj [-- Attachment #1: Type: text/plain, Size: 2543 bytes --] Ulrich, Thanks for your comments, I have updated the patch accordingly. > > /* The SPE has an additional 32 synthetic registers, with DWARF debug > > info numbering for these registers starting at 1200. While > > eh_frame @@ -951,13 +952,14 @@ enum data_align { align_abi, align_opt, > > We must map them here to avoid huge unwinder tables mostly consisting > > of unused space. */ > > #define DWARF_REG_TO_UNWIND_COLUMN(r) \ > > - ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) > > + ((r) >= FIRST_SPE_HIGH_REGNO ? ((r) - FIRST_SPE_HIGH_REGNO + > > + (DWARF_FRAME_REGISTERS - 32)) : (r)) > > As discussed above, this shouldn't change. Updated to handle first SPE high register too. #define DWARF_REG_TO_UNWIND_COLUMN(r) \ - ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) + ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r) Tested this patch on trunk [213030] & GCC v4.9.1 with ppc64 and didn't find any new regressions. Back ported this patch on GCC v4.8.3 e500v2 and tested with no new regressions PR target/60102 [libgcc] 2014-07-31 Rohit <rohitarulraj@freescale.com> * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update based on change in SPE high register numbers and 3 HTM registers. [gcc] 2014-07-31 Rohit <rohitarulraj@freescale.com> * config/rs6000/rs6000.c (rs6000_reg_names) : Add SPE high register names. (alt_reg_names) : Likewise (rs6000_dwarf_register_span) : For SPE high registers, replace dwarf register numbers with GCC hard register numbers. (rs6000_init_dwarf_reg_sizes_extra) : Likewise. (rs6000_dbx_register_number): For SPE high registers, return dwarf register number for the corresponding GCC hard register number. * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard register numbers for SPE high registers. (DWARF_FRAME_REGISTERS) : Likewise. (DWARF_REG_TO_UNWIND_COLUMN) : Likewise. (DWARF_FRAME_REGNUM) : Likewise. (FIXED_REGISTERS) : Likewise. (CALL_USED_REGISTERS) : Likewise. (CALL_REALLY_USED_REGISTERS) : Likewise. (REG_ALLOC_ORDER) : Likewise. (enum reg_class) : Likewise. (REG_CLASS_NAMES) : Likewise. (REG_CLASS_CONTENTS) : Likewise. (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. * gcc.target/powerpc/pr60102.c: New testcase. Please let me know if you have any further comments on the updated patch. Regards, Rohit [-- Attachment #2: pr60102.patch --] [-- Type: application/octet-stream, Size: 17001 bytes --] Index: libgcc/config/rs6000/linux-unwind.h =================================================================== --- libgcc/config/rs6000/linux-unwind.h (revision 213110) +++ libgcc/config/rs6000/linux-unwind.h (working copy) @@ -274,8 +274,8 @@ ppc_fallback_frame_state (struct _Unwind #ifdef __SPE__ for (i = 14; i < 32; i++) { - fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].how = REG_SAVED_OFFSET; - fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].loc.offset + fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].how = REG_SAVED_OFFSET; + fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].loc.offset = (long) ®s->vregs - new_cfa + 4 * i; } #endif Index: gcc/testsuite/gcc.target/powerpc/pr60102.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr60102.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/pr60102.c (revision 0) @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-options "-mcpu=8548 -mspe -mabi=spe -g -mfloat-gprs=double" } */ + +double +pr60102 (double x, int m) +{ + double y; + y = m % 2 ? x : 1; + return y; +} Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 213110) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -1221,7 +1221,12 @@ char rs6000_reg_names[][8] = /* Soft frame pointer. */ "sfp", /* HTM SPR registers. */ - "tfhar", "tfiar", "texasr" + "tfhar", "tfiar", "texasr", + /* SPE High registers. */ + "0", "1", "2", "3", "4", "5", "6", "7", + "8", "9", "10", "11", "12", "13", "14", "15", + "16", "17", "18", "19", "20", "21", "22", "23", + "24", "25", "26", "27", "28", "29", "30", "31" }; #ifdef TARGET_REGNAMES @@ -1249,7 +1254,12 @@ static const char alt_reg_names[][8] = /* Soft frame pointer. */ "sfp", /* HTM SPR registers. */ - "tfhar", "tfiar", "texasr" + "tfhar", "tfiar", "texasr", + /* SPE High registers. */ + "%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7", + "%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15", + "%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23", + "%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31" }; #endif @@ -31074,13 +31084,13 @@ rs6000_dwarf_register_span (rtx reg) { if (BYTES_BIG_ENDIAN) { - parts[2 * i] = gen_rtx_REG (SImode, regno + 1200); + parts[2 * i] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO); parts[2 * i + 1] = gen_rtx_REG (SImode, regno); } else { parts[2 * i] = gen_rtx_REG (SImode, regno); - parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200); + parts[2 * i + 1] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO); } } @@ -31100,11 +31110,11 @@ rs6000_init_dwarf_reg_sizes_extra (tree rtx mem = gen_rtx_MEM (BLKmode, addr); rtx value = gen_int_mode (4, mode); - for (i = 1201; i < 1232; i++) + for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++) { - int column = DWARF_REG_TO_UNWIND_COLUMN (i); - HOST_WIDE_INT offset - = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode); + int column = DWARF_REG_TO_UNWIND_COLUMN + (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true)); + HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode); emit_move_insn (adjust_address (mem, mode, offset), value); } @@ -31123,9 +31133,9 @@ rs6000_init_dwarf_reg_sizes_extra (tree for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++) { - int column = DWARF_REG_TO_UNWIND_COLUMN (i); - HOST_WIDE_INT offset - = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode); + int column = DWARF_REG_TO_UNWIND_COLUMN + (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true)); + HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode); emit_move_insn (adjust_address (mem, mode, offset), value); } @@ -31157,9 +31167,8 @@ rs6000_dbx_register_number (unsigned int return 99; if (regno == SPEFSCR_REGNO) return 612; - /* SPE high reg number. We get these values of regno from - rs6000_dwarf_register_span. */ - gcc_assert (regno >= 1200 && regno < 1232); + if (SPE_HIGH_REGNO_P (regno)) + return regno - FIRST_SPE_HIGH_REGNO + 1200; return regno; } Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 213110) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -930,35 +930,32 @@ enum data_align { align_abi, align_opt, The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ -#define FIRST_PSEUDO_REGISTER 117 +#define FIRST_PSEUDO_REGISTER 149 /* This must be included for pre gcc 3.0 glibc compatibility. */ #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 -/* Add 32 dwarf columns for synthetic SPE registers. */ -#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32) +/* SPE high registers added as hard regs. + The sfp register and 3 HTM registers + aren't included in DWARF_FRAME_REGISTERS. */ +#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) /* The SPE has an additional 32 synthetic registers, with DWARF debug info numbering for these registers starting at 1200. While eh_frame register numbering need not be the same as the debug info numbering, - we choose to number these regs for eh_frame at 1200 too. This allows - future versions of the rs6000 backend to add hard registers and - continue to use the gcc hard register numbering for eh_frame. If the - extra SPE registers in eh_frame were numbered starting from the - current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER - changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to - avoid invalidating older SPE eh_frame info. + we choose to number these regs for eh_frame at 1200 too. We must map them here to avoid huge unwinder tables mostly consisting of unused space. */ #define DWARF_REG_TO_UNWIND_COLUMN(r) \ - ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) + ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) /* Use standard DWARF numbering for DWARF debugging information. */ #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) /* Use gcc hard register numbering for eh_frame. */ -#define DWARF_FRAME_REGNUM(REGNO) (REGNO) +#define DWARF_FRAME_REGNUM(REGNO) \ + ((REGNO) >= FIRST_SPE_HIGH_REGNO ? ((REGNO) - FIRST_SPE_HIGH_REGNO + 1200) : (REGNO)) /* Map register numbers held in the call frame info that gcc has collected using DWARF_FRAME_REGNUM to those that should be output in @@ -992,7 +989,10 @@ enum data_align { align_abi, align_opt, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ - , 1, 1, 1, 1, 1, 1 \ + , 1, 1, 1, 1, 1, 1, \ + /* SPE High registers. */ \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ } /* 1 for registers not available across function calls. @@ -1012,7 +1012,10 @@ enum data_align { align_abi, align_opt, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ - , 1, 1, 1, 1, 1, 1 \ + , 1, 1, 1, 1, 1, 1, \ + /* SPE High registers. */ \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ } /* Like `CALL_USED_REGISTERS' except this macro doesn't require that @@ -1031,7 +1034,10 @@ enum data_align { align_abi, align_opt, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0 \ - , 0, 0, 0, 0, 0, 0 \ + , 0, 0, 0, 0, 0, 0, \ + /* SPE High registers. */ \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ } #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) @@ -1114,7 +1120,10 @@ enum data_align { align_abi, align_opt, 96, 95, 94, 93, 92, 91, \ 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 109, 110, \ - 111, 112, 113, 114, 115, 116 \ + 111, 112, 113, 114, 115, 116, \ + 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \ + 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \ + 141, 142, 143, 144, 145, 146, 147, 148 \ } /* True if register is floating-point. */ @@ -1136,6 +1145,10 @@ enum data_align { align_abi, align_opt, /* PAIRED SIMD registers are just the FPRs. */ #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) +/* True if register is an SPE High register. */ +#define SPE_HIGH_REGNO_P(N) \ + ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO) + /* True if register is the CA register. */ #define CA_REGNO_P(N) ((N) == CA_REGNO) @@ -1349,6 +1362,7 @@ enum reg_class CR_REGS, NON_FLOAT_REGS, CA_REGS, + SPE_HIGH_REGS, ALL_REGS, LIM_REG_CLASSES }; @@ -1380,6 +1394,7 @@ enum reg_class "CR_REGS", \ "NON_FLOAT_REGS", \ "CA_REGS", \ + "SPE_HIGH_REGS", \ "ALL_REGS" \ } @@ -1387,30 +1402,54 @@ enum reg_class This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ -#define REG_CLASS_CONTENTS \ -{ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ - { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \ - { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \ - { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ - { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ - { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, /* SPR_REGS */ \ - { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ - { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ - { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */ \ - { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \ - { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ - { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ - { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \ - { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \ - { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } /* ALL_REGS */ \ +#define REG_CLASS_CONTENTS \ +{ \ + /* NO_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ + /* BASE_REGS. */ \ + { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ + /* GENERAL_REGS. */ \ + { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ + /* FLOAT_REGS. */ \ + { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \ + /* ALTIVEC_REGS. */ \ + { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \ + /* VSX_REGS. */ \ + { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \ + /* VRSAVE_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \ + /* VSCR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \ + /* SPE_ACC_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \ + /* SPEFSCR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \ + /* SPR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \ + /* NON_SPECIAL_REGS. */ \ + { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \ + /* LINK_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \ + /* CTR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \ + /* LINK_OR_CTR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \ + /* SPECIAL_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \ + /* SPEC_OR_GEN_REGS. */ \ + { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \ + /* CR0_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \ + /* CR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \ + /* NON_FLOAT_REGS. */ \ + { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \ + /* CA_REGS. */ \ + { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \ + /* SPE_HIGH_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \ + /* ALL_REGS. */ \ + { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \ } /* The same information, inverted: @@ -2349,6 +2388,39 @@ extern char rs6000_reg_names[][8]; /* re &rs6000_reg_names[114][0], /* tfhar */ \ &rs6000_reg_names[115][0], /* tfiar */ \ &rs6000_reg_names[116][0], /* texasr */ \ + \ + &rs6000_reg_names[117][0], /* SPE rh0. */ \ + &rs6000_reg_names[118][0], /* SPE rh1. */ \ + &rs6000_reg_names[119][0], /* SPE rh2. */ \ + &rs6000_reg_names[120][0], /* SPE rh3. */ \ + &rs6000_reg_names[121][0], /* SPE rh4. */ \ + &rs6000_reg_names[122][0], /* SPE rh5. */ \ + &rs6000_reg_names[123][0], /* SPE rh6. */ \ + &rs6000_reg_names[124][0], /* SPE rh7. */ \ + &rs6000_reg_names[125][0], /* SPE rh8. */ \ + &rs6000_reg_names[126][0], /* SPE rh9. */ \ + &rs6000_reg_names[127][0], /* SPE rh10. */ \ + &rs6000_reg_names[128][0], /* SPE rh11. */ \ + &rs6000_reg_names[129][0], /* SPE rh12. */ \ + &rs6000_reg_names[130][0], /* SPE rh13. */ \ + &rs6000_reg_names[131][0], /* SPE rh14. */ \ + &rs6000_reg_names[132][0], /* SPE rh15. */ \ + &rs6000_reg_names[133][0], /* SPE rh16. */ \ + &rs6000_reg_names[134][0], /* SPE rh17. */ \ + &rs6000_reg_names[135][0], /* SPE rh18. */ \ + &rs6000_reg_names[136][0], /* SPE rh19. */ \ + &rs6000_reg_names[137][0], /* SPE rh20. */ \ + &rs6000_reg_names[138][0], /* SPE rh21. */ \ + &rs6000_reg_names[139][0], /* SPE rh22. */ \ + &rs6000_reg_names[140][0], /* SPE rh22. */ \ + &rs6000_reg_names[141][0], /* SPE rh24. */ \ + &rs6000_reg_names[142][0], /* SPE rh25. */ \ + &rs6000_reg_names[143][0], /* SPE rh26. */ \ + &rs6000_reg_names[144][0], /* SPE rh27. */ \ + &rs6000_reg_names[145][0], /* SPE rh28. */ \ + &rs6000_reg_names[146][0], /* SPE rh29. */ \ + &rs6000_reg_names[147][0], /* SPE rh30. */ \ + &rs6000_reg_names[148][0], /* SPE rh31. */ \ } /* Table of additional register names to use in user input. */ @@ -2404,7 +2476,17 @@ extern char rs6000_reg_names[][8]; /* re {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ /* Transactional Memory Facility (HTM) Registers. */ \ - {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116} } + {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \ + /* SPE high registers. */ \ + {"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \ + {"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \ + {"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \ + {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \ + {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \ + {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \ + {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \ + {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \ +} /* This is how to output an element of a case-vector that is relative. */ Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 213110) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -56,6 +56,8 @@ (TFHAR_REGNO 114) (TFIAR_REGNO 115) (TEXASR_REGNO 116) + (FIRST_SPE_HIGH_REGNO 117) + (LAST_SPE_HIGH_REGNO 148) ]) ;; ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-07-31 18:23 ` rohitarulraj @ 2014-08-01 14:29 ` Ulrich Weigand 2014-08-01 18:04 ` rohitarulraj 0 siblings, 1 reply; 28+ messages in thread From: Ulrich Weigand @ 2014-08-01 14:29 UTC (permalink / raw) To: rohitarulraj Cc: gcc-patches, Edmar Wienskoski, dje.gcc, Alan Modra, Jakub Jelinek Rohit, > #define DWARF_REG_TO_UNWIND_COLUMN(r) \ >- ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) >+ ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) OK, makes sense. > /* Use gcc hard register numbering for eh_frame. */ >-#define DWARF_FRAME_REGNUM(REGNO) (REGNO) >+#define DWARF_FRAME_REGNUM(REGNO) \ >+ ((REGNO) >= FIRST_SPE_HIGH_REGNO ? ((REGNO) - FIRST_SPE_HIGH_REGNO + 1200) : (REGNO)) Any reason for not using SPE_HIGH_REGNO_P here, just in case we do get other hard registers at some point? Otherwise this now looks good to me. (Of course, I cannot approve the patch myself.) Thanks, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain Ulrich.Weigand@de.ibm.com ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-08-01 14:29 ` Ulrich Weigand @ 2014-08-01 18:04 ` rohitarulraj 2014-08-01 18:10 ` Jakub Jelinek 2014-08-02 1:46 ` David Edelsohn 0 siblings, 2 replies; 28+ messages in thread From: rohitarulraj @ 2014-08-01 18:04 UTC (permalink / raw) To: Ulrich Weigand Cc: gcc-patches, Edmar Wienskoski, dje.gcc, Alan Modra, Jakub Jelinek, rohitarulraj [-- Attachment #1: Type: text/plain, Size: 2159 bytes --] Hello Ulrich, Thanks. > > /* Use gcc hard register numbering for eh_frame. */ -#define > >DWARF_FRAME_REGNUM(REGNO) (REGNO) > >+#define DWARF_FRAME_REGNUM(REGNO) \ > >+ ((REGNO) >= FIRST_SPE_HIGH_REGNO ? ((REGNO) - > FIRST_SPE_HIGH_REGNO + > >+1200) : (REGNO)) > > Any reason for not using SPE_HIGH_REGNO_P here, just in case we do get > other hard registers at some point? Yes, we can use it. I just have to move the definition of "SPE_HIGH_REGNO_P" macro before "DWARF_FRAME_REGNUM" macro definition. [Previously, I had defined and placed "SPE_HIGH_REGNO_P" macro along with similar macros "ALTIVEC_REGNO_P" etc.] I had updated the patch as required (For this last change, I have checked/tested only the builds: ppc64 trunk, e500v2 v4.9.1 bareboard & linux build). PR target/60102 [libgcc] 2014-07-31 Rohit <rohitarulraj@freescale.com> * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update based on change in SPE high register numbers and 3 HTM registers. [gcc] 2014-07-31 Rohit <rohitarulraj@freescale.com> * config/rs6000/rs6000.c (rs6000_reg_names) : Add SPE high register names. (alt_reg_names) : Likewise. (rs6000_dwarf_register_span) : For SPE high registers, replace dwarf register numbers with GCC hard register numbers. (rs6000_init_dwarf_reg_sizes_extra) : Likewise. (rs6000_dbx_register_number): For SPE high registers, return dwarf register number for the corresponding GCC hard register number. * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard register numbers for SPE high registers. (DWARF_FRAME_REGISTERS) : Likewise. (DWARF_REG_TO_UNWIND_COLUMN) : Likewise. (DWARF_FRAME_REGNUM) : Likewise. (FIXED_REGISTERS) : Likewise. (CALL_USED_REGISTERS) : Likewise. (CALL_REALLY_USED_REGISTERS) : Likewise. (REG_ALLOC_ORDER) : Likewise. (enum reg_class) : Likewise. (REG_CLASS_NAMES) : Likewise. (REG_CLASS_CONTENTS) : Likewise. (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. * gcc.target/powerpc/pr60102.c: New testcase. Regards, Rohit [-- Attachment #2: pr60102.patch --] [-- Type: application/octet-stream, Size: 16734 bytes --] Index: libgcc/config/rs6000/linux-unwind.h =================================================================== --- libgcc/config/rs6000/linux-unwind.h (revision 213110) +++ libgcc/config/rs6000/linux-unwind.h (working copy) @@ -274,8 +274,8 @@ ppc_fallback_frame_state (struct _Unwind #ifdef __SPE__ for (i = 14; i < 32; i++) { - fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].how = REG_SAVED_OFFSET; - fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].loc.offset + fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].how = REG_SAVED_OFFSET; + fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].loc.offset = (long) ®s->vregs - new_cfa + 4 * i; } #endif Index: gcc/testsuite/gcc.target/powerpc/pr60102.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr60102.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/pr60102.c (revision 0) @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-options "-mcpu=8548 -mspe -mabi=spe -g -mfloat-gprs=double" } */ + +double +pr60102 (double x, int m) +{ + double y; + y = m % 2 ? x : 1; + return y; +} Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 213110) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -1221,7 +1221,12 @@ char rs6000_reg_names[][8] = /* Soft frame pointer. */ "sfp", /* HTM SPR registers. */ - "tfhar", "tfiar", "texasr" + "tfhar", "tfiar", "texasr", + /* SPE High registers. */ + "0", "1", "2", "3", "4", "5", "6", "7", + "8", "9", "10", "11", "12", "13", "14", "15", + "16", "17", "18", "19", "20", "21", "22", "23", + "24", "25", "26", "27", "28", "29", "30", "31" }; #ifdef TARGET_REGNAMES @@ -1249,7 +1254,12 @@ static const char alt_reg_names[][8] = /* Soft frame pointer. */ "sfp", /* HTM SPR registers. */ - "tfhar", "tfiar", "texasr" + "tfhar", "tfiar", "texasr", + /* SPE High registers. */ + "%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7", + "%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15", + "%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23", + "%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31" }; #endif @@ -31074,13 +31084,13 @@ rs6000_dwarf_register_span (rtx reg) { if (BYTES_BIG_ENDIAN) { - parts[2 * i] = gen_rtx_REG (SImode, regno + 1200); + parts[2 * i] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO); parts[2 * i + 1] = gen_rtx_REG (SImode, regno); } else { parts[2 * i] = gen_rtx_REG (SImode, regno); - parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200); + parts[2 * i + 1] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO); } } @@ -31100,11 +31110,11 @@ rs6000_init_dwarf_reg_sizes_extra (tree rtx mem = gen_rtx_MEM (BLKmode, addr); rtx value = gen_int_mode (4, mode); - for (i = 1201; i < 1232; i++) + for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++) { - int column = DWARF_REG_TO_UNWIND_COLUMN (i); - HOST_WIDE_INT offset - = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode); + int column = DWARF_REG_TO_UNWIND_COLUMN + (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true)); + HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode); emit_move_insn (adjust_address (mem, mode, offset), value); } @@ -31123,9 +31133,9 @@ rs6000_init_dwarf_reg_sizes_extra (tree for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++) { - int column = DWARF_REG_TO_UNWIND_COLUMN (i); - HOST_WIDE_INT offset - = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode); + int column = DWARF_REG_TO_UNWIND_COLUMN + (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true)); + HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode); emit_move_insn (adjust_address (mem, mode, offset), value); } @@ -31157,9 +31167,8 @@ rs6000_dbx_register_number (unsigned int return 99; if (regno == SPEFSCR_REGNO) return 612; - /* SPE high reg number. We get these values of regno from - rs6000_dwarf_register_span. */ - gcc_assert (regno >= 1200 && regno < 1232); + if (SPE_HIGH_REGNO_P (regno)) + return regno - FIRST_SPE_HIGH_REGNO + 1200; return regno; } Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 213110) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -930,35 +930,36 @@ enum data_align { align_abi, align_opt, The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ -#define FIRST_PSEUDO_REGISTER 117 +#define FIRST_PSEUDO_REGISTER 149 /* This must be included for pre gcc 3.0 glibc compatibility. */ #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 -/* Add 32 dwarf columns for synthetic SPE registers. */ -#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32) +/* True if register is an SPE High register. */ +#define SPE_HIGH_REGNO_P(N) \ + ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO) + +/* SPE high registers added as hard regs. + The sfp register and 3 HTM registers + aren't included in DWARF_FRAME_REGISTERS. */ +#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) /* The SPE has an additional 32 synthetic registers, with DWARF debug info numbering for these registers starting at 1200. While eh_frame register numbering need not be the same as the debug info numbering, - we choose to number these regs for eh_frame at 1200 too. This allows - future versions of the rs6000 backend to add hard registers and - continue to use the gcc hard register numbering for eh_frame. If the - extra SPE registers in eh_frame were numbered starting from the - current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER - changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to - avoid invalidating older SPE eh_frame info. + we choose to number these regs for eh_frame at 1200 too. We must map them here to avoid huge unwinder tables mostly consisting of unused space. */ #define DWARF_REG_TO_UNWIND_COLUMN(r) \ - ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) + ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) /* Use standard DWARF numbering for DWARF debugging information. */ #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) /* Use gcc hard register numbering for eh_frame. */ -#define DWARF_FRAME_REGNUM(REGNO) (REGNO) +#define DWARF_FRAME_REGNUM(REGNO) \ + (SPE_HIGH_REGNO_P (REGNO) ? ((REGNO) - FIRST_SPE_HIGH_REGNO + 1200) : (REGNO)) /* Map register numbers held in the call frame info that gcc has collected using DWARF_FRAME_REGNUM to those that should be output in @@ -992,7 +993,10 @@ enum data_align { align_abi, align_opt, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ - , 1, 1, 1, 1, 1, 1 \ + , 1, 1, 1, 1, 1, 1, \ + /* SPE High registers. */ \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ } /* 1 for registers not available across function calls. @@ -1012,7 +1016,10 @@ enum data_align { align_abi, align_opt, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ - , 1, 1, 1, 1, 1, 1 \ + , 1, 1, 1, 1, 1, 1, \ + /* SPE High registers. */ \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ } /* Like `CALL_USED_REGISTERS' except this macro doesn't require that @@ -1031,7 +1038,10 @@ enum data_align { align_abi, align_opt, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0 \ - , 0, 0, 0, 0, 0, 0 \ + , 0, 0, 0, 0, 0, 0, \ + /* SPE High registers. */ \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ } #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) @@ -1114,7 +1124,10 @@ enum data_align { align_abi, align_opt, 96, 95, 94, 93, 92, 91, \ 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 109, 110, \ - 111, 112, 113, 114, 115, 116 \ + 111, 112, 113, 114, 115, 116, \ + 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \ + 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \ + 141, 142, 143, 144, 145, 146, 147, 148 \ } /* True if register is floating-point. */ @@ -1349,6 +1362,7 @@ enum reg_class CR_REGS, NON_FLOAT_REGS, CA_REGS, + SPE_HIGH_REGS, ALL_REGS, LIM_REG_CLASSES }; @@ -1380,6 +1394,7 @@ enum reg_class "CR_REGS", \ "NON_FLOAT_REGS", \ "CA_REGS", \ + "SPE_HIGH_REGS", \ "ALL_REGS" \ } @@ -1387,30 +1402,54 @@ enum reg_class This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ -#define REG_CLASS_CONTENTS \ -{ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ - { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \ - { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \ - { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ - { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ - { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, /* SPR_REGS */ \ - { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ - { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ - { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */ \ - { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \ - { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ - { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ - { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \ - { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \ - { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } /* ALL_REGS */ \ +#define REG_CLASS_CONTENTS \ +{ \ + /* NO_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ + /* BASE_REGS. */ \ + { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ + /* GENERAL_REGS. */ \ + { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ + /* FLOAT_REGS. */ \ + { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \ + /* ALTIVEC_REGS. */ \ + { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \ + /* VSX_REGS. */ \ + { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \ + /* VRSAVE_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \ + /* VSCR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \ + /* SPE_ACC_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \ + /* SPEFSCR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \ + /* SPR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \ + /* NON_SPECIAL_REGS. */ \ + { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \ + /* LINK_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \ + /* CTR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \ + /* LINK_OR_CTR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \ + /* SPECIAL_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \ + /* SPEC_OR_GEN_REGS. */ \ + { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \ + /* CR0_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \ + /* CR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \ + /* NON_FLOAT_REGS. */ \ + { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \ + /* CA_REGS. */ \ + { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \ + /* SPE_HIGH_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \ + /* ALL_REGS. */ \ + { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \ } /* The same information, inverted: @@ -2349,6 +2388,39 @@ extern char rs6000_reg_names[][8]; /* re &rs6000_reg_names[114][0], /* tfhar */ \ &rs6000_reg_names[115][0], /* tfiar */ \ &rs6000_reg_names[116][0], /* texasr */ \ + \ + &rs6000_reg_names[117][0], /* SPE rh0. */ \ + &rs6000_reg_names[118][0], /* SPE rh1. */ \ + &rs6000_reg_names[119][0], /* SPE rh2. */ \ + &rs6000_reg_names[120][0], /* SPE rh3. */ \ + &rs6000_reg_names[121][0], /* SPE rh4. */ \ + &rs6000_reg_names[122][0], /* SPE rh5. */ \ + &rs6000_reg_names[123][0], /* SPE rh6. */ \ + &rs6000_reg_names[124][0], /* SPE rh7. */ \ + &rs6000_reg_names[125][0], /* SPE rh8. */ \ + &rs6000_reg_names[126][0], /* SPE rh9. */ \ + &rs6000_reg_names[127][0], /* SPE rh10. */ \ + &rs6000_reg_names[128][0], /* SPE rh11. */ \ + &rs6000_reg_names[129][0], /* SPE rh12. */ \ + &rs6000_reg_names[130][0], /* SPE rh13. */ \ + &rs6000_reg_names[131][0], /* SPE rh14. */ \ + &rs6000_reg_names[132][0], /* SPE rh15. */ \ + &rs6000_reg_names[133][0], /* SPE rh16. */ \ + &rs6000_reg_names[134][0], /* SPE rh17. */ \ + &rs6000_reg_names[135][0], /* SPE rh18. */ \ + &rs6000_reg_names[136][0], /* SPE rh19. */ \ + &rs6000_reg_names[137][0], /* SPE rh20. */ \ + &rs6000_reg_names[138][0], /* SPE rh21. */ \ + &rs6000_reg_names[139][0], /* SPE rh22. */ \ + &rs6000_reg_names[140][0], /* SPE rh22. */ \ + &rs6000_reg_names[141][0], /* SPE rh24. */ \ + &rs6000_reg_names[142][0], /* SPE rh25. */ \ + &rs6000_reg_names[143][0], /* SPE rh26. */ \ + &rs6000_reg_names[144][0], /* SPE rh27. */ \ + &rs6000_reg_names[145][0], /* SPE rh28. */ \ + &rs6000_reg_names[146][0], /* SPE rh29. */ \ + &rs6000_reg_names[147][0], /* SPE rh30. */ \ + &rs6000_reg_names[148][0], /* SPE rh31. */ \ } /* Table of additional register names to use in user input. */ @@ -2404,7 +2476,17 @@ extern char rs6000_reg_names[][8]; /* re {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ /* Transactional Memory Facility (HTM) Registers. */ \ - {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116} } + {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \ + /* SPE high registers. */ \ + {"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \ + {"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \ + {"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \ + {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \ + {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \ + {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \ + {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \ + {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \ +} /* This is how to output an element of a case-vector that is relative. */ Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 213110) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -56,6 +56,8 @@ (TFHAR_REGNO 114) (TFIAR_REGNO 115) (TEXASR_REGNO 116) + (FIRST_SPE_HIGH_REGNO 117) + (LAST_SPE_HIGH_REGNO 148) ]) ;; ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-08-01 18:04 ` rohitarulraj @ 2014-08-01 18:10 ` Jakub Jelinek 2014-08-01 18:21 ` rohitarulraj 2014-08-02 1:46 ` David Edelsohn 1 sibling, 1 reply; 28+ messages in thread From: Jakub Jelinek @ 2014-08-01 18:10 UTC (permalink / raw) To: rohitarulraj Cc: Ulrich Weigand, gcc-patches, Edmar Wienskoski, dje.gcc, Alan Modra On Fri, Aug 01, 2014 at 06:03:56PM +0000, rohitarulraj@freescale.com wrote: > PR target/60102 --- libgcc/config/rs6000/linux-unwind.h (revision 213110) +++ libgcc/config/rs6000/linux-unwind.h (working copy) @@ -274,8 +274,8 @@ ppc_fallback_frame_state (struct _Unwind #ifdef __SPE__ for (i = 14; i < 32; i++) { - fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].how = REG_SAVED_OFFSET; - fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].loc.offset + fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].how = REG_SAVED_OFFSET; + fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].loc.offset = (long) ®s->vregs - new_cfa + 4 * i; } #endif is a different index, previously i + 116, newly i + 113, is that intentional? Jakub ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-08-01 18:10 ` Jakub Jelinek @ 2014-08-01 18:21 ` rohitarulraj 0 siblings, 0 replies; 28+ messages in thread From: rohitarulraj @ 2014-08-01 18:21 UTC (permalink / raw) To: Jakub Jelinek Cc: Ulrich Weigand, gcc-patches, Edmar Wienskoski, dje.gcc, Alan Modra, rohitarulraj Jakub, > On Fri, Aug 01, 2014 at 06:03:56PM +0000, rohitarulraj@freescale.com wrote: > > PR target/60102 > > --- libgcc/config/rs6000/linux-unwind.h (revision 213110) > +++ libgcc/config/rs6000/linux-unwind.h (working copy) > @@ -274,8 +274,8 @@ ppc_fallback_frame_state (struct _Unwind > #ifdef __SPE__ > for (i = 14; i < 32; i++) > { > - fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].how = REG_SAVED_OFFSET; > - fs->regs.reg[i + FIRST_PSEUDO_REGISTER - 1].loc.offset > + fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].how = REG_SAVED_OFFSET; > + fs->regs.reg[i + FIRST_SPE_HIGH_REGNO - 4].loc.offset > = (long) ®s->vregs - new_cfa + 4 * i; > } > #endif > > is a different index, previously i + 116, newly i + 113, is that intentional? > Yes, it is intentional. This part of code wasn't updated after the introduction of three HTM registers. Regards, Rohit ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-08-01 18:04 ` rohitarulraj 2014-08-01 18:10 ` Jakub Jelinek @ 2014-08-02 1:46 ` David Edelsohn 2014-08-04 10:25 ` Ulrich Weigand 1 sibling, 1 reply; 28+ messages in thread From: David Edelsohn @ 2014-08-02 1:46 UTC (permalink / raw) To: rohitarulraj Cc: Ulrich Weigand, gcc-patches, Edmar Wienskoski, Alan Modra, Jakub Jelinek On Fri, Aug 1, 2014 at 2:03 PM, rohitarulraj@freescale.com <rohitarulraj@freescale.com> wrote: > Hello Ulrich, > > Thanks. > >> > /* Use gcc hard register numbering for eh_frame. */ -#define >> >DWARF_FRAME_REGNUM(REGNO) (REGNO) >> >+#define DWARF_FRAME_REGNUM(REGNO) \ >> >+ ((REGNO) >= FIRST_SPE_HIGH_REGNO ? ((REGNO) - >> FIRST_SPE_HIGH_REGNO + >> >+1200) : (REGNO)) >> >> Any reason for not using SPE_HIGH_REGNO_P here, just in case we do get >> other hard registers at some point? > > Yes, we can use it. I just have to move the definition of "SPE_HIGH_REGNO_P" macro before "DWARF_FRAME_REGNUM" macro definition. > [Previously, I had defined and placed "SPE_HIGH_REGNO_P" macro along with similar macros "ALTIVEC_REGNO_P" etc.] > > I had updated the patch as required (For this last change, I have checked/tested only the builds: ppc64 trunk, e500v2 v4.9.1 bareboard & linux build). > > PR target/60102 > > [libgcc] > 2014-07-31 Rohit <rohitarulraj@freescale.com> > * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update > based on change in SPE high register numbers and 3 HTM registers. > > [gcc] > 2014-07-31 Rohit <rohitarulraj@freescale.com> > * config/rs6000/rs6000.c > (rs6000_reg_names) : Add SPE high register names. > (alt_reg_names) : Likewise. > (rs6000_dwarf_register_span) : For SPE high registers, replace > dwarf register numbers with GCC hard register numbers. > (rs6000_init_dwarf_reg_sizes_extra) : Likewise. > (rs6000_dbx_register_number): For SPE high registers, return dwarf > register number for the corresponding GCC hard register number. > > * config/rs6000/rs6000.h > (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard > register numbers for SPE high registers. > (DWARF_FRAME_REGISTERS) : Likewise. > (DWARF_REG_TO_UNWIND_COLUMN) : Likewise. > (DWARF_FRAME_REGNUM) : Likewise. > (FIXED_REGISTERS) : Likewise. > (CALL_USED_REGISTERS) : Likewise. > (CALL_REALLY_USED_REGISTERS) : Likewise. > (REG_ALLOC_ORDER) : Likewise. > (enum reg_class) : Likewise. > (REG_CLASS_NAMES) : Likewise. > (REG_CLASS_CONTENTS) : Likewise. > (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. > > * gcc.target/powerpc/pr60102.c: New testcase. The patch is okay with me if Uli is satisfied. Thanks, David ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-08-02 1:46 ` David Edelsohn @ 2014-08-04 10:25 ` Ulrich Weigand 2014-08-04 16:56 ` Edmar 0 siblings, 1 reply; 28+ messages in thread From: Ulrich Weigand @ 2014-08-04 10:25 UTC (permalink / raw) To: David Edelsohn Cc: rohitarulraj, gcc-patches, Edmar Wienskoski, Alan Modra, Jakub Jelinek David Edelsohn wrote: > On Fri, Aug 1, 2014 at 2:03 PM, rohitarulraj@freescale.com > <rohitarulraj@freescale.com> wrote: > > [libgcc] > > 2014-07-31 Rohit <rohitarulraj@freescale.com> > > * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update > > based on change in SPE high register numbers and 3 HTM registers. > > > > [gcc] > > 2014-07-31 Rohit <rohitarulraj@freescale.com> > > * config/rs6000/rs6000.c > > (rs6000_reg_names) : Add SPE high register names. > > (alt_reg_names) : Likewise. > > (rs6000_dwarf_register_span) : For SPE high registers, replace > > dwarf register numbers with GCC hard register numbers. > > (rs6000_init_dwarf_reg_sizes_extra) : Likewise. > > (rs6000_dbx_register_number): For SPE high registers, return dwarf > > register number for the corresponding GCC hard register number. > > > > * config/rs6000/rs6000.h > > (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard > > register numbers for SPE high registers. > > (DWARF_FRAME_REGISTERS) : Likewise. > > (DWARF_REG_TO_UNWIND_COLUMN) : Likewise. > > (DWARF_FRAME_REGNUM) : Likewise. > > (FIXED_REGISTERS) : Likewise. > > (CALL_USED_REGISTERS) : Likewise. > > (CALL_REALLY_USED_REGISTERS) : Likewise. > > (REG_ALLOC_ORDER) : Likewise. > > (enum reg_class) : Likewise. > > (REG_CLASS_NAMES) : Likewise. > > (REG_CLASS_CONTENTS) : Likewise. > > (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. > > > > * gcc.target/powerpc/pr60102.c: New testcase. > > The patch is okay with me if Uli is satisfied. Yes, this is fine with me. Bye, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain Ulrich.Weigand@de.ibm.com ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-08-04 10:25 ` Ulrich Weigand @ 2014-08-04 16:56 ` Edmar 2014-08-05 8:11 ` Jakub Jelinek 2014-09-28 22:23 ` Maciej W. Rozycki 0 siblings, 2 replies; 28+ messages in thread From: Edmar @ 2014-08-04 16:56 UTC (permalink / raw) To: Ulrich Weigand Cc: David Edelsohn, rohitarulraj, gcc-patches, Alan Modra, Jakub Jelinek Committed on trunk, revision 213596 Committed on 4.9 branch, revision 213597 I made an omission on the first commit. I did not add the test case and corresponding ChangeLog entry. Committed as obvious on trunk, revision 213598 Thanks Edmar On 08/04/2014 05:25 AM, Ulrich Weigand wrote: > David Edelsohn wrote: >> On Fri, Aug 1, 2014 at 2:03 PM, rohitarulraj@freescale.com >> <rohitarulraj@freescale.com> wrote: >>> [libgcc] >>> 2014-07-31 Rohit<rohitarulraj@freescale.com> >>> * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update >>> based on change in SPE high register numbers and 3 HTM registers. >>> >>> [gcc] >>> 2014-07-31 Rohit<rohitarulraj@freescale.com> >>> * config/rs6000/rs6000.c >>> (rs6000_reg_names) : Add SPE high register names. >>> (alt_reg_names) : Likewise. >>> (rs6000_dwarf_register_span) : For SPE high registers, replace >>> dwarf register numbers with GCC hard register numbers. >>> (rs6000_init_dwarf_reg_sizes_extra) : Likewise. >>> (rs6000_dbx_register_number): For SPE high registers, return dwarf >>> register number for the corresponding GCC hard register number. >>> >>> * config/rs6000/rs6000.h >>> (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard >>> register numbers for SPE high registers. >>> (DWARF_FRAME_REGISTERS) : Likewise. >>> (DWARF_REG_TO_UNWIND_COLUMN) : Likewise. >>> (DWARF_FRAME_REGNUM) : Likewise. >>> (FIXED_REGISTERS) : Likewise. >>> (CALL_USED_REGISTERS) : Likewise. >>> (CALL_REALLY_USED_REGISTERS) : Likewise. >>> (REG_ALLOC_ORDER) : Likewise. >>> (enum reg_class) : Likewise. >>> (REG_CLASS_NAMES) : Likewise. >>> (REG_CLASS_CONTENTS) : Likewise. >>> (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. >>> >>> * gcc.target/powerpc/pr60102.c: New testcase. >> The patch is okay with me if Uli is satisfied. > Yes, this is fine with me. > > Bye, > Ulrich > ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-08-04 16:56 ` Edmar @ 2014-08-05 8:11 ` Jakub Jelinek 2014-08-05 10:44 ` rohitarulraj 2014-08-05 14:47 ` Edmar 2014-09-28 22:23 ` Maciej W. Rozycki 1 sibling, 2 replies; 28+ messages in thread From: Jakub Jelinek @ 2014-08-05 8:11 UTC (permalink / raw) To: Edmar Cc: Ulrich Weigand, David Edelsohn, rohitarulraj, gcc-patches, Alan Modra On Mon, Aug 04, 2014 at 11:51:34AM -0500, Edmar wrote: > Committed on trunk, revision 213596 > Committed on 4.9 branch, revision 213597 Note the ChangeLog entry was grossly misformated. I've fixed it up in gcc/ChangeLog on the trunk, but not on the branch nor in libgcc. There should be no space before :, all lines in ChangeLog entry should be just tab indented rather than tab + 2 spaces, and filenames, unless they are too long, shouldn't be alone on the lines. And testsuite entries shouldn't go into gcc/ChangeLog. > On 08/04/2014 05:25 AM, Ulrich Weigand wrote: > >David Edelsohn wrote: > >>On Fri, Aug 1, 2014 at 2:03 PM, rohitarulraj@freescale.com > >><rohitarulraj@freescale.com> wrote: > >>>[libgcc] > >>>2014-07-31 Rohit<rohitarulraj@freescale.com> > >>> * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update > >>> based on change in SPE high register numbers and 3 HTM registers. > >>> > >>>[gcc] > >>>2014-07-31 Rohit<rohitarulraj@freescale.com> > >>> * config/rs6000/rs6000.c > >>> (rs6000_reg_names) : Add SPE high register names. > >>> (alt_reg_names) : Likewise. > >>> (rs6000_dwarf_register_span) : For SPE high registers, replace > >>> dwarf register numbers with GCC hard register numbers. > >>> (rs6000_init_dwarf_reg_sizes_extra) : Likewise. > >>> (rs6000_dbx_register_number): For SPE high registers, return dwarf > >>> register number for the corresponding GCC hard register number. > >>> > >>> * config/rs6000/rs6000.h > >>> (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard > >>> register numbers for SPE high registers. > >>> (DWARF_FRAME_REGISTERS) : Likewise. > >>> (DWARF_REG_TO_UNWIND_COLUMN) : Likewise. > >>> (DWARF_FRAME_REGNUM) : Likewise. > >>> (FIXED_REGISTERS) : Likewise. > >>> (CALL_USED_REGISTERS) : Likewise. > >>> (CALL_REALLY_USED_REGISTERS) : Likewise. > >>> (REG_ALLOC_ORDER) : Likewise. > >>> (enum reg_class) : Likewise. > >>> (REG_CLASS_NAMES) : Likewise. > >>> (REG_CLASS_CONTENTS) : Likewise. > >>> (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. > >>> > >>> * gcc.target/powerpc/pr60102.c: New testcase. > >>The patch is okay with me if Uli is satisfied. > >Yes, this is fine with me. Jakub ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-08-05 8:11 ` Jakub Jelinek @ 2014-08-05 10:44 ` rohitarulraj 2014-08-05 14:47 ` Edmar 1 sibling, 0 replies; 28+ messages in thread From: rohitarulraj @ 2014-08-05 10:44 UTC (permalink / raw) To: Edmar Wienskoski, Jakub Jelinek Cc: Ulrich Weigand, David Edelsohn, gcc-patches, Alan Modra, rohitarulraj [-- Attachment #1: Type: text/plain, Size: 786 bytes --] Jakub, > On Mon, Aug 04, 2014 at 11:51:34AM -0500, Edmar wrote: > > Committed on trunk, revision 213596 > > Committed on 4.9 branch, revision 213597 > > Note the ChangeLog entry was grossly misformated. > I've fixed it up in gcc/ChangeLog on the trunk, but not on the branch > nor in libgcc. There should be no space before :, all lines > in ChangeLog entry should be just tab indented rather than tab + 2 spaces, > and filenames, unless they are too long, shouldn't be alone on the lines. > And testsuite entries shouldn't go into gcc/ChangeLog. Sorry about that. I have updated the ChangeLog entries accordingly. Edmar, can you please commit these patches? Trunk: pr60102-ChangeLog-trunk.patch GCC v4.9 branch: pr60102-ChangeLog-v49.patch Regards, Rohit [-- Attachment #2: pr60102-ChangeLog-trunk.patch --] [-- Type: application/octet-stream, Size: 459 bytes --] Index: libgcc/ChangeLog =================================================================== --- libgcc/ChangeLog (revision 213623) +++ libgcc/ChangeLog (working copy) @@ -2,7 +2,7 @@ PR target/60102 * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update - based on change in SPE high register numbers and 3 HTM registers. + based on change in SPE high register numbers and 3 HTM registers. 2014-08-01 Nathan Sidwell <nathan@acm.org> [-- Attachment #3: pr60102-ChangeLog-v49.patch --] [-- Type: application/octet-stream, Size: 2769 bytes --] Index: libgcc/ChangeLog =================================================================== --- libgcc/ChangeLog (revision 213627) +++ libgcc/ChangeLog (working copy) @@ -2,7 +2,7 @@ PR target/60102 * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update - based on change in SPE high register numbers and 3 HTM registers. + based on change in SPE high register numbers and 3 HTM registers. 2014-07-16 Release Manager Index: gcc/ChangeLog =================================================================== --- gcc/ChangeLog (revision 213627) +++ gcc/ChangeLog (working copy) @@ -1,29 +1,27 @@ 2014-08-04 Rohit <rohitarulraj@freescale.com> PR target/60102 - * config/rs6000/rs6000.c - (rs6000_reg_names) : Add SPE high register names. - (alt_reg_names) : Likewise. - (rs6000_dwarf_register_span) : For SPE high registers, replace - dwarf register numbers with GCC hard register numbers. - (rs6000_init_dwarf_reg_sizes_extra) : Likewise. - (rs6000_dbx_register_number): For SPE high registers, return dwarf - register number for the corresponding GCC hard register number. - * config/rs6000/rs6000.h - (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard - register numbers for SPE high registers. - (DWARF_FRAME_REGISTERS) : Likewise. - (DWARF_REG_TO_UNWIND_COLUMN) : Likewise. - (DWARF_FRAME_REGNUM) : Likewise. - (FIXED_REGISTERS) : Likewise. - (CALL_USED_REGISTERS) : Likewise. - (CALL_REALLY_USED_REGISTERS) : Likewise. - (REG_ALLOC_ORDER) : Likewise. - (enum reg_class) : Likewise. - (REG_CLASS_NAMES) : Likewise. - (REG_CLASS_CONTENTS) : Likewise. - (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. - * gcc.target/powerpc/pr60102.c: New testcase. + * config/rs6000/rs6000.c (rs6000_reg_names): Add SPE high register + names. + (alt_reg_names): Likewise. + (rs6000_dwarf_register_span): For SPE high registers, replace + dwarf register numbers with GCC hard register numbers. + (rs6000_init_dwarf_reg_sizes_extra): Likewise. + (rs6000_dbx_register_number): For SPE high registers, return dwarf + register number for the corresponding GCC hard register number. + * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Update based on 32 + newly added GCC hard register numbers for SPE high registers. + (DWARF_FRAME_REGISTERS): Likewise. + (DWARF_REG_TO_UNWIND_COLUMN): Likewise. + (DWARF_FRAME_REGNUM): Likewise. + (FIXED_REGISTERS): Likewise. + (CALL_USED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (enum reg_class): Likewise. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + (SPE_HIGH_REGNO_P): New macro to identify SPE high registers. 2014-08-01 Vladimir Makarov <vmakarov@redhat.com> ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-08-05 8:11 ` Jakub Jelinek 2014-08-05 10:44 ` rohitarulraj @ 2014-08-05 14:47 ` Edmar 1 sibling, 0 replies; 28+ messages in thread From: Edmar @ 2014-08-05 14:47 UTC (permalink / raw) To: Jakub Jelinek Cc: Ulrich Weigand, David Edelsohn, rohitarulraj, gcc-patches, Alan Modra Jackub, Thanks for point this up. I apologize for the sloppiness. I fixed and committed the ChangeLogs on the branch, revision 213639 Also fixed the libgcc ChangeLog on trunk. Revision 213640 Edmar On 08/05/2014 03:11 AM, Jakub Jelinek wrote: > On Mon, Aug 04, 2014 at 11:51:34AM -0500, Edmar wrote: >> Committed on trunk, revision 213596 >> Committed on 4.9 branch, revision 213597 > Note the ChangeLog entry was grossly misformated. > I've fixed it up in gcc/ChangeLog on the trunk, but not on the branch > nor in libgcc. There should be no space before :, all lines > in ChangeLog entry should be just tab indented rather than tab + 2 spaces, > and filenames, unless they are too long, shouldn't be alone on the lines. > And testsuite entries shouldn't go into gcc/ChangeLog. > >> On 08/04/2014 05:25 AM, Ulrich Weigand wrote: >>> David Edelsohn wrote: >>>> On Fri, Aug 1, 2014 at 2:03 PM, rohitarulraj@freescale.com >>>> <rohitarulraj@freescale.com> wrote: >>>>> [libgcc] >>>>> 2014-07-31 Rohit<rohitarulraj@freescale.com> >>>>> * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update >>>>> based on change in SPE high register numbers and 3 HTM registers. >>>>> >>>>> [gcc] >>>>> 2014-07-31 Rohit<rohitarulraj@freescale.com> >>>>> * config/rs6000/rs6000.c >>>>> (rs6000_reg_names) : Add SPE high register names. >>>>> (alt_reg_names) : Likewise. >>>>> (rs6000_dwarf_register_span) : For SPE high registers, replace >>>>> dwarf register numbers with GCC hard register numbers. >>>>> (rs6000_init_dwarf_reg_sizes_extra) : Likewise. >>>>> (rs6000_dbx_register_number): For SPE high registers, return dwarf >>>>> register number for the corresponding GCC hard register number. >>>>> >>>>> * config/rs6000/rs6000.h >>>>> (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard >>>>> register numbers for SPE high registers. >>>>> (DWARF_FRAME_REGISTERS) : Likewise. >>>>> (DWARF_REG_TO_UNWIND_COLUMN) : Likewise. >>>>> (DWARF_FRAME_REGNUM) : Likewise. >>>>> (FIXED_REGISTERS) : Likewise. >>>>> (CALL_USED_REGISTERS) : Likewise. >>>>> (CALL_REALLY_USED_REGISTERS) : Likewise. >>>>> (REG_ALLOC_ORDER) : Likewise. >>>>> (enum reg_class) : Likewise. >>>>> (REG_CLASS_NAMES) : Likewise. >>>>> (REG_CLASS_CONTENTS) : Likewise. >>>>> (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. >>>>> >>>>> * gcc.target/powerpc/pr60102.c: New testcase. >>>> The patch is okay with me if Uli is satisfied. >>> Yes, this is fine with me. > Jakub > . > ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-08-04 16:56 ` Edmar 2014-08-05 8:11 ` Jakub Jelinek @ 2014-09-28 22:23 ` Maciej W. Rozycki 2014-09-29 9:44 ` Ulrich Weigand 1 sibling, 1 reply; 28+ messages in thread From: Maciej W. Rozycki @ 2014-09-28 22:23 UTC (permalink / raw) To: Edmar Cc: Ulrich Weigand, David Edelsohn, rohitarulraj, gcc-patches, Alan Modra, Jakub Jelinek, gdb On Mon, 4 Aug 2014, Edmar wrote: > Committed on trunk, revision 213596 > Committed on 4.9 branch, revision 213597 This change regressed GDB for e500v2 multilibs, presumably because it does not understand the new DWARF register numbers and does not know how to map them to hardware registers. Here's the full list of regressions observed: FAIL: gdb.base/store.exp: var double l; print old l, expecting -1 FAIL: gdb.base/store.exp: var double l; print old r, expecting -2 FAIL: gdb.base/store.exp: var double l; print incremented l, expecting 2 FAIL: gdb.base/store.exp: var doublest l; print old l, expecting -1 FAIL: gdb.base/store.exp: var doublest l; print old r, expecting -2 FAIL: gdb.base/store.exp: var doublest l; print new l, expecting 4 FAIL: gdb.base/store.exp: var doublest l; print incremented l, expecting 2 FAIL: gdb.base/store.exp: upvar double l; print old l, expecting -1 FAIL: gdb.base/store.exp: upvar double l; print old r, expecting -2 UNRESOLVED: gdb.base/store.exp: upvar double l; set l to 4 UNRESOLVED: gdb.base/store.exp: upvar double l; print new l, expecting 4 FAIL: gdb.base/store.exp: upvar doublest l; print old l, expecting -1 FAIL: gdb.base/store.exp: upvar doublest l; print old r, expecting -2 UNRESOLVED: gdb.base/store.exp: upvar doublest l; set l to 4 UNRESOLVED: gdb.base/store.exp: upvar doublest l; print new l, expecting 4 These tests all used to score a PASS status. Do you plan to address this problem anyhow? Maciej ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-09-28 22:23 ` Maciej W. Rozycki @ 2014-09-29 9:44 ` Ulrich Weigand 2014-09-29 10:24 ` rohitarulraj 0 siblings, 1 reply; 28+ messages in thread From: Ulrich Weigand @ 2014-09-29 9:44 UTC (permalink / raw) To: Maciej W. Rozycki Cc: Edmar, David Edelsohn, rohitarulraj, gcc-patches, Alan Modra, Jakub Jelinek Maciej W. Rozycki wrote: > On Mon, 4 Aug 2014, Edmar wrote: > > > Committed on trunk, revision 213596 > > Committed on 4.9 branch, revision 213597 > > This change regressed GDB for e500v2 multilibs, presumably because it > does not understand the new DWARF register numbers and does not know how > to map them to hardware registers. As I understand it, the change was supposed to only affect GCC internals, all externally generated debug info was supposed to remain unchanged. If there are changes in debug info, something must have gone wrong. Bye, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain Ulrich.Weigand@de.ibm.com ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-09-29 9:44 ` Ulrich Weigand @ 2014-09-29 10:24 ` rohitarulraj 2014-09-29 17:26 ` Maciej W. Rozycki 2014-10-06 15:48 ` rohitarulraj 0 siblings, 2 replies; 28+ messages in thread From: rohitarulraj @ 2014-09-29 10:24 UTC (permalink / raw) To: Ulrich Weigand, Maciej W. Rozycki Cc: Edmar Wienskoski, David Edelsohn, gcc-patches, Alan Modra, Jakub Jelinek, rohitarulraj > From: Ulrich Weigand [mailto:uweigand@de.ibm.com] > Maciej W. Rozycki wrote: > > On Mon, 4 Aug 2014, Edmar wrote: > > > > > Committed on trunk, revision 213596 > > > Committed on 4.9 branch, revision 213597 > > > > This change regressed GDB for e500v2 multilibs, presumably because it > > does not understand the new DWARF register numbers and does not know > > how to map them to hardware registers. > > As I understand it, the change was supposed to only affect GCC internals, all > externally generated debug info was supposed to remain unchanged. > > If there are changes in debug info, something must have gone wrong. Let me check if I can track this down. Regards, Rohit ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-09-29 10:24 ` rohitarulraj @ 2014-09-29 17:26 ` Maciej W. Rozycki 2014-10-06 15:48 ` rohitarulraj 1 sibling, 0 replies; 28+ messages in thread From: Maciej W. Rozycki @ 2014-09-29 17:26 UTC (permalink / raw) To: rohitarulraj Cc: Ulrich Weigand, Edmar Wienskoski, David Edelsohn, gcc-patches, Alan Modra, Jakub Jelinek On Mon, 29 Sep 2014, rohitarulraj@freescale.com wrote: > > As I understand it, the change was supposed to only affect GCC internals, all > > externally generated debug info was supposed to remain unchanged. > > > > If there are changes in debug info, something must have gone wrong. > > Let me check if I can track this down. Thanks. In case that helps the multilib flags I used for this testing were: -mcpu=8548 -mfloat-gprs=double -mspe=yes -mabi=spe Maciej ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-09-29 10:24 ` rohitarulraj 2014-09-29 17:26 ` Maciej W. Rozycki @ 2014-10-06 15:48 ` rohitarulraj 2014-10-08 18:09 ` Ulrich Weigand 1 sibling, 1 reply; 28+ messages in thread From: rohitarulraj @ 2014-10-06 15:48 UTC (permalink / raw) To: Ulrich Weigand, Maciej W. Rozycki Cc: Edmar Wienskoski, David Edelsohn, gcc-patches, Alan Modra, Jakub Jelinek, rohitarulraj > From: Dharmakan Rohit-B30502 > Sent: Monday, September 29, 2014 3:54 PM > > > From: Ulrich Weigand [mailto:uweigand@de.ibm.com] Maciej W. Rozycki > > wrote: > > > On Mon, 4 Aug 2014, Edmar wrote: > > > > > > > Committed on trunk, revision 213596 Committed on 4.9 branch, > > > > revision 213597 > > > > > > This change regressed GDB for e500v2 multilibs, presumably because > > > it does not understand the new DWARF register numbers and does not > > > know how to map them to hardware registers. > > > > As I understand it, the change was supposed to only affect GCC > > internals, all externally generated debug info was supposed to remain > unchanged. > > > > If there are changes in debug info, something must have gone wrong. > > Let me check if I can track this down. Maciej/Ulrich, I was able to narrow down the issue. Debug info generated with the current patch: <2><334>: Abbrev Number: 10 (DW_TAG_formal_parameter) <335> DW_AT_name : u <337> DW_AT_decl_file : 1 <338> DW_AT_decl_line : 51 <339> DW_AT_type : <0x357> <33d> DW_AT_location : 7 byte block: 90 7d 93 4 58 93 4 (DW_OP_regx: 125 (r125); DW_OP_piece: 4; DW_OP_reg8 (r8); DW_OP_piece: 4) Expected debug info: <2><334>: Abbrev Number: 10 (DW_TAG_formal_parameter) <335> DW_AT_name : u <337> DW_AT_decl_file : 1 <338> DW_AT_decl_line : 51 <339> DW_AT_type : <0x359> <33d> DW_AT_location : 8 byte block: 90 b8 9 93 4 58 93 4 (DW_OP_regx: 1208 (r1208); DW_OP_piece: 4; DW_OP_reg8 (r8); DW_OP_piece: 4) While emitting the location descriptors of multiple registers (SPE high/low part) individually, the GCC hard register number is converted in to DWARF register number using "dbx_reg_number" [Statement "A", "B" & "C" below]. File1: gcc-4.9/gcc/config/rs6000/rs6000.h ================================= ... /* Use standard DWARF numbering for DWARF debugging information. */ #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) ---------------------------------------------------------(A) ... File2: gcc-4.9/gcc/dwarf2out.c ========================= /* Given an RTL of a register, return a location descriptor that designates a value that spans more than one register. */ static dw_loc_descr_ref multiple_reg_loc_descriptor (rtx rtl, rtx regs, enum var_init_status initialized) { ... /* Now onto stupid register sets in non contiguous locations. */ .... for (i = 0; i < XVECLEN (regs, 0); ++i) { dw_loc_descr_ref t; t = one_reg_loc_descriptor (dbx_reg_number (XVECEXP (regs, 0, i)), VAR_INIT_STATUS_INITIALIZED); -------------------------------(B) ... } ..... } static unsigned int dbx_reg_number (const_rtx rtl) { .... .... regno = DBX_REGISTER_NUMBER (regno); -------------------------------------------------------------------------------------------------------------(C) gcc_assert (regno != INVALID_REGNUM); return regno; } File3:gcc-4.9/gcc/config/rs6000/sysv4.h =============================== .... /* This target uses the sysv4.opt file. */ #define TARGET_USES_SYSV4_OPT 1 #undef DBX_REGISTER_NUMBER ----------------------------------------------------------------------------------------------------------(D) .... But statement "C" macro "DBX_REGISTER_NUMBER" gets undefined by statement "D" hence the GCC hard register number gets emitted in the debug info instead of DWARF register number. Previously, without this patch for SPE high registers the GCC hard register number was same as the DWARF register number (1200 onwards), hence we didn't see this issue. Removing statement "D" from "sysv4.h" file so as to generate expected DWARF register number does work, but will there be any side effects? Regards, Rohit ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-10-06 15:48 ` rohitarulraj @ 2014-10-08 18:09 ` Ulrich Weigand 2014-10-08 18:27 ` David Edelsohn 2014-10-08 19:47 ` Maciej W. Rozycki 0 siblings, 2 replies; 28+ messages in thread From: Ulrich Weigand @ 2014-10-08 18:09 UTC (permalink / raw) To: rohitarulraj Cc: Maciej W. Rozycki, Edmar Wienskoski, David Edelsohn, gcc-patches, Alan Modra, Jakub Jelinek rohitarulraj wrote: > I was able to narrow down the issue. [snip] > While emitting the location descriptors of multiple registers (SPE high/low > part) individually, the GCC hard register number is converted in to DWARF > register number using "dbx_reg_number" [Statement "A", "B" & "C" below]. > But statement "C" macro "DBX_REGISTER_NUMBER" gets undefined by statement > "D" hence the GCC hard register number gets emitted in the debug info > instead of DWARF register number. Previously, without this patch for SPE > high registers the GCC hard register number was same as the DWARF register > number (1200 onwards), hence we didn't see this issue. > > Removing statement "D" from "sysv4.h" file so as to generate expected > DWARF register number does work, but will there be any side effects? Ah, I had completely forgotten about this issue, sorry ... The problem with DBX_REGISTER_NUMBER is actually described in detail here: https://gcc.gnu.org/ml/gcc-patches/2012-11/msg02136.html At the time, we decided to not remove the #undef DBX_REGISTER_NUMBER to avoid compatibility issues, but use GCC internal numbers in .debug_frame and .debug_info on Linux (option (3) in the above mail). However, this was never actually implemented. Looking at the current status, there are three groups of rs6000 targets: - Some use the DBX_REGISTER_NUMBER definition from rs6000.h: These are only AIX and Darwin. - Some provide their own definition of DBX_REGISTER_NUMBER after the rs6000.h one was undefined by sysv4.h: These are FreeBSD, NetBSD, and Lynx. - All other targets do not have DBX_REGISTER_NUMBER because it is undefined by sysv4.h, and therefore using GCC internal register numbers: These are Linux, rtems, vxworks, and all ELF/EABI targets. The following patch tries to remove the unfortunate confusion about undefining and redefining DBX_REGISTER_NUMBER, while keeping the behavior on all targets unchanged with the following two exceptions: - fix the SPE problem by always translating high register numbers - implement option (3) above by not replacing CR2 with CR in .debug_frame on targets that do not use the standard DWARF register numbering The way this works is to have a common, simple implementation of DBX_REGISTER_NUMBER and DWARF2_FRAME_REG_OUT for all targets that just calls to the rs6000_dbx_register_number routine, passing an extra format argument that decides whether the register number is to be used for .debug_info, .debug_frame, or .eh_frame. In order to ensure rs6000_dbx_register_number always gets a GCC internal number as input, DWARF_FRAME_REGNUM has to be again defined as identity map. All the logic to decide debug register numbers is now contained in that single place. However, in order to maintain current behavior, we still have to distinguish between platforms that want to use the standard DWARF register numbering scheme, and those that use GCC internal numbers. This is now simply done by having the former provide a new define RS6000_USE_DWARF_NUMBERING in a target header file. Tested on powerpc64le-linux and powerpc64-linux. Rohit, could you verify whether this fixes the SPE problem? David, does this approach look reasonable to you? Bye, Ulrich ChangeLog: * config/rs6000/rs6000.h (DBX_REGISTER_NUMBER): Pass format argument to rs6000_dbx_register_number. (DWARF_FRAME_REGNUM): Redefine as identity map. (DWARF2_FRAME_REG_OUT): Call rs6000_dbx_register_number. * config/rs6000/rs6000-protos.h (rs6000_dbx_register_number): Update. * config/rs6000/rs6000.c (rs6000_dbx_register_number): Add format argument to handle .debug_frame and .eh_frame directly. Always translate SPE high register numbers. Add special treatment for CR, but only in .debug_frame. Respect RS6000_USE_DWARF_NUMBERING. * config/rs6000/sysv.h (DBX_REGISTER_NUMBER): Do not undefine. * config/rs6000/freebsd.h (DBX_REGISTER_NUMBER): Remove. (RS6000_USE_DWARF_NUMBERING): Define. * config/rs6000/freebsd64.h (DBX_REGISTER_NUMBER): Remove. (RS6000_USE_DWARF_NUMBERING): Define. * config/rs6000/netbsd.h (DBX_REGISTER_NUMBER): Remove. (RS6000_USE_DWARF_NUMBERING): Define. * config/rs6000/lynx.h (DBX_REGISTER_NUMBER): Remove. (RS6000_USE_DWARF_NUMBERING): Define. * config/rs6000/aix.h (RS6000_USE_DWARF_NUMBERING): Define. * config/rs6000/darwin.h (RS6000_USE_DWARF_NUMBERING): Define. Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 215999) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -947,23 +947,16 @@ enum data_align { align_abi, align_opt, ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) /* Use standard DWARF numbering for DWARF debugging information. */ -#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) +#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) /* Use gcc hard register numbering for eh_frame. */ -#define DWARF_FRAME_REGNUM(REGNO) \ - (SPE_HIGH_REGNO_P (REGNO) ? ((REGNO) - FIRST_SPE_HIGH_REGNO + 1200) : (REGNO)) +#define DWARF_FRAME_REGNUM(REGNO) (REGNO) /* Map register numbers held in the call frame info that gcc has collected using DWARF_FRAME_REGNUM to those that should be output in - .debug_frame and .eh_frame. We continue to use gcc hard reg numbers - for .eh_frame, but use the numbers mandated by the various ABIs for - .debug_frame. rs6000_emit_prologue has translated any combination of - CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves - the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */ -#define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ - ((FOR_EH) ? (REGNO) \ - : (REGNO) == CR2_REGNO ? 64 \ - : DBX_REGISTER_NUMBER (REGNO)) + .debug_frame and .eh_frame. */ +#define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ + rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1) /* 1 for registers that have pervasive standard uses and are not available for the register allocator. Index: gcc/config/rs6000/rs6000-protos.h =================================================================== --- gcc/config/rs6000/rs6000-protos.h (revision 215999) +++ gcc/config/rs6000/rs6000-protos.h (working copy) @@ -188,7 +188,7 @@ extern int rs6000_trampoline_size (void) extern alias_set_type get_TOC_alias_set (void); extern void rs6000_emit_prologue (void); extern void rs6000_emit_load_toc_table (int); -extern unsigned int rs6000_dbx_register_number (unsigned int); +extern unsigned int rs6000_dbx_register_number (unsigned int, unsigned int); extern void rs6000_emit_epilogue (int); extern void rs6000_emit_eh_reg_restore (rtx, rtx); extern const char * output_isel (rtx *); Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 215999) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -31581,17 +31581,40 @@ rs6000_init_dwarf_reg_sizes_extra (tree } } -/* Map internal gcc register numbers to DWARF2 register numbers. */ +/* Map internal gcc register numbers to debug format register numbers. + FORMAT specifies the type of debug register number to use: + 0 -- debug information, except for frame-related sections + 1 -- DWARF .debug_frame section + 2 -- DWARF .eh_frame section */ unsigned int -rs6000_dbx_register_number (unsigned int regno) +rs6000_dbx_register_number (unsigned int regno, unsigned int format) { - if (regno <= 63 || write_symbols != DWARF2_DEBUG) + /* We never use the GCC internal number for SPE high registers. + Those are mapped to the 1200..1231 range for all debug formats. */ + if (SPE_HIGH_REGNO_P (regno)) + return regno - FIRST_SPE_HIGH_REGNO + 1200; + + /* Except for the above, we use the internal number for non-DWARF + debug information, and also for .eh_frame. */ + if ((format == 0 && write_symbols != DWARF2_DEBUG) || format == 2) + return regno; + + /* On some platforms, we use the standard DWARF register + numbering for .debug_info and .debug_frame. */ +#ifdef RS6000_USE_DWARF_NUMBERING + if (regno <= 63) return regno; if (regno == LR_REGNO) return 108; if (regno == CTR_REGNO) return 109; + /* Special handling for CR for .debug_frame: rs6000_emit_prologue has + translated any combination of CR2, CR3, CR4 saves to a save of CR2. + The actual code emitted saves the whole of CR, so we map CR2_REGNO + to the DWARF reg for CR. */ + if (format == 1 && regno == CR2_REGNO) + return 64; if (CR_REGNO_P (regno)) return regno - CR0_REGNO + 86; if (regno == CA_REGNO) @@ -31606,8 +31629,7 @@ rs6000_dbx_register_number (unsigned int return 99; if (regno == SPEFSCR_REGNO) return 612; - if (SPE_HIGH_REGNO_P (regno)) - return regno - FIRST_SPE_HIGH_REGNO + 1200; +#endif return regno; } Index: gcc/config/rs6000/sysv4.h =================================================================== --- gcc/config/rs6000/sysv4.h (revision 215999) +++ gcc/config/rs6000/sysv4.h (working copy) @@ -949,4 +949,3 @@ ncrtn.o%s" /* This target uses the sysv4.opt file. */ #define TARGET_USES_SYSV4_OPT 1 -#undef DBX_REGISTER_NUMBER Index: gcc/config/rs6000/freebsd.h =================================================================== --- gcc/config/rs6000/freebsd.h (revision 215999) +++ gcc/config/rs6000/freebsd.h (working copy) @@ -73,6 +73,7 @@ #define RELOCATABLE_NEEDS_FIXUP \ (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE) -#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) +/* Use standard DWARF numbering for DWARF debugging information. */ +#define RS6000_USE_DWARF_NUMBERING #define POWERPC_FREEBSD Index: gcc/config/rs6000/freebsd64.h =================================================================== --- gcc/config/rs6000/freebsd64.h (revision 215999) +++ gcc/config/rs6000/freebsd64.h (working copy) @@ -362,7 +362,8 @@ extern int dot_symbols; /* The default value isn't sufficient in 64-bit mode. */ #define STACK_CHECK_PROTECT (TARGET_64BIT ? 16 * 1024 : 12 * 1024) -#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) +/* Use standard DWARF numbering for DWARF debugging information. */ +#define RS6000_USE_DWARF_NUMBERING /* PowerPC64 Linux word-aligns FP doubles when -malign-power is given. */ #undef ADJUST_FIELD_ALIGN Index: gcc/config/rs6000/netbsd.h =================================================================== --- gcc/config/rs6000/netbsd.h (revision 215999) +++ gcc/config/rs6000/netbsd.h (working copy) @@ -87,4 +87,6 @@ { "netbsd_endfile_spec", NETBSD_ENDFILE_SPEC }, -#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) +/* Use standard DWARF numbering for DWARF debugging information. */ +#define RS6000_USE_DWARF_NUMBERING + Index: gcc/config/rs6000/lynx.h =================================================================== --- gcc/config/rs6000/lynx.h (revision 215999) +++ gcc/config/rs6000/lynx.h (working copy) @@ -99,7 +99,8 @@ #undef HAVE_AS_TLS #define HAVE_AS_TLS 0 -#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) +/* Use standard DWARF numbering for DWARF debugging information. */ +#define RS6000_USE_DWARF_NUMBERING #ifdef CRT_BEGIN /* This function is part of crtbegin*.o which is at the beginning of Index: gcc/config/rs6000/aix.h =================================================================== --- gcc/config/rs6000/aix.h (revision 215999) +++ gcc/config/rs6000/aix.h (working copy) @@ -223,3 +223,7 @@ /* Static stack checking is supported by means of probes. */ #define STACK_CHECK_STATIC_BUILTIN 1 + +/* Use standard DWARF numbering for DWARF debugging information. */ +#define RS6000_USE_DWARF_NUMBERING + Index: gcc/config/rs6000/darwin.h =================================================================== --- gcc/config/rs6000/darwin.h (revision 215999) +++ gcc/config/rs6000/darwin.h (working copy) @@ -424,3 +424,7 @@ do { \ /* So far, there is no rs6000_fold_builtin, if one is introduced, then this will need to be modified similar to the x86 case. */ #define TARGET_FOLD_BUILTIN SUBTARGET_FOLD_BUILTIN + +/* Use standard DWARF numbering for DWARF debugging information. */ +#define RS6000_USE_DWARF_NUMBERING + -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain Ulrich.Weigand@de.ibm.com ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-10-08 18:09 ` Ulrich Weigand @ 2014-10-08 18:27 ` David Edelsohn 2014-10-08 19:47 ` Maciej W. Rozycki 1 sibling, 0 replies; 28+ messages in thread From: David Edelsohn @ 2014-10-08 18:27 UTC (permalink / raw) To: Ulrich Weigand Cc: rohitarulraj, Maciej W. Rozycki, Edmar Wienskoski, gcc-patches, Alan Modra, Jakub Jelinek On Wed, Oct 8, 2014 at 2:09 PM, Ulrich Weigand <uweigand@de.ibm.com> wrote: > rohitarulraj wrote: > >> I was able to narrow down the issue. > [snip] >> While emitting the location descriptors of multiple registers (SPE high/low >> part) individually, the GCC hard register number is converted in to DWARF >> register number using "dbx_reg_number" [Statement "A", "B" & "C" below]. > >> But statement "C" macro "DBX_REGISTER_NUMBER" gets undefined by statement >> "D" hence the GCC hard register number gets emitted in the debug info >> instead of DWARF register number. Previously, without this patch for SPE >> high registers the GCC hard register number was same as the DWARF register >> number (1200 onwards), hence we didn't see this issue. >> >> Removing statement "D" from "sysv4.h" file so as to generate expected >> DWARF register number does work, but will there be any side effects? > > Ah, I had completely forgotten about this issue, sorry ... > > The problem with DBX_REGISTER_NUMBER is actually described in detail here: > https://gcc.gnu.org/ml/gcc-patches/2012-11/msg02136.html > > At the time, we decided to not remove the #undef DBX_REGISTER_NUMBER to > avoid compatibility issues, but use GCC internal numbers in .debug_frame > and .debug_info on Linux (option (3) in the above mail). However, this > was never actually implemented. > > Looking at the current status, there are three groups of rs6000 targets: > > - Some use the DBX_REGISTER_NUMBER definition from rs6000.h: > These are only AIX and Darwin. > > - Some provide their own definition of DBX_REGISTER_NUMBER after the rs6000.h > one was undefined by sysv4.h: > These are FreeBSD, NetBSD, and Lynx. > > - All other targets do not have DBX_REGISTER_NUMBER because it is undefined > by sysv4.h, and therefore using GCC internal register numbers: > These are Linux, rtems, vxworks, and all ELF/EABI targets. > > > The following patch tries to remove the unfortunate confusion about undefining > and redefining DBX_REGISTER_NUMBER, while keeping the behavior on all targets > unchanged with the following two exceptions: > - fix the SPE problem by always translating high register numbers > - implement option (3) above by not replacing CR2 with CR in .debug_frame > on targets that do not use the standard DWARF register numbering > > The way this works is to have a common, simple implementation of > DBX_REGISTER_NUMBER and DWARF2_FRAME_REG_OUT for all targets that just > calls to the rs6000_dbx_register_number routine, passing an extra format > argument that decides whether the register number is to be used for > .debug_info, .debug_frame, or .eh_frame. In order to ensure > rs6000_dbx_register_number always gets a GCC internal number as input, > DWARF_FRAME_REGNUM has to be again defined as identity map. > > All the logic to decide debug register numbers is now contained in that > single place. However, in order to maintain current behavior, we still > have to distinguish between platforms that want to use the standard > DWARF register numbering scheme, and those that use GCC internal numbers. > This is now simply done by having the former provide a new define > RS6000_USE_DWARF_NUMBERING in a target header file. > > Tested on powerpc64le-linux and powerpc64-linux. > > Rohit, could you verify whether this fixes the SPE problem? > > David, does this approach look reasonable to you? This seems like the best solution. Thanks for untangling this. - David ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-10-08 18:09 ` Ulrich Weigand 2014-10-08 18:27 ` David Edelsohn @ 2014-10-08 19:47 ` Maciej W. Rozycki 2014-10-09 12:20 ` rohitarulraj 1 sibling, 1 reply; 28+ messages in thread From: Maciej W. Rozycki @ 2014-10-08 19:47 UTC (permalink / raw) To: Ulrich Weigand Cc: rohitarulraj, Edmar Wienskoski, David Edelsohn, gcc-patches, Alan Modra, Jakub Jelinek Ulrich, > > While emitting the location descriptors of multiple registers (SPE high/low > > part) individually, the GCC hard register number is converted in to DWARF > > register number using "dbx_reg_number" [Statement "A", "B" & "C" below]. > > > But statement "C" macro "DBX_REGISTER_NUMBER" gets undefined by statement > > "D" hence the GCC hard register number gets emitted in the debug info > > instead of DWARF register number. Previously, without this patch for SPE > > high registers the GCC hard register number was same as the DWARF register > > number (1200 onwards), hence we didn't see this issue. > > > > Removing statement "D" from "sysv4.h" file so as to generate expected > > DWARF register number does work, but will there be any side effects? > > Ah, I had completely forgotten about this issue, sorry ... > > The problem with DBX_REGISTER_NUMBER is actually described in detail here: > https://gcc.gnu.org/ml/gcc-patches/2012-11/msg02136.html > > At the time, we decided to not remove the #undef DBX_REGISTER_NUMBER to > avoid compatibility issues, but use GCC internal numbers in .debug_frame > and .debug_info on Linux (option (3) in the above mail). However, this > was never actually implemented. > > Looking at the current status, there are three groups of rs6000 targets: > > - Some use the DBX_REGISTER_NUMBER definition from rs6000.h: > These are only AIX and Darwin. > > - Some provide their own definition of DBX_REGISTER_NUMBER after the rs6000.h > one was undefined by sysv4.h: > These are FreeBSD, NetBSD, and Lynx. > > - All other targets do not have DBX_REGISTER_NUMBER because it is undefined > by sysv4.h, and therefore using GCC internal register numbers: > These are Linux, rtems, vxworks, and all ELF/EABI targets. > > > The following patch tries to remove the unfortunate confusion about undefining > and redefining DBX_REGISTER_NUMBER, while keeping the behavior on all targets > unchanged with the following two exceptions: > - fix the SPE problem by always translating high register numbers > - implement option (3) above by not replacing CR2 with CR in .debug_frame > on targets that do not use the standard DWARF register numbering > > The way this works is to have a common, simple implementation of > DBX_REGISTER_NUMBER and DWARF2_FRAME_REG_OUT for all targets that just > calls to the rs6000_dbx_register_number routine, passing an extra format > argument that decides whether the register number is to be used for > .debug_info, .debug_frame, or .eh_frame. In order to ensure > rs6000_dbx_register_number always gets a GCC internal number as input, > DWARF_FRAME_REGNUM has to be again defined as identity map. > > All the logic to decide debug register numbers is now contained in that > single place. However, in order to maintain current behavior, we still > have to distinguish between platforms that want to use the standard > DWARF register numbering scheme, and those that use GCC internal numbers. > This is now simply done by having the former provide a new define > RS6000_USE_DWARF_NUMBERING in a target header file. > > Tested on powerpc64le-linux and powerpc64-linux. > > Rohit, could you verify whether this fixes the SPE problem? Thanks for your work, I have applied your change to my 4.9 setup, rebuilt the compiler and smoke-tested it with gdb.base/store.exp and my e500v2 multilib only; powerpc-linux-gnu target. Unfortunately your patch hasn't changed anything, the same failures remain. Just to be sure I haven't missed anything I reverted your change and Rohit's one as well, rebuilt the compiler and rerun this testing and this time all failures were gone. So it looks like your fix didn't completely cover the damage Rohit's change caused. :( Maciej ^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-10-08 19:47 ` Maciej W. Rozycki @ 2014-10-09 12:20 ` rohitarulraj 2014-10-09 13:40 ` Ulrich Weigand 0 siblings, 1 reply; 28+ messages in thread From: rohitarulraj @ 2014-10-09 12:20 UTC (permalink / raw) To: Maciej W. Rozycki, Ulrich Weigand Cc: Edmar Wienskoski, David Edelsohn, gcc-patches, Alan Modra, Jakub Jelinek, rohitarulraj > -----Original Message----- > From: Maciej W. Rozycki [mailto:macro@codesourcery.com] > To: Ulrich Weigand > Cc: Dharmakan Rohit-B30502; Wienskoski Edmar-RA8797; David Edelsohn; gcc- > patches@gcc.gnu.org; Alan Modra; Jakub Jelinek > Subject: Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit > ices@dwf_regno [snip] > > > > Rohit, could you verify whether this fixes the SPE problem? > > Thanks for your work, I have applied your change to my 4.9 setup, rebuilt the > compiler and smoke-tested it with gdb.base/store.exp and my e500v2 multilib > only; powerpc-linux-gnu target. Unfortunately your patch hasn't changed > anything, the same failures remain. > > Just to be sure I haven't missed anything I reverted your change and Rohit's > one as well, rebuilt the compiler and rerun this testing and this time all failures > were gone. So it looks like your fix didn't completely cover the damage Rohit's > change caused. :( Ulrich/Maciej, The patch works for me. Tested with GCC v4.9 branch rev 216036 and GCC trunk rev 216027. Regards, Rohit ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-10-09 12:20 ` rohitarulraj @ 2014-10-09 13:40 ` Ulrich Weigand 2014-10-09 15:49 ` Maciej W. Rozycki 0 siblings, 1 reply; 28+ messages in thread From: Ulrich Weigand @ 2014-10-09 13:40 UTC (permalink / raw) To: rohitarulraj Cc: Maciej W. Rozycki, Edmar Wienskoski, David Edelsohn, gcc-patches, Alan Modra, Jakub Jelinek rohitarulraj wrote: > > -----Original Message----- > > From: Maciej W. Rozycki [mailto:macro@codesourcery.com] > > To: Ulrich Weigand > > Cc: Dharmakan Rohit-B30502; Wienskoski Edmar-RA8797; David Edelsohn; gcc- > > patches@gcc.gnu.org; Alan Modra; Jakub Jelinek > > Subject: Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit > > ices@dwf_regno > [snip] > > > > > > Rohit, could you verify whether this fixes the SPE problem? > >=20 > > Thanks for your work, I have applied your change to my 4.9 setup, rebuil= > t the > > compiler and smoke-tested it with gdb.base/store.exp and my e500v2 multil= > ib > > only; powerpc-linux-gnu target. Unfortunately your patch hasn't changed > > anything, the same failures remain. > >=20 > > Just to be sure I haven't missed anything I reverted your change and Roh= > it's > > one as well, rebuilt the compiler and rerun this testing and this time al= > l failures > > were gone. So it looks like your fix didn't completely cover the damage = > Rohit's > > change caused. :( > > Ulrich/Maciej, > > The patch works for me. > Tested with GCC v4.9 branch rev 216036 and GCC trunk rev 216027. Thanks for testing! Can you work with Maciej to find out why he's seeing different results? Bye, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain Ulrich.Weigand@de.ibm.com ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-10-09 13:40 ` Ulrich Weigand @ 2014-10-09 15:49 ` Maciej W. Rozycki 2014-10-11 14:49 ` Maciej W. Rozycki 0 siblings, 1 reply; 28+ messages in thread From: Maciej W. Rozycki @ 2014-10-09 15:49 UTC (permalink / raw) To: Ulrich Weigand Cc: rohitarulraj, Edmar Wienskoski, David Edelsohn, gcc-patches, Alan Modra, Jakub Jelinek On Thu, 9 Oct 2014, Ulrich Weigand wrote: > > The patch works for me. > > Tested with GCC v4.9 branch rev 216036 and GCC trunk rev 216027. > > Thanks for testing! Can you work with Maciej to find out why he's > seeing different results? Seeing Rohit got good results it has struck me that perhaps one of the patches I had previously reverted, to be able to compile GCC in the first place, interfered with this fix -- I backed out all the subsequent patches to test yours and Rohit's by themselves only. And it was actually the case, with this change: 2013-05-21 Christian Bruel <christian.bruel@st.com> * dwarf2out.c (multiple_reg_loc_descriptor): Use dbx_reg_number for spanning registers. LEAF_REG_REMAP is supported only for contiguous registers. Set register size out of the PARALLEL loop. back in place, in addition to your fix, I get an all-passed score for gdb.base/store.exp. So your change looks good and my decision to back out the other patches unfortunate. I'll yet run full e500v2 testing now to double check, and let you know what the results are, within a couple of hours if things work well. Testing with my other multilibs will have to wait a few days as our Power board farm is currently in maintenance and some are offline. Given this situation and that you both already tested some other multilibs I think there is little point in waiting for my full results. If anything pops up there, then it can be addressed later on. Thanks for your effort and sorry about the confusion with testing. Maciej ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-10-09 15:49 ` Maciej W. Rozycki @ 2014-10-11 14:49 ` Maciej W. Rozycki 2014-10-13 13:22 ` Ulrich Weigand 0 siblings, 1 reply; 28+ messages in thread From: Maciej W. Rozycki @ 2014-10-11 14:49 UTC (permalink / raw) To: Ulrich Weigand Cc: rohitarulraj, Edmar Wienskoski, David Edelsohn, gcc-patches, Alan Modra, Jakub Jelinek On Thu, 9 Oct 2014, Maciej W. Rozycki wrote: > Seeing Rohit got good results it has struck me that perhaps one of the > patches I had previously reverted, to be able to compile GCC in the first > place, interfered with this fix -- I backed out all the subsequent patches > to test yours and Rohit's by themselves only. And it was actually the > case, with this change: > > 2013-05-21 Christian Bruel <christian.bruel@st.com> > > * dwarf2out.c (multiple_reg_loc_descriptor): Use dbx_reg_number for > spanning registers. LEAF_REG_REMAP is supported only for contiguous > registers. Set register size out of the PARALLEL loop. > > back in place, in addition to your fix, I get an all-passed score for > gdb.base/store.exp. So your change looks good and my decision to back out > the other patches unfortunate. I'll yet run full e500v2 testing now to > double check, and let you know what the results are, within a couple of > hours if things work well. It took a bit more because I saw some regressions that I wanted to investigate. In the end they turned out intermittent and the failures happen sometimes whether your change is applied or not. So I'm fine with your change, thanks for your work and patience. For the record the failures were: FAIL: gcc.dg/tree-prof/time-profiler-2.c scan-ipa-dump-times profile "Read tp_first_run: 0" 2 FAIL: gcc.dg/tree-prof/time-profiler-2.c scan-ipa-dump-times profile "Read tp_first_run: 2" 1 FAIL: gcc.dg/tree-prof/time-profiler-2.c scan-ipa-dump-times profile "Read tp_first_run: 3" 1 Maciej ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-10-11 14:49 ` Maciej W. Rozycki @ 2014-10-13 13:22 ` Ulrich Weigand 2014-10-13 17:39 ` David Edelsohn 0 siblings, 1 reply; 28+ messages in thread From: Ulrich Weigand @ 2014-10-13 13:22 UTC (permalink / raw) To: Maciej W. Rozycki Cc: rohitarulraj, Edmar Wienskoski, David Edelsohn, gcc-patches, Alan Modra, Jakub Jelinek Maciej W. Rozycki wrote: > On Thu, 9 Oct 2014, Maciej W. Rozycki wrote: > > > Seeing Rohit got good results it has struck me that perhaps one of the > > patches I had previously reverted, to be able to compile GCC in the first > > place, interfered with this fix -- I backed out all the subsequent patches > > to test yours and Rohit's by themselves only. And it was actually the > > case, with this change: > > > > 2013-05-21 Christian Bruel <christian.bruel@st.com> > > > > * dwarf2out.c (multiple_reg_loc_descriptor): Use dbx_reg_number for > > spanning registers. LEAF_REG_REMAP is supported only for contiguous > > registers. Set register size out of the PARALLEL loop. > > > > back in place, in addition to your fix, I get an all-passed score for > > gdb.base/store.exp. So your change looks good and my decision to back out > > the other patches unfortunate. I'll yet run full e500v2 testing now to > > double check, and let you know what the results are, within a couple of > > hours if things work well. > > It took a bit more because I saw some regressions that I wanted to > investigate. In the end they turned out intermittent and the failures > happen sometimes whether your change is applied or not. So I'm fine with > your change, thanks for your work and patience. Thanks for verifying! David, is the patch OK to commit now? Bye, Ulrich -- Dr. Ulrich Weigand GNU/Linux compilers and toolchain Ulrich.Weigand@de.ibm.com ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno 2014-10-13 13:22 ` Ulrich Weigand @ 2014-10-13 17:39 ` David Edelsohn 0 siblings, 0 replies; 28+ messages in thread From: David Edelsohn @ 2014-10-13 17:39 UTC (permalink / raw) To: Ulrich Weigand Cc: Maciej W. Rozycki, rohitarulraj, Edmar Wienskoski, gcc-patches, Alan Modra, Jakub Jelinek On Mon, Oct 13, 2014 at 9:20 AM, Ulrich Weigand <uweigand@de.ibm.com> wrote: > Maciej W. Rozycki wrote: >> On Thu, 9 Oct 2014, Maciej W. Rozycki wrote: >> >> > Seeing Rohit got good results it has struck me that perhaps one of the >> > patches I had previously reverted, to be able to compile GCC in the first >> > place, interfered with this fix -- I backed out all the subsequent patches >> > to test yours and Rohit's by themselves only. And it was actually the >> > case, with this change: >> > >> > 2013-05-21 Christian Bruel <christian.bruel@st.com> >> > >> > * dwarf2out.c (multiple_reg_loc_descriptor): Use dbx_reg_number for >> > spanning registers. LEAF_REG_REMAP is supported only for contiguous >> > registers. Set register size out of the PARALLEL loop. >> > >> > back in place, in addition to your fix, I get an all-passed score for >> > gdb.base/store.exp. So your change looks good and my decision to back out >> > the other patches unfortunate. I'll yet run full e500v2 testing now to >> > double check, and let you know what the results are, within a couple of >> > hours if things work well. >> >> It took a bit more because I saw some regressions that I wanted to >> investigate. In the end they turned out intermittent and the failures >> happen sometimes whether your change is applied or not. So I'm fine with >> your change, thanks for your work and patience. > > Thanks for verifying! > > David, is the patch OK to commit now? Okay with me. Thanks! David ^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2014-10-13 17:30 UTC | newest] Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2014-07-08 2:42 [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices at dwf_regno rohitarulraj 2014-07-22 7:28 ` rohitarulraj 2014-07-24 16:54 ` [RFC: Patch, PR 60102] [4.9/4.10 Regression] powerpc fp-bit ices@dwf_regno Ulrich Weigand 2014-07-31 18:23 ` rohitarulraj 2014-08-01 14:29 ` Ulrich Weigand 2014-08-01 18:04 ` rohitarulraj 2014-08-01 18:10 ` Jakub Jelinek 2014-08-01 18:21 ` rohitarulraj 2014-08-02 1:46 ` David Edelsohn 2014-08-04 10:25 ` Ulrich Weigand 2014-08-04 16:56 ` Edmar 2014-08-05 8:11 ` Jakub Jelinek 2014-08-05 10:44 ` rohitarulraj 2014-08-05 14:47 ` Edmar 2014-09-28 22:23 ` Maciej W. Rozycki 2014-09-29 9:44 ` Ulrich Weigand 2014-09-29 10:24 ` rohitarulraj 2014-09-29 17:26 ` Maciej W. Rozycki 2014-10-06 15:48 ` rohitarulraj 2014-10-08 18:09 ` Ulrich Weigand 2014-10-08 18:27 ` David Edelsohn 2014-10-08 19:47 ` Maciej W. Rozycki 2014-10-09 12:20 ` rohitarulraj 2014-10-09 13:40 ` Ulrich Weigand 2014-10-09 15:49 ` Maciej W. Rozycki 2014-10-11 14:49 ` Maciej W. Rozycki 2014-10-13 13:22 ` Ulrich Weigand 2014-10-13 17:39 ` David Edelsohn
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