From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9147 invoked by alias); 28 Aug 2014 07:07:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 9136 invoked by uid 89); 28 Aug 2014 07:07:02 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-we0-f174.google.com Received: from mail-we0-f174.google.com (HELO mail-we0-f174.google.com) (74.125.82.174) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Thu, 28 Aug 2014 07:07:01 +0000 Received: by mail-we0-f174.google.com with SMTP id u57so308562wes.19 for ; Thu, 28 Aug 2014 00:06:58 -0700 (PDT) X-Received: by 10.194.200.137 with SMTP id js9mr2643809wjc.90.1409209618087; Thu, 28 Aug 2014 00:06:58 -0700 (PDT) Received: from msticlxl57.ims.intel.com (jfdmzpr02-ext.jf.intel.com. [134.134.137.71]) by mx.google.com with ESMTPSA id bt9sm7381209wjc.44.2014.08.28.00.06.54 for (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Aug 2014 00:06:57 -0700 (PDT) Date: Thu, 28 Aug 2014 07:07:00 -0000 From: Kirill Yukhin To: Uros Bizjak Cc: Jakub Jelinek , Richard Henderson , GCC Patches , kirill.yukhin@gmail.com Subject: [PATCH i386 AVX512] [28/n] Add si/di masked interleave. Message-ID: <20140828070537.GA24795@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes X-SW-Source: 2014-08/txt/msg02541.txt.bz2 Hello, This patch adds support for SI/DO masked interleaves. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/sse.md (define_insn "avx2_interleave_highv4di"): Add masking. (define_insn "vec_interleave_highv2di"): Ditto. (define_insn "avx2_interleave_lowv4di"): Ditto. (define_insn "vec_interleave_lowv2di"): Ditto. -- Thanks, K diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index c602eeb..c9931b4 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -7515,18 +7515,18 @@ }) ;; punpcklqdq and punpckhqdq are shorter than shufpd. -(define_insn "avx2_interleave_highv4di" - [(set (match_operand:V4DI 0 "register_operand" "=x") +(define_insn "avx2_interleave_highv4di" + [(set (match_operand:V4DI 0 "register_operand" "=v") (vec_select:V4DI (vec_concat:V8DI - (match_operand:V4DI 1 "register_operand" "x") - (match_operand:V4DI 2 "nonimmediate_operand" "xm")) + (match_operand:V4DI 1 "register_operand" "v") + (match_operand:V4DI 2 "nonimmediate_operand" "vm")) (parallel [(const_int 1) (const_int 5) (const_int 3) (const_int 7)])))] - "TARGET_AVX2" - "vpunpckhqdq\t{%2, %1, %0|%0, %1, %2}" + "TARGET_AVX2 && " + "vpunpckhqdq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "vex") (set_attr "mode" "OI")]) @@ -7547,36 +7547,36 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "vec_interleave_highv2di" - [(set (match_operand:V2DI 0 "register_operand" "=x,x") +(define_insn "vec_interleave_highv2di" + [(set (match_operand:V2DI 0 "register_operand" "=x,v") (vec_select:V2DI (vec_concat:V4DI - (match_operand:V2DI 1 "register_operand" "0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")) + (match_operand:V2DI 1 "register_operand" "0,v") + (match_operand:V2DI 2 "nonimmediate_operand" "xm,vm")) (parallel [(const_int 1) (const_int 3)])))] - "TARGET_SSE2" + "TARGET_SSE2 && " "@ punpckhqdq\t{%2, %0|%0, %2} - vpunpckhqdq\t{%2, %1, %0|%0, %1, %2}" + vpunpckhqdq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") (set_attr "prefix_data16" "1,*") - (set_attr "prefix" "orig,vex") + (set_attr "prefix" "orig,") (set_attr "mode" "TI")]) -(define_insn "avx2_interleave_lowv4di" - [(set (match_operand:V4DI 0 "register_operand" "=x") +(define_insn "avx2_interleave_lowv4di" + [(set (match_operand:V4DI 0 "register_operand" "=v") (vec_select:V4DI (vec_concat:V8DI - (match_operand:V4DI 1 "register_operand" "x") - (match_operand:V4DI 2 "nonimmediate_operand" "xm")) + (match_operand:V4DI 1 "register_operand" "v") + (match_operand:V4DI 2 "nonimmediate_operand" "vm")) (parallel [(const_int 0) (const_int 4) (const_int 2) (const_int 6)])))] - "TARGET_AVX2" - "vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}" + "TARGET_AVX2 && " + "vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "vex") (set_attr "mode" "OI")]) @@ -7597,18 +7597,18 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "vec_interleave_lowv2di" - [(set (match_operand:V2DI 0 "register_operand" "=x,x") +(define_insn "vec_interleave_lowv2di" + [(set (match_operand:V2DI 0 "register_operand" "=x,v") (vec_select:V2DI (vec_concat:V4DI - (match_operand:V2DI 1 "register_operand" "0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")) + (match_operand:V2DI 1 "register_operand" "0,v") + (match_operand:V2DI 2 "nonimmediate_operand" "xm,vm")) (parallel [(const_int 0) (const_int 2)])))] - "TARGET_SSE2" + "TARGET_SSE2 && " "@ punpcklqdq\t{%2, %0|%0, %2} - vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}" + vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sselog") (set_attr "prefix_data16" "1,*")