From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13376 invoked by alias); 1 Sep 2014 11:39:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 13362 invoked by uid 89); 1 Sep 2014 11:39:13 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.0 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 X-HELO: gate.crashing.org Received: from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Mon, 01 Sep 2014 11:39:12 +0000 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id s81Bcpus020797; Mon, 1 Sep 2014 06:38:51 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id s81BcoJ7020796; Mon, 1 Sep 2014 06:38:50 -0500 Date: Mon, 01 Sep 2014 11:39:00 -0000 From: Segher Boessenkool To: "Bin.Cheng" Cc: Jeff Law , Richard Earnshaw , Bin Cheng , "gcc-patches@gcc.gnu.org" Subject: Re: [PATCH PR62151]Fix uninitialized register issue caused by distribute_notes in combine pass Message-ID: <20140901113850.GA15134@gate.crashing.org> References: <000a01cfc1de$cac1c230$60454690$@arm.com> <53FDB440.5030904@arm.com> <5401680D.60907@redhat.com> <20140831121844.GA8949@gate.crashing.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.3i X-IsSubscribed: yes X-SW-Source: 2014-09/txt/msg00035.txt.bz2 On Mon, Sep 01, 2014 at 11:36:07AM +0800, Bin.Cheng wrote: > > In the testcase (and comment in the proposed patch), why is combine > > combining four insns at all? That means it rejected combining just the > > first three. Why did it do that? > It is explicitly reject by below code in can_combine_p. > > if (GET_CODE (PATTERN (i3)) == PARALLEL) > for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) > if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER) > { > /* Don't substitute for a register intended as a clobberable > operand. */ > rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0); > if (rtx_equal_p (reg, dest)) > return 0; > > Since insn i2 in the list of i0/i1/i2 as below contains parallel > clobber of dest_of_insn76/use_of_insn77. > 32: r84:SI=0 > 76: flags:CC=cmp(r84:SI,0x1) > REG_DEAD r84:SI > 77: {r84:SI=-ltu(flags:CC,0);clobber flags:CC;} > REG_DEAD flags:CC > REG_UNUSED flags:CC Archaeology suggests this check is because the clobber might be an earlyclobber. Which seems silly: how can it be a valid insn at all in that case? It seems to me the check can just be removed. That will hide your issue, maybe even solve it (but I doubt it). If not, then combining the four insns (your case that explodes) should not be allowed either (it's just the same, with a register copy tucked on the end). I haven't looked, but a missing can_combine_p call perhaps? Another question is why is r84 set twice in the first place? Segher