From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13800 invoked by alias); 19 Sep 2014 10:59:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 13791 invoked by uid 89); 19 Sep 2014 10:59:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 X-HELO: cam-smtp0.cambridge.arm.com Received: from fw-tnat.cambridge.arm.com (HELO cam-smtp0.cambridge.arm.com) (217.140.96.21) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Fri, 19 Sep 2014 10:59:27 +0000 Received: from arm.com (e106375-lin.cambridge.arm.com [10.1.203.160]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id s8JAxNoJ002428; Fri, 19 Sep 2014 11:59:23 +0100 Date: Fri, 19 Sep 2014 10:59:00 -0000 From: James Greenhalgh To: "gcc-patches@gcc.gnu.org" Cc: Marcus Shawcroft Subject: Re: [AArch64] Tighten predicates on SIMD shift intrinsics Message-ID: <20140919105923.GA14658@arm.com> References: <1410424192-5243-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1410424192-5243-1-git-send-email-james.greenhalgh@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes X-SW-Source: 2014-09/txt/msg01618.txt.bz2 *Ping* Thanks, James On Thu, Sep 11, 2014 at 09:29:52AM +0100, James Greenhalgh wrote: > gcc/ > > 2014-09-11 James Greenhalgh > > * config/aarch64/aarch64-protos.h (aarch64_simd_const_bounds): Change > return type to bool. > * config/aarch64/aarch64-simd.md (aarch64_qshl): Use > new predicates. > (aarch64_shll2_n): Likewise. > (aarch64_shr_n): Likewise. > (aarch64_sra_n: Likewise. > (aarch64_si_n): Likewise. > (aarch64_qshl_n): Likewise. > * config/aarch64/aarch64.c (aarch64_simd_const_bounds): Change > return type to bool; don't print errors. > * config/aarch64/iterators.md (ve_mode): New. > (offsetlr): Remap to infix text for use in new predicates. > * config/aarch64/predicates.md (aarch64_simd_shift_imm_qi): New. > (aarch64_simd_shift_imm_hi): Likewise. > (aarch64_simd_shift_imm_si): Likewise. > (aarch64_simd_shift_imm_di): Likewise. > (aarch64_simd_shift_imm_offset_qi): Likewise. > (aarch64_simd_shift_imm_offset_hi): Likewise. > (aarch64_simd_shift_imm_offset_si): Likewise. > (aarch64_simd_shift_imm_offset_di): Likewise. > (aarch64_simd_shift_imm_bitsize_qi): Likewise. > (aarch64_simd_shift_imm_bitsize_hi): Likewise. > (aarch64_simd_shift_imm_bitsize_si): Likewise. > (aarch64_simd_shift_imm_bitsize_di): Likewise. > > gcc/testsuite/ > > 2014-09-08 James Greenhalgh > > * gcc.target/aarch64/simd/vqshlb_1.c: New. > > diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h > index 35f89ff..9de7af7 100644 > --- a/gcc/config/aarch64/aarch64-protos.h > +++ b/gcc/config/aarch64/aarch64-protos.h > @@ -205,6 +205,7 @@ bool aarch64_regno_ok_for_base_p (int, bool); > bool aarch64_regno_ok_for_index_p (int, bool); > bool aarch64_simd_check_vect_par_cnst_half (rtx op, enum machine_mode mode, > bool high); > +bool aarch64_simd_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); > bool aarch64_simd_imm_scalar_p (rtx x, enum machine_mode mode); > bool aarch64_simd_imm_zero_p (rtx, enum machine_mode); > bool aarch64_simd_scalar_immediate_valid_for_move (rtx, enum machine_mode); > @@ -255,7 +256,6 @@ void aarch64_emit_call_insn (rtx); > /* Initialize builtins for SIMD intrinsics. */ > void init_aarch64_simd_builtins (void); > > -void aarch64_simd_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); > void aarch64_simd_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int); > > /* Emit code to place a AdvSIMD pair result in memory locations (with equal > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > index 6a45e91512ffe1c8c2ecd2b1ba4336baf87f7256..9e688e310027c772cfe5ecd4a158796b143998c5 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -3715,12 +3715,12 @@ (define_insn "aarch64_qshl > (define_insn "aarch64_shll_n" > [(set (match_operand: 0 "register_operand" "=w") > (unspec: [(match_operand:VDW 1 "register_operand" "w") > - (match_operand:SI 2 "immediate_operand" "i")] > + (match_operand:SI 2 > + "aarch64_simd_shift_imm_bitsize_" "i")] > VSHLL))] > "TARGET_SIMD" > "* > int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; > - aarch64_simd_const_bounds (operands[2], 0, bit_width + 1); > if (INTVAL (operands[2]) == bit_width) > { > return \"shll\\t%0., %1., %2\"; > @@ -3741,7 +3741,6 @@ (define_insn "aarch64_shll2_n > "TARGET_SIMD" > "* > int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; > - aarch64_simd_const_bounds (operands[2], 0, bit_width + 1); > if (INTVAL (operands[2]) == bit_width) > { > return \"shll2\\t%0., %1., %2\"; > @@ -3757,13 +3756,11 @@ (define_insn "aarch64_shll2_n > (define_insn "aarch64_shr_n" > [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w") > (unspec:VSDQ_I_DI [(match_operand:VSDQ_I_DI 1 "register_operand" "w") > - (match_operand:SI 2 "immediate_operand" "i")] > + (match_operand:SI 2 > + "aarch64_simd_shift_imm_offset_" "i")] > VRSHR_N))] > "TARGET_SIMD" > - "* > - int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; > - aarch64_simd_const_bounds (operands[2], 1, bit_width + 1); > - return \"shr\\t%0, %1, %2\";" > + "shr\\t%0, %1, %2" > [(set_attr "type" "neon_sat_shift_imm")] > ) > > @@ -3773,13 +3770,11 @@ (define_insn "aarch64_sra_n" > [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w") > (unspec:VSDQ_I_DI [(match_operand:VSDQ_I_DI 1 "register_operand" "0") > (match_operand:VSDQ_I_DI 2 "register_operand" "w") > - (match_operand:SI 3 "immediate_operand" "i")] > + (match_operand:SI 3 > + "aarch64_simd_shift_imm_offset_" "i")] > VSRA))] > "TARGET_SIMD" > - "* > - int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; > - aarch64_simd_const_bounds (operands[3], 1, bit_width + 1); > - return \"sra\\t%0, %2, %3\";" > + "sra\\t%0, %2, %3" > [(set_attr "type" "neon_shift_acc")] > ) > > @@ -3789,14 +3784,11 @@ (define_insn "aarch64_si_n [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w") > (unspec:VSDQ_I_DI [(match_operand:VSDQ_I_DI 1 "register_operand" "0") > (match_operand:VSDQ_I_DI 2 "register_operand" "w") > - (match_operand:SI 3 "immediate_operand" "i")] > + (match_operand:SI 3 > + "aarch64_simd_shift_imm_" "i")] > VSLRI))] > "TARGET_SIMD" > - "* > - int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; > - aarch64_simd_const_bounds (operands[3], 1 - , > - bit_width - + 1); > - return \"si\\t%0, %2, %3\";" > + "si\\t%0, %2, %3" > [(set_attr "type" "neon_shift_imm")] > ) > > @@ -3805,13 +3797,11 @@ (define_insn "aarch64_si_n (define_insn "aarch64_qshl_n" > [(set (match_operand:VSDQ_I 0 "register_operand" "=w") > (unspec:VSDQ_I [(match_operand:VSDQ_I 1 "register_operand" "w") > - (match_operand:SI 2 "immediate_operand" "i")] > + (match_operand:SI 2 > + "aarch64_simd_shift_imm_" "i")] > VQSHL_N))] > "TARGET_SIMD" > - "* > - int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; > - aarch64_simd_const_bounds (operands[2], 0, bit_width); > - return \"qshl\\t%0, %1, %2\";" > + "qshl\\t%0, %1, %2" > [(set_attr "type" "neon_sat_shift_imm")] > ) > > @@ -3821,13 +3811,11 @@ (define_insn "aarch64_qshl_n (define_insn "aarch64_qshrn_n" > [(set (match_operand: 0 "register_operand" "=w") > (unspec: [(match_operand:VSQN_HSDI 1 "register_operand" "w") > - (match_operand:SI 2 "immediate_operand" "i")] > + (match_operand:SI 2 > + "aarch64_simd_shift_imm_offset_" "i")] > VQSHRN_N))] > "TARGET_SIMD" > - "* > - int bit_width = GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; > - aarch64_simd_const_bounds (operands[2], 1, bit_width + 1); > - return \"qshrn\\t%0, %1, %2\";" > + "qshrn\\t%0, %1, %2" > [(set_attr "type" "neon_sat_shift_imm_narrow_q")] > ) > > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c > index e020bd3..b87db36 100644 > --- a/gcc/config/aarch64/aarch64.c > +++ b/gcc/config/aarch64/aarch64.c > @@ -7931,14 +7931,13 @@ aarch64_simd_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) > error ("lane out of range"); > } > > -void > +bool > aarch64_simd_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) > { > gcc_assert (CONST_INT_P (operand)); > - HOST_WIDE_INT lane = INTVAL (operand); > + HOST_WIDE_INT constant = INTVAL (operand); > > - if (lane < low || lane >= high) > - error ("constant out of range"); > + return (constant >= low && constant <= high); > } > > /* Emit code to reinterpret one AdvSIMD type as another, > diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md > index a00283a04b3c916422ea65c5260e39db63d1a4b3..79f3ba58c28638924294c630ee86379cb1352053 100644 > --- a/gcc/config/aarch64/iterators.md > +++ b/gcc/config/aarch64/iterators.md > @@ -538,6 +538,14 @@ (define_mode_attr v_cmp_result [(V8QI "v > (V2DF "v2di") (DF "di") > (SF "si")]) > > +;; Lower case element modes (as used in shift immediate patterns). > +(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi") > + (V4HI "hi") (V8HI "hi") > + (V2SI "si") (V4SI "si") > + (DI "di") (V2DI "di") > + (QI "qi") (HI "hi") > + (SI "si")]) > + > ;; Vm for lane instructions is restricted to FP_LO_REGS. > (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") > (V2SI "w") (V4SI "w") (SI "w")]) > @@ -1007,8 +1015,9 @@ (define_int_attr addsub [(UNSPEC_SHADD " > (UNSPEC_RADDHN2 "add") > (UNSPEC_RSUBHN2 "sub")]) > > -(define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1") > - (UNSPEC_SSRI "0") (UNSPEC_USRI "0")]) > +(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "") > + (UNSPEC_SSRI "offset_") > + (UNSPEC_USRI "offset_")]) > > ;; Standard pattern names for floating-point rounding instructions. > (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc") > diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md > index 8191169e89b1eaf04c00ea709af70412d2cee361..3b65b5e03f3e762d62bb7b2d59e9a05dad34162b 100644 > --- a/gcc/config/aarch64/predicates.md > +++ b/gcc/config/aarch64/predicates.md > @@ -279,3 +279,56 @@ (define_special_predicate "aarch64_simd_ > { > return aarch64_const_vec_all_same_int_p (op, -1); > }) > + > +;; Predicates used by the various SIMD shift operations. These > +;; fall in to 3 categories. > +;; Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm) > +;; Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset) > +;; Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize) > +(define_predicate "aarch64_simd_shift_imm_qi" > + (and (match_code "const_int") > + (match_test "aarch64_simd_const_bounds (op, 0, 7)"))) > + > +(define_predicate "aarch64_simd_shift_imm_hi" > + (and (match_code "const_int") > + (match_test "aarch64_simd_const_bounds (op, 0, 15)"))) > + > +(define_predicate "aarch64_simd_shift_imm_si" > + (and (match_code "const_int") > + (match_test "aarch64_simd_const_bounds (op, 0, 31)"))) > + > +(define_predicate "aarch64_simd_shift_imm_di" > + (and (match_code "const_int") > + (match_test "aarch64_simd_const_bounds (op, 0, 63)"))) > + > +(define_predicate "aarch64_simd_shift_imm_offset_qi" > + (and (match_code "const_int") > + (match_test "aarch64_simd_const_bounds (op, 1, 8)"))) > + > +(define_predicate "aarch64_simd_shift_imm_offset_hi" > + (and (match_code "const_int") > + (match_test "aarch64_simd_const_bounds (op, 1, 16)"))) > + > +(define_predicate "aarch64_simd_shift_imm_offset_si" > + (and (match_code "const_int") > + (match_test "aarch64_simd_const_bounds (op, 1, 32)"))) > + > +(define_predicate "aarch64_simd_shift_imm_offset_di" > + (and (match_code "const_int") > + (match_test "aarch64_simd_const_bounds (op, 1, 64)"))) > + > +(define_predicate "aarch64_simd_shift_imm_bitsize_qi" > + (and (match_code "const_int") > + (match_test "aarch64_simd_const_bounds (op, 0, 8)"))) > + > +(define_predicate "aarch64_simd_shift_imm_bitsize_hi" > + (and (match_code "const_int") > + (match_test "aarch64_simd_const_bounds (op, 0, 16)"))) > + > +(define_predicate "aarch64_simd_shift_imm_bitsize_si" > + (and (match_code "const_int") > + (match_test "aarch64_simd_const_bounds (op, 0, 32)"))) > + > +(define_predicate "aarch64_simd_shift_imm_bitsize_di" > + (and (match_code "const_int") > + (match_test "aarch64_simd_const_bounds (op, 0, 64)"))) > diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqshlb_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vqshlb_1.c > new file mode 100644 > index 0000000..ae741de > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqshlb_1.c > @@ -0,0 +1,21 @@ > +/* { dg-do run } */ > +/* { dg-options "-O3" } */ > + > +#include "arm_neon.h" > + > +extern void abort (); > + > +int > +main (int argc, char **argv) > +{ > + int8_t arg1 = -1; > + int8_t arg2 = 127; > + int8_t exp = -128; > + int8_t got = vqshlb_s8 (arg1, arg2); > + > + if (exp != got) > + abort (); > + > + return 0; > +} > +