* [PATCH i386 AVX512] [81/n] Add new built-ins.
@ 2014-10-20 13:50 Kirill Yukhin
2014-10-20 13:56 ` Jakub Jelinek
2014-10-23 12:58 ` [PATCH i386 AVX512] [81.2/n] " Kirill Yukhin
0 siblings, 2 replies; 16+ messages in thread
From: Kirill Yukhin @ 2014-10-20 13:50 UTC (permalink / raw)
To: Uros Bizjak; +Cc: Jakub Jelinek, Richard Henderson, GCC Patches, kirill.yukhin
Hello,
This patch adds (almost) all built-ins needed by
AVX-512VL,BW,DQ intrinsics.
Main questionable hunk is:
diff --git a/gcc/tree-core.h b/gcc/tree-core.h
index b69312b..a639487 100644
--- a/gcc/tree-core.h
+++ b/gcc/tree-core.h
@@ -1539,7 +1539,7 @@ struct GTY(()) tree_function_decl {
DECL_FUNCTION_CODE. Otherwise unused.
??? The bitfield needs to be able to hold all target function
codes as well. */
- ENUM_BITFIELD(built_in_function) function_code : 11;
+ ENUM_BITFIELD(built_in_function) function_code : 12;
ENUM_BITFIELD(built_in_class) built_in_class : 2;
unsigned static_ctor_flag : 1;
It may significantly increase compile time memory consumpsion.
There's a hack: e.g. to move a fields to some struct where
free space is still available.
Bootstrapped.
AVX-512* tests on top of patch-set all pass
under simulator.
Is it ok for trunk?
gcc/
2014-09-17 Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/i386/i386-builtin-types.def
(SHORT): New.
(V32HI): Ditto.
(V12QI): Ditto.
(V14QI): Ditto.
(V32SI): Ditto.
(V8UDI): Ditto.
(V16USI): Ditto.
(V32UHI): Ditto.
(PSHORT): Ditto.
(PV32QI): Ditto.
(PV32HI): Ditto.
(PV64QI): Ditto.
(PCV8HI): Ditto.
(PCV16QI): Ditto.
(PCV16HI): Ditto.
(PCV32QI): Ditto.
(PCV32HI): Ditto.
(PCV64QI): Ditto.
(V4SF_FTYPE_V2DF_V4SF_QI): Ditto.
(V4SF_FTYPE_V4DF_V4SF_QI): Ditto.
(V4SF_FTYPE_V8HI_V4SF_QI): Ditto.
(V8SF_FTYPE_V8HI_V8SF_QI): Ditto.
(V16SF_FTYPE_V16HI): Ditto.
(V16SF_FTYPE_V16HI_V16SF_HI): Ditto.
(V16SF_FTYPE_V16SI): Ditto.
(V4DI_FTYPE_V4DI): Ditto.
(V16SI_FTYPE_V16SF): Ditto.
(V8DI_FTYPE_PV2DI): Ditto.
(V8DF_FTYPE_PV2DF): Ditto.
(V4DI_FTYPE_PV2DI): Ditto.
(V4DF_FTYPE_PV2DF): Ditto.
(V16SI_FTYPE_PV2SI): Ditto.
(V16SF_FTYPE_PV2SF): Ditto.
(V8SF_FTYPE_FLOAT): Ditto.
(V4SF_FTYPE_FLOAT): Ditto.
(V4DF_FTYPE_DOUBLE): Ditto.
(V8SF_FTYPE_PV4SF): Ditto.
(V8SI_FTYPE_PV4SI): Ditto.
(V4SI_FTYPE_PV2SI): Ditto.
(V8SF_FTYPE_PV2SF): Ditto.
(V8SI_FTYPE_PV2SI): Ditto.
(V16SF_FTYPE_PV8SF): Ditto.
(V16SI_FTYPE_PV8SI): Ditto.
(V8DI_FTYPE_V8SF): Ditto.
(V4DI_FTYPE_V4SF): Ditto.
(V2DI_FTYPE_V4SF): Ditto.
(V64QI_FTYPE_QI): Ditto.
(V32HI_FTYPE_HI): Ditto.
(V16UHI_FTYPE_V16UHI): Ditto.
(V32UHI_FTYPE_V32UHI): Ditto.
(V2UDI_FTYPE_V2UDI): Ditto.
(V4UDI_FTYPE_V4UDI): Ditto.
(V8UDI_FTYPE_V8UDI): Ditto.
(V4USI_FTYPE_V4USI): Ditto.
(V16USI_FTYPE_V16USI): Ditto.
(V2DF_FTYPE_V4DF_INT_V2DF_QI): Ditto.
(V2DF_FTYPE_V8DF_INT): Ditto.
(V2DF_FTYPE_V8DF_INT_V2DF_QI): Ditto.
(V2DI_FTYPE_V2DI_INT_V2DI_QI): Ditto.
(V8DF_FTYPE_V8DF_INT): Ditto.
(V4SF_FTYPE_V8SF_INT_V4SF_QI): Ditto.
(V4SI_FTYPE_V2DF_V4SI_QI): Ditto.
(V4SI_FTYPE_V4SI_INT_V4SI_QI): Ditto.
(V4SI_FTYPE_V8HI_V8HI_V4SI_QI): Ditto.
(V4SI_FTYPE_V8SI_INT_V4SI_QI): Ditto.
(V8HI_FTYPE_V16QI_V16QI_V8HI_QI): Ditto.
(V8DI_FTYPE_V8DI_INT): Ditto.
(V8HI_FTYPE_V8SF_INT_V8HI_QI): Ditto.
(V8HI_FTYPE_V4SF_INT_V8HI_QI): Ditto.
(V8SF_FTYPE_V16SF_INT): Ditto.
(V8SF_FTYPE_V16SF_INT_V8SF_QI): Ditto.
(V64QI_FTYPE_V32HI_V32HI): Ditto.
(V32HI_FTYPE_V16SI_V16SI): Ditto.
(V8DF_FTYPE_V8DF_V2DF_INT): Ditto.
(V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI): Ditto.
(V8DF_FTYPE_V8DF_V8DF_INT): Ditto.
(V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT): Ditto.
(V8DF_FTYPE_V8DF_V8DF_V8DI_INT): Ditto.
(V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI): Ditto.
(V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI): Ditto.
(V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI): Ditto.
(V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT): Ditto.
(V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI): Ditto.
(V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI): Ditto.
(V32HI_FTYPE_V64QI_V64QI): Ditto.
(V16HI_FTYPE_V32QI_V32QI_V16HI_HI): Ditto.
(V32HI_FTYPE_V64QI_V64QI_V32HI_SI): Ditto.
(V32HI_FTYPE_V32HI_V32HI): Ditto.
(V32HI_FTYPE_V32HI_INT): Ditto.
(V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI): Ditto.
(V16SI_FTYPE_V32HI_V32HI): Ditto.
(V8SI_FTYPE_V16HI_V16HI_V8SI_QI): Ditto.
(V16SI_FTYPE_V32HI_V32HI_V16SI_HI): Ditto.
(V8SI_FTYPE_V8SI_INT_V8SI_QI): Ditto.
(V8SI_FTYPE_V16SI_INT): Ditto.
(V8SI_FTYPE_V16SI_INT_V8SI_QI): Ditto.
(V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI): Ditto.
(V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI): Ditto.
(V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI): Ditto.
(V8DI_FTYPE_V8DI_V4DI_INT): Ditto.
(V8DI_FTYPE_V8DI_V2DI_INT): Ditto.
(V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI): Ditto.
(V8DI_FTYPE_V16SI_V16SI): Ditto.
(V8DI_FTYPE_V64QI_V64QI): Ditto.
(V4DI_FTYPE_V4DI_INT_V4DI_QI): Ditto.
(V2DI_FTYPE_V4DI_INT_V2DI_QI): Ditto.
(V2DI_FTYPE_V8DI_INT): Ditto.
(V2DI_FTYPE_V8DI_INT_V2DI_QI): Ditto.
(QI_FTYPE_QI): Ditto.
(SI_FTYPE_SI): Ditto.
(DI_FTYPE_DI): Ditto.
(HI_FTYPE_V16QI): Ditto.
(SI_FTYPE_V32QI): Ditto.
(DI_FTYPE_V64QI): Ditto.
(QI_FTYPE_V8HI): Ditto.
(HI_FTYPE_V16HI): Ditto.
(SI_FTYPE_V32HI): Ditto.
(QI_FTYPE_V4SI): Ditto.
(QI_FTYPE_V8SI): Ditto.
(HI_FTYPE_V16SI): Ditto.
(QI_FTYPE_V2DI): Ditto.
(QI_FTYPE_V4DI): Ditto.
(QI_FTYPE_V8DI): Ditto.
(V16QI_FTYPE_HI): Ditto.
(V32QI_FTYPE_SI): Ditto.
(V64QI_FTYPE_DI): Ditto.
(V8HI_FTYPE_QI): Ditto.
(V16HI_FTYPE_HI): Ditto.
(V32HI_FTYPE_SI): Ditto.
(V4SI_FTYPE_QI): Ditto.
(V4SI_FTYPE_HI): Ditto.
(V8SI_FTYPE_QI): Ditto.
(V8SI_FTYPE_HI): Ditto.
(V2DI_FTYPE_QI): Ditto.
(V4DI_FTYPE_QI): Ditto.
(QI_FTYPE_QI_QI): Ditto.
(SI_FTYPE_SI_SI): Ditto.
(DI_FTYPE_DI_DI): Ditto.
(QI_FTYPE_QI_INT): Ditto.
(SI_FTYPE_SI_INT): Ditto.
(DI_FTYPE_DI_INT): Ditto.
(HI_FTYPE_V16QI_V16QI): Ditto.
(HI_FTYPE_V16QI_V16QI_HI): Ditto.
(HI_FTYPE_V16QI_V16QI_INT_HI): Ditto.
(SI_FTYPE_V32QI_V32QI): Ditto.
(SI_FTYPE_V32QI_V32QI_SI): Ditto.
(SI_FTYPE_V32QI_V32QI_INT_SI): Ditto.
(DI_FTYPE_V64QI_V64QI): Ditto.
(DI_FTYPE_V64QI_V64QI_DI): Ditto.
(DI_FTYPE_V64QI_V64QI_INT_DI): Ditto.
(QI_FTYPE_V8HI_V8HI): Ditto.
(QI_FTYPE_V8HI_V8HI_QI): Ditto.
(QI_FTYPE_V8HI_V8HI_INT_QI): Ditto.
(HI_FTYPE_V16HI_V16HI): Ditto.
(HI_FTYPE_V16HI_V16HI_HI): Ditto.
(HI_FTYPE_V16HI_V16HI_INT_HI): Ditto.
(SI_FTYPE_V32HI_V32HI): Ditto.
(SI_FTYPE_V32HI_V32HI_SI): Ditto.
(SI_FTYPE_V32HI_V32HI_INT_SI): Ditto.
(QI_FTYPE_V4SI_V4SI): Ditto.
(QI_FTYPE_V4SI_V4SI_QI): Ditto.
(QI_FTYPE_V4SI_V4SI_INT_QI): Ditto.
(QI_FTYPE_V8SI_V8SI): Ditto.
(QI_FTYPE_V8SI_V8SI_QI): Ditto.
(QI_FTYPE_V8SI_V8SI_INT_QI): Ditto.
(QI_FTYPE_V2DI_V2DI): Ditto.
(QI_FTYPE_V2DI_V2DI_QI): Ditto.
(QI_FTYPE_V2DI_V2DI_INT_QI): Ditto.
(QI_FTYPE_V4DI_V4DI): Ditto.
(QI_FTYPE_V4DI_V4DI_QI): Ditto.
(QI_FTYPE_V4DI_V4DI_INT_QI): Ditto.
(V32HI_FTYPE_V32HI_V32HI_V32HI): Ditto.
(V4DF_FTYPE_V4DF_V4DI_INT): Ditto.
(V2DF_FTYPE_V2DI_V2DF_V2DF_QI): Ditto.
(V2DF_FTYPE_V2DF_V2DI_V2DF_QI): Ditto.
(V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI): Ditto.
(V8DI_FTYPE_V8DI_V8DI_INT): Ditto.
(V4SF_FTYPE_V4SI_V4SF_V4SF_QI): Ditto.
(V4SF_FTYPE_V4SF_V4SI_V4SF_QI): Ditto.
(V4SF_FTYPE_V4SF_V4SF_V4SF_QI): Ditto.
(V4SF_FTYPE_V4SF_V2DF_V4SF_QI): Ditto.
(V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI): Ditto.
(V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI): Ditto.
(V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI): Ditto.
(V2DF_FTYPE_V2DF_V2DF_QI): Ditto.
(V2DF_FTYPE_V4SF_V2DF_QI): Ditto.
(V2DF_FTYPE_V4SI_V2DF_QI): Ditto.
(V4DF_FTYPE_V4DF_V4DF_QI): Ditto.
(V4DF_FTYPE_V4SF_V4DF_QI): Ditto.
(V4DF_FTYPE_V4SI_V4DF_QI): Ditto.
(V2DI_FTYPE_V4SI_V2DI_QI): Ditto.
(V2DI_FTYPE_V8HI_V2DI_QI): Ditto.
(V8DI_FTYPE_V8DF_V8DI_QI): Ditto.
(V4DI_FTYPE_V4DF_V4DI_QI): Ditto.
(V2DI_FTYPE_V2DF_V2DI_QI): Ditto.
(V2DI_FTYPE_V2DI_V2DI_V2DI_QI): Ditto.
(V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI): Ditto.
(V4DI_FTYPE_V4DI_V4DI_V4DI_QI): Ditto.
(V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI): Ditto.
(V2DI_FTYPE_V16QI_V2DI_QI): Ditto.
(V4DI_FTYPE_V16QI_V4DI_QI): Ditto.
(V4DI_FTYPE_V4DI_V4DI_QI): Ditto.
(V4DI_FTYPE_V4SI_V4DI_QI): Ditto.
(V4DI_FTYPE_V8HI_V4DI_QI): Ditto.
(V4DF_FTYPE_V4DI_V4DF_V4DF_QI): Ditto.
(V4DF_FTYPE_V4DF_V4DI_V4DF_QI): Ditto.
(V4DF_FTYPE_V4DF_V4DF_V4DF_QI): Ditto.
(V16QI_FTYPE_V16QI_V16QI_V16QI_HI): Ditto.
(V16HI_FTYPE_V16HI_V16HI_V16HI_HI): Ditto.
(V32HI_FTYPE_V32HI_V32HI_V32HI_SI): Ditto.
(V64QI_FTYPE_V64QI_V64QI_V64QI_DI): Ditto.
(V32QI_FTYPE_V32QI_V32QI_V32QI_SI): Ditto.
(V8HI_FTYPE_V8HI_V8HI_V8HI_QI): Ditto.
(V4SF_FTYPE_V4SF_V4SF_QI): Ditto.
(V4SF_FTYPE_V4SI_V4SF_QI): Ditto.
(V8SF_FTYPE_V8SF_V8SF_QI): Ditto.
(V8SF_FTYPE_V8SI_V8SF_QI): Ditto.
(V4SI_FTYPE_V16QI_V4SI_QI): Ditto.
(V4SI_FTYPE_V8HI_V4SI_QI): Ditto.
(V8SI_FTYPE_V8SI_V8SI_QI): Ditto.
(V8SI_FTYPE_V8HI_V8SI_QI): Ditto.
(V8SI_FTYPE_V16QI_V8SI_QI): Ditto.
(V4SI_FTYPE_V4SI_V4SI_V4SI_QI): Ditto.
(V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI): Ditto.
(V8SF_FTYPE_V8SF_V8SF_V8SF_QI): Ditto.
(V8SF_FTYPE_V8SI_V8SF_V8SF_QI): Ditto.
(V8SF_FTYPE_V8SF_V8SI_V8SF_QI): Ditto.
(V8SI_FTYPE_V8SI_V8SI_V8SI_QI): Ditto.
(V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI): Ditto.
(V16SF_FTYPE_V8SF_V16SF_HI): Ditto.
(V16SI_FTYPE_V8SI_V16SI_HI): Ditto.
(V4SI_FTYPE_V4DF_V4SI_QI): Ditto.
(V8DI_FTYPE_PCCHAR_V8DI_QI): Ditto.
(V8SF_FTYPE_PCFLOAT_V8SF_QI): Ditto.
(V4SF_FTYPE_PCFLOAT_V4SF_QI): Ditto.
(V4DF_FTYPE_PCDOUBLE_V4DF_QI): Ditto.
(V2DF_FTYPE_PCDOUBLE_V2DF_QI): Ditto.
(V8SI_FTYPE_PCCHAR_V8SI_QI): Ditto.
(V4SI_FTYPE_PCCHAR_V4SI_QI): Ditto.
(V4DI_FTYPE_PCCHAR_V4DI_QI): Ditto.
(V2DI_FTYPE_PCCHAR_V2DI_QI): Ditto.
(V16QI_FTYPE_V16SI_V16QI_HI): Ditto.
(V16QI_FTYPE_V8DI_V16QI_QI): Ditto.
(V32HI_FTYPE_V32HI_V32HI_SI): Ditto.
(V32HI_FTYPE_V64QI_V64QI_INT): Ditto.
(V32HI_FTYPE_V32QI_V32HI_SI): Ditto.
(V16HI_FTYPE_V16HI_V16HI_HI): Ditto.
(V16HI_FTYPE_V32QI_V32QI_INT): Ditto.
(V16HI_FTYPE_V16QI_V16HI_HI): Ditto.
(V8HI_FTYPE_V16QI_V8HI_QI): Ditto.
(V8HI_FTYPE_V16QI_V16QI_INT): Ditto.
(V8SF_FTYPE_V4SF_V8SF_QI): Ditto.
(V4DF_FTYPE_V2DF_V4DF_QI): Ditto.
(V8SI_FTYPE_V4SI_V8SI_QI): Ditto.
(V8SI_FTYPE_SI_V8SI_QI): Ditto.
(V4SI_FTYPE_V4SI_V4SI_QI): Ditto.
(V4SI_FTYPE_SI_V4SI_QI): Ditto.
(V4DI_FTYPE_V2DI_V4DI_QI): Ditto.
(V4DI_FTYPE_DI_V4DI_QI): Ditto.
(V2DI_FTYPE_V2DI_V2DI_QI): Ditto.
(V2DI_FTYPE_DI_V2DI_QI): Ditto.
(V64QI_FTYPE_V64QI_V64QI_DI): Ditto.
(V64QI_FTYPE_V16QI_V64QI_DI): Ditto.
(V64QI_FTYPE_QI_V64QI_DI): Ditto.
(V32QI_FTYPE_V32QI_V32QI_SI): Ditto.
(V32QI_FTYPE_V16QI_V32QI_SI): Ditto.
(V32QI_FTYPE_QI_V32QI_SI): Ditto.
(V16QI_FTYPE_V16QI_V16QI_HI): Ditto.
(V16QI_FTYPE_QI_V16QI_HI): Ditto.
(V32HI_FTYPE_V8HI_V32HI_SI): Ditto.
(V32HI_FTYPE_HI_V32HI_SI): Ditto.
(V16HI_FTYPE_V8HI_V16HI_HI): Ditto.
(V16HI_FTYPE_HI_V16HI_HI): Ditto.
(V8HI_FTYPE_V8HI_V8HI_QI): Ditto.
(V8HI_FTYPE_HI_V8HI_QI): Ditto.
(V64QI_FTYPE_PCV64QI_V64QI_DI): Ditto.
(V32HI_FTYPE_PCV32HI_V32HI_SI): Ditto.
(V32QI_FTYPE_PCV32QI_V32QI_SI): Ditto.
(V16SF_FTYPE_PCV8SF_V16SF_HI): Ditto.
(V16SI_FTYPE_PCV8SI_V16SI_HI): Ditto.
(V16HI_FTYPE_PCV16HI_V16HI_HI): Ditto.
(V16QI_FTYPE_PCV16QI_V16QI_HI): Ditto.
(V8DF_FTYPE_PCV2DF_V8DF_QI): Ditto.
(V8SF_FTYPE_PCV8SF_V8SF_QI): Ditto.
(V8SF_FTYPE_PCV4SF_V8SF_QI): Ditto.
(V8DI_FTYPE_PCV2DI_V8DI_QI): Ditto.
(V8SI_FTYPE_PCV8SI_V8SI_QI): Ditto.
(V8SI_FTYPE_PCV4SI_V8SI_QI): Ditto.
(V8HI_FTYPE_PCV8HI_V8HI_QI): Ditto.
(V4DF_FTYPE_PCV2DF_V4DF_QI): Ditto.
(V4DF_FTYPE_PCV4DF_V4DF_QI): Ditto.
(V4SF_FTYPE_PCV4SF_V4SF_QI): Ditto.
(V4DI_FTYPE_PCV4DI_V4DI_QI): Ditto.
(V4DI_FTYPE_PCV2DI_V4DI_QI): Ditto.
(V4SI_FTYPE_PCV4SI_V4SI_QI): Ditto.
(V2DF_FTYPE_PCV2DF_V2DF_QI): Ditto.
(V2DI_FTYPE_PCV2DI_V2DI_QI): Ditto.
(V16QI_FTYPE_V8HI_V16QI_QI): Ditto.
(V16QI_FTYPE_V16HI_V16QI_HI): Ditto.
(V16QI_FTYPE_V4SI_V16QI_QI): Ditto.
(V16QI_FTYPE_V8SI_V16QI_QI): Ditto.
(V8HI_FTYPE_V4SI_V8HI_QI): Ditto.
(V8HI_FTYPE_V8SI_V8HI_QI): Ditto.
(V16QI_FTYPE_V2DI_V16QI_QI): Ditto.
(V16QI_FTYPE_V4DI_V16QI_QI): Ditto.
(V8HI_FTYPE_V2DI_V8HI_QI): Ditto.
(V8HI_FTYPE_V4DI_V8HI_QI): Ditto.
(V4SI_FTYPE_V2DI_V4SI_QI): Ditto.
(V4SI_FTYPE_V4DI_V4SI_QI): Ditto.
(V32QI_FTYPE_V32HI_V32QI_SI): Ditto.
(V2DF_FTYPE_V2DF_INT_V2DF_QI): Ditto.
(V4DF_FTYPE_V4DF_INT_V4DF_QI): Ditto.
(V4SF_FTYPE_V4SF_INT_V4SF_QI): Ditto.
(V8SF_FTYPE_V8SF_INT_V8SF_QI): Ditto.
(V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI): Ditto.
(V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI): Ditto.
(V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI): Ditto.
(V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI): Ditto.
(VOID_FTYPE_PV8HI_V4DI_QI): Ditto.
(VOID_FTYPE_PV8HI_V2DI_QI): Ditto.
(VOID_FTYPE_PV4SI_V4DI_QI): Ditto.
(VOID_FTYPE_PV4SI_V2DI_QI): Ditto.
(VOID_FTYPE_PV8HI_V8SI_QI): Ditto.
(VOID_FTYPE_PV8HI_V4SI_QI): Ditto.
(VOID_FTYPE_PV4DF_V4DF_QI): Ditto.
(VOID_FTYPE_PV2DF_V2DF_QI): Ditto.
(VOID_FTYPE_PV8SF_V8SF_QI): Ditto.
(VOID_FTYPE_PV4SF_V4SF_QI): Ditto.
(VOID_FTYPE_PV4DI_V4DI_QI): Ditto.
(VOID_FTYPE_PV2DI_V2DI_QI): Ditto.
(VOID_FTYPE_PV16QI_V8SI_QI): Ditto.
(VOID_FTYPE_PV16QI_V4SI_QI): Ditto.
(VOID_FTYPE_PV16QI_V4DI_QI): Ditto.
(VOID_FTYPE_PV16QI_V2DI_QI): Ditto.
(VOID_FTYPE_PV8SI_V8SI_QI): Ditto.
(VOID_FTYPE_PV4SI_V4SI_QI): Ditto.
(VOID_FTYPE_PV32HI_V32HI_SI): Ditto.
(VOID_FTYPE_PV16HI_V16HI_HI): Ditto.
(VOID_FTYPE_PV8HI_V8HI_QI): Ditto.
(VOID_FTYPE_PV64QI_V64QI_DI): Ditto.
(VOID_FTYPE_PV32QI_V32QI_SI): Ditto.
(VOID_FTYPE_PV16QI_V16QI_HI): Ditto.
(V8SI_FTYPE_V8SF_V8SI_QI): Ditto.
(V4SI_FTYPE_V4SF_V4SI_QI): Ditto.
(V8DI_FTYPE_V8SF_V8DI_QI): Ditto.
(V4DI_FTYPE_V4SF_V4DI_QI): Ditto.
(V2DI_FTYPE_V4SF_V2DI_QI): Ditto.
(V8SF_FTYPE_V8DI_V8SF_QI): Ditto.
(V4SF_FTYPE_V4DI_V4SF_QI): Ditto.
(V4SF_FTYPE_V2DI_V4SF_QI): Ditto.
(V8DF_FTYPE_V8DI_V8DF_QI): Ditto.
(V4DF_FTYPE_V4DI_V4DF_QI): Ditto.
(V2DF_FTYPE_V2DI_V2DF_QI): Ditto.
(V32HI_FTYPE_V32HI_INT_V32HI_SI): Ditto.
(V32HI_FTYPE_V32HI_V8HI_V32HI_SI): Ditto.
(V16HI_FTYPE_V16HI_INT_V16HI_HI): Ditto.
(V16HI_FTYPE_V16HI_V8HI_V16HI_HI): Ditto.
(V8HI_FTYPE_V8HI_INT_V8HI_QI): Ditto.
(V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI): Ditto.
(V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI): Ditto.
(V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI): Ditto.
(V64QI_FTYPE_V32HI_V32HI_V64QI_DI): Ditto.
(V32QI_FTYPE_V16HI_V16HI_V32QI_SI): Ditto.
(V16QI_FTYPE_V8HI_V8HI_V16QI_HI): Ditto.
(V32HI_FTYPE_V16SI_V16SI_V32HI_SI): Ditto.
(V16HI_FTYPE_V8SI_V8SI_V16HI_HI): Ditto.
(V8HI_FTYPE_V4SI_V4SI_V8HI_QI): Ditto.
(V8DI_FTYPE_V16SI_V16SI_V8DI_QI): Ditto.
(V4DI_FTYPE_V8SI_V8SI_V4DI_QI): Ditto.
(V2DI_FTYPE_V4SI_V4SI_V2DI_QI): Ditto.
(V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI): Ditto.
(V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI): Ditto.
(V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI): Ditto.
(V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI): Ditto.
(V2DF_FTYPE_V2DF_V2DI_V2DF): Ditto.
(V4DF_FTYPE_V4DF_V4DI_V4DF): Ditto.
(V4SF_FTYPE_V4SF_V4SI_V4SF): Ditto.
(V8SF_FTYPE_V8SF_V8SI_V8SF): Ditto.
(V8SI_FTYPE_V8SI_V4SI_V8SI_QI): Ditto.
(V4DI_FTYPE_V4DI_V2DI_V4DI_QI): Ditto.
(QI_FTYPE_V8DF_INT): Ditto.
(QI_FTYPE_V4DF_INT): Ditto.
(QI_FTYPE_V4DF_V4DF_INT_QI): Ditto.
(QI_FTYPE_V2DF_INT): Ditto.
(HI_FTYPE_V16SF_INT): Ditto.
(QI_FTYPE_V8SF_INT): Ditto.
(QI_FTYPE_V8SF_V8SF_INT_QI): Ditto.
(QI_FTYPE_V4SF_INT): Ditto.
(QI_FTYPE_V8DF_INT_QI): Ditto.
(QI_FTYPE_V4DF_INT_QI): Ditto.
(QI_FTYPE_V2DF_INT_QI): Ditto.
(HI_FTYPE_V16SF_INT_HI): Ditto.
(QI_FTYPE_V8SF_INT_QI): Ditto.
(QI_FTYPE_V4SF_INT_QI): Ditto.
(V8DI_FTYPE_V8DF_V8DI_QI_INT): Ditto.
(V8DI_FTYPE_V8SF_V8DI_QI_INT): Ditto.
(V8DF_FTYPE_V8DI_V8DF_QI_INT): Ditto.
(V8SF_FTYPE_V8DI_V8SF_QI_INT): Ditto.
(V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT): Ditto.
(V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT): Ditto.
(V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT): Ditto.
(V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT): Ditto.
(V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT): Ditto.
(V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT): Ditto.
(V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT): Ditto.
(V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT): Ditto.
(V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT): Ditto.
(V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT): Ditto.
(V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT): Ditto.
(V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT): Ditto.
(V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT): Ditto.
(V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT): Ditto.
(V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT): Ditto.
(V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT): Ditto.
(V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT): Ditto.
(V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT): Ditto.
(V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT): Ditto.
(V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT): Ditto.
(VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT): Ditto.
(VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT): Ditto.
(VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT): Ditto.
(VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT): Ditto.
(VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT): Ditto.
(VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT): Ditto.
(VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT): Ditto.
(VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT): Ditto.
(VOID_FTYPE_PINT_QI_V8SI_V8SI_INT): Ditto.
(VOID_FTYPE_PINT_QI_V4SI_V4SI_INT): Ditto.
(VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT): Ditto.
(VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT): Ditto.
(VOID_FTYPE_PINT_QI_V4DI_V4SI_INT): Ditto.
(VOID_FTYPE_PINT_QI_V2DI_V4SI_INT): Ditto.
(VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT): Ditto.
(VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT): Ditto.
(V8DI_FTYPE_V8DI_INT): Ditto.
(V8DI_FTYPE_V8DI_V8DI_INT): Ditto.
(V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI): Ditto.
(V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI): Ditto.
(V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI): Ditto.
(V2DF_FTYPE_ V2DF_ V2DF_ V2DI_ INT_ QI): Remove.
(V4SF_FTYPE_ V4SF_ V2DF_ V4SF_ QI): Ditto.
(V4SF_FTYPE_ V4SF_ V4SF_ V4SF_ QI): Ditto.
(V2DF_FTYPE_ PCDOUBLE_ V2DF_ QI): Ditto.
(V4SF_FTYPE_ PCFLOAT_ V4SF_ QI): Ditto.
(V16QI_FTYPE_ V16SI_ V16QI_ HI): Ditto.
(V16QI_FTYPE_ V8DI_ V16QI_ QI): Ditto.
(V4SF_FTYPE_ V4SF_ V4SF_ INT_ V4SF_ QI): Ditto.
(V2DF_FTYPE_ V2DF_ V2DF_ INT_ V2DF_ QI): Ditto.
(V8DI_FTYPE_ V16SI_ V16SI_ V8DI_ QI): Ditto.
* config/i386/i386.c (ix86_builtins):
Add IX86_BUILTIN_PMOVUSQD256_MEM, IX86_BUILTIN_PMOVUSQD128_MEM,
IX86_BUILTIN_PMOVSQD256_MEM, IX86_BUILTIN_PMOVSQD128_MEM,
IX86_BUILTIN_PMOVQD256_MEM, IX86_BUILTIN_PMOVQD128_MEM,
IX86_BUILTIN_PMOVUSQW256_MEM, IX86_BUILTIN_PMOVUSQW128_MEM,
IX86_BUILTIN_PMOVSQW256_MEM, IX86_BUILTIN_PMOVSQW128_MEM,
IX86_BUILTIN_PMOVQW256_MEM, IX86_BUILTIN_PMOVQW128_MEM,
IX86_BUILTIN_PMOVUSQB256_MEM, IX86_BUILTIN_PMOVUSQB128_MEM,
IX86_BUILTIN_PMOVSQB256_MEM, IX86_BUILTIN_PMOVSQB128_MEM,
IX86_BUILTIN_PMOVQB256_MEM, IX86_BUILTIN_PMOVQB128_MEM,
IX86_BUILTIN_PMOVUSDW256_MEM, IX86_BUILTIN_PMOVUSDW128_MEM,
IX86_BUILTIN_PMOVSDW256_MEM, IX86_BUILTIN_PMOVSDW128_MEM,
IX86_BUILTIN_PMOVDW256_MEM, IX86_BUILTIN_PMOVDW128_MEM,
IX86_BUILTIN_PMOVUSDB256_MEM, IX86_BUILTIN_PMOVUSDB128_MEM,
IX86_BUILTIN_PMOVSDB256_MEM, IX86_BUILTIN_PMOVSDB128_MEM,
IX86_BUILTIN_PMOVDB256_MEM, IX86_BUILTIN_PMOVDB128_MEM,
IX86_BUILTIN_MOVDQA64LOAD256_MASK, IX86_BUILTIN_MOVDQA64LOAD128_MASK,
IX86_BUILTIN_MOVDQA32LOAD256_MASK, IX86_BUILTIN_MOVDQA32LOAD128_MASK,
IX86_BUILTIN_MOVDQA64STORE256_MASK, IX86_BUILTIN_MOVDQA64STORE128_MASK,
IX86_BUILTIN_MOVDQA32STORE256_MASK, IX86_BUILTIN_MOVDQA32STORE128_MASK,
IX86_BUILTIN_LOADAPD256_MASK, IX86_BUILTIN_LOADAPD128_MASK,
IX86_BUILTIN_LOADAPS256_MASK, IX86_BUILTIN_LOADAPS128_MASK,
IX86_BUILTIN_STOREAPD256_MASK, IX86_BUILTIN_STOREAPD128_MASK,
IX86_BUILTIN_STOREAPS256_MASK, IX86_BUILTIN_STOREAPS128_MASK,
IX86_BUILTIN_LOADUPD256_MASK, IX86_BUILTIN_LOADUPD128_MASK,
IX86_BUILTIN_LOADUPS256_MASK, IX86_BUILTIN_LOADUPS128_MASK,
IX86_BUILTIN_STOREUPD256_MASK, IX86_BUILTIN_STOREUPD128_MASK,
IX86_BUILTIN_STOREUPS256_MASK, IX86_BUILTIN_STOREUPS128_MASK,
IX86_BUILTIN_LOADDQUDI256_MASK, IX86_BUILTIN_LOADDQUDI128_MASK,
IX86_BUILTIN_LOADDQUSI256_MASK, IX86_BUILTIN_LOADDQUSI128_MASK,
IX86_BUILTIN_LOADDQUHI256_MASK, IX86_BUILTIN_LOADDQUHI128_MASK,
IX86_BUILTIN_LOADDQUQI256_MASK, IX86_BUILTIN_LOADDQUQI128_MASK,
IX86_BUILTIN_STOREDQUDI256_MASK, IX86_BUILTIN_STOREDQUDI128_MASK,
IX86_BUILTIN_STOREDQUSI256_MASK, IX86_BUILTIN_STOREDQUSI128_MASK,
IX86_BUILTIN_STOREDQUHI256_MASK, IX86_BUILTIN_STOREDQUHI128_MASK,
IX86_BUILTIN_STOREDQUQI256_MASK, IX86_BUILTIN_STOREDQUQI128_MASK,
IX86_BUILTIN_COMPRESSPDSTORE256, IX86_BUILTIN_COMPRESSPDSTORE128,
IX86_BUILTIN_COMPRESSPSSTORE256, IX86_BUILTIN_COMPRESSPSSTORE128,
IX86_BUILTIN_PCOMPRESSQSTORE256, IX86_BUILTIN_PCOMPRESSQSTORE128,
IX86_BUILTIN_PCOMPRESSDSTORE256, IX86_BUILTIN_PCOMPRESSDSTORE128,
IX86_BUILTIN_EXPANDPDLOAD256, IX86_BUILTIN_EXPANDPDLOAD128,
IX86_BUILTIN_EXPANDPSLOAD256, IX86_BUILTIN_EXPANDPSLOAD128,
IX86_BUILTIN_PEXPANDQLOAD256, IX86_BUILTIN_PEXPANDQLOAD128,
IX86_BUILTIN_PEXPANDDLOAD256, IX86_BUILTIN_PEXPANDDLOAD128,
IX86_BUILTIN_EXPANDPDLOAD256Z, IX86_BUILTIN_EXPANDPDLOAD128Z,
IX86_BUILTIN_EXPANDPSLOAD256Z, IX86_BUILTIN_EXPANDPSLOAD128Z,
IX86_BUILTIN_PEXPANDQLOAD256Z, IX86_BUILTIN_PEXPANDQLOAD128Z,
IX86_BUILTIN_PEXPANDDLOAD256Z, IX86_BUILTIN_PEXPANDDLOAD128Z,
IX86_BUILTIN_PALIGNR256_MASK, IX86_BUILTIN_PALIGNR128_MASK,
IX86_BUILTIN_MOVDQA64_256_MASK, IX86_BUILTIN_MOVDQA64_128_MASK,
IX86_BUILTIN_MOVDQA32_256_MASK, IX86_BUILTIN_MOVDQA32_128_MASK,
IX86_BUILTIN_MOVAPD256_MASK, IX86_BUILTIN_MOVAPD128_MASK,
IX86_BUILTIN_MOVAPS256_MASK, IX86_BUILTIN_MOVAPS128_MASK,
IX86_BUILTIN_MOVDQUHI256_MASK, IX86_BUILTIN_MOVDQUHI128_MASK,
IX86_BUILTIN_MOVDQUQI256_MASK, IX86_BUILTIN_MOVDQUQI128_MASK,
IX86_BUILTIN_MINPS128_MASK, IX86_BUILTIN_MAXPS128_MASK,
IX86_BUILTIN_MINPD128_MASK, IX86_BUILTIN_MAXPD128_MASK,
IX86_BUILTIN_MAXPD256_MASK, IX86_BUILTIN_MAXPS256_MASK,
IX86_BUILTIN_MINPD256_MASK, IX86_BUILTIN_MINPS256_MASK,
IX86_BUILTIN_MULPS128_MASK, IX86_BUILTIN_DIVPS128_MASK,
IX86_BUILTIN_MULPD128_MASK, IX86_BUILTIN_DIVPD128_MASK,
IX86_BUILTIN_DIVPD256_MASK, IX86_BUILTIN_DIVPS256_MASK,
IX86_BUILTIN_MULPD256_MASK, IX86_BUILTIN_MULPS256_MASK,
IX86_BUILTIN_ADDPD128_MASK, IX86_BUILTIN_ADDPD256_MASK,
IX86_BUILTIN_ADDPS128_MASK, IX86_BUILTIN_ADDPS256_MASK,
IX86_BUILTIN_SUBPD128_MASK, IX86_BUILTIN_SUBPD256_MASK,
IX86_BUILTIN_SUBPS128_MASK, IX86_BUILTIN_SUBPS256_MASK,
IX86_BUILTIN_XORPD256_MASK, IX86_BUILTIN_XORPD128_MASK,
IX86_BUILTIN_XORPS256_MASK, IX86_BUILTIN_XORPS128_MASK,
IX86_BUILTIN_ORPD256_MASK, IX86_BUILTIN_ORPD128_MASK,
IX86_BUILTIN_ORPS256_MASK, IX86_BUILTIN_ORPS128_MASK,
IX86_BUILTIN_BROADCASTF32x2_256, IX86_BUILTIN_BROADCASTI32x2_256,
IX86_BUILTIN_BROADCASTI32x2_128, IX86_BUILTIN_BROADCASTF64X2_256,
IX86_BUILTIN_BROADCASTI64X2_256, IX86_BUILTIN_BROADCASTF32X4_256,
IX86_BUILTIN_BROADCASTI32X4_256, IX86_BUILTIN_EXTRACTF32X4_256,
IX86_BUILTIN_EXTRACTI32X4_256, IX86_BUILTIN_DBPSADBW256,
IX86_BUILTIN_DBPSADBW128, IX86_BUILTIN_CVTTPD2QQ256,
IX86_BUILTIN_CVTTPD2QQ128, IX86_BUILTIN_CVTTPD2UQQ256,
IX86_BUILTIN_CVTTPD2UQQ128, IX86_BUILTIN_CVTPD2QQ256,
IX86_BUILTIN_CVTPD2QQ128, IX86_BUILTIN_CVTPD2UQQ256,
IX86_BUILTIN_CVTPD2UQQ128, IX86_BUILTIN_CVTPD2UDQ256_MASK,
IX86_BUILTIN_CVTPD2UDQ128_MASK, IX86_BUILTIN_CVTTPS2QQ256,
IX86_BUILTIN_CVTTPS2QQ128, IX86_BUILTIN_CVTTPS2UQQ256,
IX86_BUILTIN_CVTTPS2UQQ128, IX86_BUILTIN_CVTTPS2DQ256_MASK,
IX86_BUILTIN_CVTTPS2DQ128_MASK, IX86_BUILTIN_CVTTPS2UDQ256,
IX86_BUILTIN_CVTTPS2UDQ128, IX86_BUILTIN_CVTTPD2DQ256_MASK,
IX86_BUILTIN_CVTTPD2DQ128_MASK, IX86_BUILTIN_CVTTPD2UDQ256_MASK,
IX86_BUILTIN_CVTTPD2UDQ128_MASK, IX86_BUILTIN_CVTPD2DQ256_MASK,
IX86_BUILTIN_CVTPD2DQ128_MASK, IX86_BUILTIN_CVTDQ2PD256_MASK,
IX86_BUILTIN_CVTDQ2PD128_MASK, IX86_BUILTIN_CVTUDQ2PD256_MASK,
IX86_BUILTIN_CVTUDQ2PD128_MASK, IX86_BUILTIN_CVTDQ2PS256_MASK,
IX86_BUILTIN_CVTDQ2PS128_MASK, IX86_BUILTIN_CVTUDQ2PS256_MASK,
IX86_BUILTIN_CVTUDQ2PS128_MASK, IX86_BUILTIN_CVTPS2PD256_MASK,
IX86_BUILTIN_CVTPS2PD128_MASK, IX86_BUILTIN_PBROADCASTB256_MASK,
IX86_BUILTIN_PBROADCASTB256_GPR_MASK, IX86_BUILTIN_PBROADCASTB128_MASK,
IX86_BUILTIN_PBROADCASTB128_GPR_MASK, IX86_BUILTIN_PBROADCASTW256_MASK,
IX86_BUILTIN_PBROADCASTW256_GPR_MASK, IX86_BUILTIN_PBROADCASTW128_MASK,
IX86_BUILTIN_PBROADCASTW128_GPR_MASK, IX86_BUILTIN_PBROADCASTD256_MASK,
IX86_BUILTIN_PBROADCASTD256_GPR_MASK, IX86_BUILTIN_PBROADCASTD128_MASK,
IX86_BUILTIN_PBROADCASTD128_GPR_MASK, IX86_BUILTIN_PBROADCASTQ256_MASK,
IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, IX86_BUILTIN_PBROADCASTQ256_MEM_MASK,
IX86_BUILTIN_PBROADCASTQ128_MASK, IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
IX86_BUILTIN_PBROADCASTQ128_MEM_MASK, IX86_BUILTIN_BROADCASTSS256,
IX86_BUILTIN_BROADCASTSS128, IX86_BUILTIN_BROADCASTSD256,
IX86_BUILTIN_EXTRACTF64X2_256, IX86_BUILTIN_EXTRACTI64X2_256,
IX86_BUILTIN_INSERTF32X4_256, IX86_BUILTIN_INSERTI32X4_256,
IX86_BUILTIN_PMOVSXBW256_MASK, IX86_BUILTIN_PMOVSXBW128_MASK,
IX86_BUILTIN_PMOVSXBD256_MASK, IX86_BUILTIN_PMOVSXBD128_MASK,
IX86_BUILTIN_PMOVSXBQ256_MASK, IX86_BUILTIN_PMOVSXBQ128_MASK,
IX86_BUILTIN_PMOVSXWD256_MASK, IX86_BUILTIN_PMOVSXWD128_MASK,
IX86_BUILTIN_PMOVSXWQ256_MASK, IX86_BUILTIN_PMOVSXWQ128_MASK,
IX86_BUILTIN_PMOVSXDQ256_MASK, IX86_BUILTIN_PMOVSXDQ128_MASK,
IX86_BUILTIN_PMOVZXBW256_MASK, IX86_BUILTIN_PMOVZXBW128_MASK,
IX86_BUILTIN_PMOVZXBD256_MASK, IX86_BUILTIN_PMOVZXBD128_MASK,
IX86_BUILTIN_PMOVZXBQ256_MASK, IX86_BUILTIN_PMOVZXBQ128_MASK,
IX86_BUILTIN_PMOVZXWD256_MASK, IX86_BUILTIN_PMOVZXWD128_MASK,
IX86_BUILTIN_PMOVZXWQ256_MASK, IX86_BUILTIN_PMOVZXWQ128_MASK,
IX86_BUILTIN_PMOVZXDQ256_MASK, IX86_BUILTIN_PMOVZXDQ128_MASK,
IX86_BUILTIN_REDUCEPD256_MASK, IX86_BUILTIN_REDUCEPD128_MASK,
IX86_BUILTIN_REDUCEPS256_MASK, IX86_BUILTIN_REDUCEPS128_MASK,
IX86_BUILTIN_REDUCESD_MASK, IX86_BUILTIN_REDUCESS_MASK,
IX86_BUILTIN_VPERMVARHI256_MASK, IX86_BUILTIN_VPERMVARHI128_MASK,
IX86_BUILTIN_VPERMT2VARHI256, IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
IX86_BUILTIN_VPERMT2VARHI128, IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
IX86_BUILTIN_VPERMI2VARHI256, IX86_BUILTIN_VPERMI2VARHI128,
IX86_BUILTIN_RCP14PD256, IX86_BUILTIN_RCP14PD128,
IX86_BUILTIN_RCP14PS256, IX86_BUILTIN_RCP14PS128,
IX86_BUILTIN_RSQRT14PD256_MASK, IX86_BUILTIN_RSQRT14PD128_MASK,
IX86_BUILTIN_RSQRT14PS256_MASK, IX86_BUILTIN_RSQRT14PS128_MASK,
IX86_BUILTIN_SQRTPD256_MASK, IX86_BUILTIN_SQRTPD128_MASK,
IX86_BUILTIN_SQRTPS256_MASK, IX86_BUILTIN_SQRTPS128_MASK,
IX86_BUILTIN_PADDB128_MASK, IX86_BUILTIN_PADDW128_MASK,
IX86_BUILTIN_PADDD128_MASK, IX86_BUILTIN_PADDQ128_MASK,
IX86_BUILTIN_PSUBB128_MASK, IX86_BUILTIN_PSUBW128_MASK,
IX86_BUILTIN_PSUBD128_MASK, IX86_BUILTIN_PSUBQ128_MASK,
IX86_BUILTIN_PADDSB128_MASK, IX86_BUILTIN_PADDSW128_MASK,
IX86_BUILTIN_PSUBSB128_MASK, IX86_BUILTIN_PSUBSW128_MASK,
IX86_BUILTIN_PADDUSB128_MASK, IX86_BUILTIN_PADDUSW128_MASK,
IX86_BUILTIN_PSUBUSB128_MASK, IX86_BUILTIN_PSUBUSW128_MASK,
IX86_BUILTIN_PADDB256_MASK, IX86_BUILTIN_PADDW256_MASK,
IX86_BUILTIN_PADDD256_MASK, IX86_BUILTIN_PADDQ256_MASK,
IX86_BUILTIN_PADDSB256_MASK, IX86_BUILTIN_PADDSW256_MASK,
IX86_BUILTIN_PADDUSB256_MASK, IX86_BUILTIN_PADDUSW256_MASK,
IX86_BUILTIN_PSUBB256_MASK, IX86_BUILTIN_PSUBW256_MASK,
IX86_BUILTIN_PSUBD256_MASK, IX86_BUILTIN_PSUBQ256_MASK,
IX86_BUILTIN_PSUBSB256_MASK, IX86_BUILTIN_PSUBSW256_MASK,
IX86_BUILTIN_PSUBUSB256_MASK, IX86_BUILTIN_PSUBUSW256_MASK,
IX86_BUILTIN_SHUF_F64x2_256, IX86_BUILTIN_SHUF_I64x2_256,
IX86_BUILTIN_SHUF_I32x4_256, IX86_BUILTIN_SHUF_F32x4_256,
IX86_BUILTIN_PMOVWB128, IX86_BUILTIN_PMOVWB256,
IX86_BUILTIN_PMOVSWB128, IX86_BUILTIN_PMOVSWB256,
IX86_BUILTIN_PMOVUSWB128, IX86_BUILTIN_PMOVUSWB256,
IX86_BUILTIN_PMOVDB128, IX86_BUILTIN_PMOVDB256,
IX86_BUILTIN_PMOVSDB128, IX86_BUILTIN_PMOVSDB256,
IX86_BUILTIN_PMOVUSDB128, IX86_BUILTIN_PMOVUSDB256,
IX86_BUILTIN_PMOVDW128, IX86_BUILTIN_PMOVDW256,
IX86_BUILTIN_PMOVSDW128, IX86_BUILTIN_PMOVSDW256,
IX86_BUILTIN_PMOVUSDW128, IX86_BUILTIN_PMOVUSDW256,
IX86_BUILTIN_PMOVQB128, IX86_BUILTIN_PMOVQB256,
IX86_BUILTIN_PMOVSQB128, IX86_BUILTIN_PMOVSQB256,
IX86_BUILTIN_PMOVUSQB128, IX86_BUILTIN_PMOVUSQB256,
IX86_BUILTIN_PMOVQW128, IX86_BUILTIN_PMOVQW256,
IX86_BUILTIN_PMOVSQW128, IX86_BUILTIN_PMOVSQW256,
IX86_BUILTIN_PMOVUSQW128, IX86_BUILTIN_PMOVUSQW256,
IX86_BUILTIN_PMOVQD128, IX86_BUILTIN_PMOVQD256,
IX86_BUILTIN_PMOVSQD128, IX86_BUILTIN_PMOVSQD256,
IX86_BUILTIN_PMOVUSQD128, IX86_BUILTIN_PMOVUSQD256,
IX86_BUILTIN_RANGEPD256, IX86_BUILTIN_RANGEPD128,
IX86_BUILTIN_RANGEPS256, IX86_BUILTIN_RANGEPS128,
IX86_BUILTIN_GETEXPPS256, IX86_BUILTIN_GETEXPPD256,
IX86_BUILTIN_GETEXPPS128, IX86_BUILTIN_GETEXPPD128,
IX86_BUILTIN_FIXUPIMMPD256, IX86_BUILTIN_FIXUPIMMPD256_MASK,
IX86_BUILTIN_FIXUPIMMPD256_MASKZ, IX86_BUILTIN_FIXUPIMMPS256,
IX86_BUILTIN_FIXUPIMMPS256_MASK, IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
IX86_BUILTIN_FIXUPIMMPD128, IX86_BUILTIN_FIXUPIMMPD128_MASK,
IX86_BUILTIN_FIXUPIMMPD128_MASKZ, IX86_BUILTIN_FIXUPIMMPS128,
IX86_BUILTIN_FIXUPIMMPS128_MASK, IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
IX86_BUILTIN_PABSQ256, IX86_BUILTIN_PABSQ128,
IX86_BUILTIN_PABSD256_MASK, IX86_BUILTIN_PABSD128_MASK,
IX86_BUILTIN_PMULHRSW256_MASK, IX86_BUILTIN_PMULHRSW128_MASK,
IX86_BUILTIN_PMULHUW128_MASK, IX86_BUILTIN_PMULHUW256_MASK,
IX86_BUILTIN_PMULHW256_MASK, IX86_BUILTIN_PMULHW128_MASK,
IX86_BUILTIN_PMULLW256_MASK, IX86_BUILTIN_PMULLW128_MASK,
IX86_BUILTIN_PMULLQ256, IX86_BUILTIN_PMULLQ128,
IX86_BUILTIN_ANDPD256_MASK, IX86_BUILTIN_ANDPD128_MASK,
IX86_BUILTIN_ANDPS256_MASK, IX86_BUILTIN_ANDPS128_MASK,
IX86_BUILTIN_ANDNPD256_MASK, IX86_BUILTIN_ANDNPD128_MASK,
IX86_BUILTIN_ANDNPS256_MASK, IX86_BUILTIN_ANDNPS128_MASK,
IX86_BUILTIN_PSLLWI128_MASK, IX86_BUILTIN_PSLLDI128_MASK,
IX86_BUILTIN_PSLLQI128_MASK, IX86_BUILTIN_PSLLW128_MASK,
IX86_BUILTIN_PSLLD128_MASK, IX86_BUILTIN_PSLLQ128_MASK,
IX86_BUILTIN_PSLLWI256_MASK , IX86_BUILTIN_PSLLW256_MASK,
IX86_BUILTIN_PSLLDI256_MASK, IX86_BUILTIN_PSLLD256_MASK,
IX86_BUILTIN_PSLLQI256_MASK, IX86_BUILTIN_PSLLQ256_MASK,
IX86_BUILTIN_PSRADI128_MASK, IX86_BUILTIN_PSRAD128_MASK,
IX86_BUILTIN_PSRADI256_MASK, IX86_BUILTIN_PSRAD256_MASK,
IX86_BUILTIN_PSRAQI128_MASK, IX86_BUILTIN_PSRAQ128_MASK,
IX86_BUILTIN_PSRAQI256_MASK, IX86_BUILTIN_PSRAQ256_MASK,
IX86_BUILTIN_PANDD256, IX86_BUILTIN_PANDD128,
IX86_BUILTIN_PSRLDI128_MASK, IX86_BUILTIN_PSRLD128_MASK,
IX86_BUILTIN_PSRLDI256_MASK, IX86_BUILTIN_PSRLD256_MASK,
IX86_BUILTIN_PSRLQI128_MASK, IX86_BUILTIN_PSRLQ128_MASK,
IX86_BUILTIN_PSRLQI256_MASK, IX86_BUILTIN_PSRLQ256_MASK,
IX86_BUILTIN_PANDQ256, IX86_BUILTIN_PANDQ128,
IX86_BUILTIN_PANDND256, IX86_BUILTIN_PANDND128,
IX86_BUILTIN_PANDNQ256, IX86_BUILTIN_PANDNQ128,
IX86_BUILTIN_PORD256, IX86_BUILTIN_PORD128,
IX86_BUILTIN_PORQ256, IX86_BUILTIN_PORQ128,
IX86_BUILTIN_PXORD256, IX86_BUILTIN_PXORD128,
IX86_BUILTIN_PXORQ256, IX86_BUILTIN_PXORQ128,
IX86_BUILTIN_PACKSSWB256_MASK, IX86_BUILTIN_PACKSSWB128_MASK,
IX86_BUILTIN_PACKUSWB256_MASK, IX86_BUILTIN_PACKUSWB128_MASK,
IX86_BUILTIN_RNDSCALEPS256, IX86_BUILTIN_RNDSCALEPD256,
IX86_BUILTIN_RNDSCALEPS128, IX86_BUILTIN_RNDSCALEPD128,
IX86_BUILTIN_VTERNLOGQ256_MASK, IX86_BUILTIN_VTERNLOGQ256_MASKZ,
IX86_BUILTIN_VTERNLOGD256_MASK, IX86_BUILTIN_VTERNLOGD256_MASKZ,
IX86_BUILTIN_VTERNLOGQ128_MASK, IX86_BUILTIN_VTERNLOGQ128_MASKZ,
IX86_BUILTIN_VTERNLOGD128_MASK, IX86_BUILTIN_VTERNLOGD128_MASKZ,
IX86_BUILTIN_SCALEFPD256, IX86_BUILTIN_SCALEFPS256,
IX86_BUILTIN_SCALEFPD128, IX86_BUILTIN_SCALEFPS128,
IX86_BUILTIN_VFMADDPD256_MASK, IX86_BUILTIN_VFMADDPD256_MASK3,
IX86_BUILTIN_VFMADDPD256_MASKZ, IX86_BUILTIN_VFMADDPD128_MASK,
IX86_BUILTIN_VFMADDPD128_MASK3, IX86_BUILTIN_VFMADDPD128_MASKZ,
IX86_BUILTIN_VFMADDPS256_MASK, IX86_BUILTIN_VFMADDPS256_MASK3,
IX86_BUILTIN_VFMADDPS256_MASKZ, IX86_BUILTIN_VFMADDPS128_MASK,
IX86_BUILTIN_VFMADDPS128_MASK3, IX86_BUILTIN_VFMADDPS128_MASKZ,
IX86_BUILTIN_VFMSUBPD256_MASK3, IX86_BUILTIN_VFMSUBPD128_MASK3,
IX86_BUILTIN_VFMSUBPS256_MASK3, IX86_BUILTIN_VFMSUBPS128_MASK3,
IX86_BUILTIN_VFNMADDPD256_MASK, IX86_BUILTIN_VFNMADDPD128_MASK,
IX86_BUILTIN_VFNMADDPS256_MASK, IX86_BUILTIN_VFNMADDPS128_MASK,
IX86_BUILTIN_VFNMSUBPD256_MASK, IX86_BUILTIN_VFNMSUBPD256_MASK3,
IX86_BUILTIN_VFNMSUBPD128_MASK, IX86_BUILTIN_VFNMSUBPD128_MASK3,
IX86_BUILTIN_VFNMSUBPS256_MASK, IX86_BUILTIN_VFNMSUBPS256_MASK3,
IX86_BUILTIN_VFNMSUBPS128_MASK, IX86_BUILTIN_VFNMSUBPS128_MASK3,
IX86_BUILTIN_VFMADDSUBPD256_MASK, IX86_BUILTIN_VFMADDSUBPD256_MASK3,
IX86_BUILTIN_VFMADDSUBPD256_MASKZ, IX86_BUILTIN_VFMADDSUBPD128_MASK,
IX86_BUILTIN_VFMADDSUBPD128_MASK3, IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
IX86_BUILTIN_VFMADDSUBPS256_MASK, IX86_BUILTIN_VFMADDSUBPS256_MASK3,
IX86_BUILTIN_VFMADDSUBPS256_MASKZ, IX86_BUILTIN_VFMADDSUBPS128_MASK,
IX86_BUILTIN_VFMADDSUBPS128_MASK3, IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
IX86_BUILTIN_VFMSUBADDPD256_MASK3, IX86_BUILTIN_VFMSUBADDPD128_MASK3,
IX86_BUILTIN_VFMSUBADDPS256_MASK3, IX86_BUILTIN_VFMSUBADDPS128_MASK3,
IX86_BUILTIN_INSERTF64X2_256, IX86_BUILTIN_INSERTI64X2_256,
IX86_BUILTIN_PSRAVV16HI, IX86_BUILTIN_PSRAVV8HI,
IX86_BUILTIN_PMADDUBSW256_MASK, IX86_BUILTIN_PMADDUBSW128_MASK,
IX86_BUILTIN_PMADDWD256_MASK, IX86_BUILTIN_PMADDWD128_MASK,
IX86_BUILTIN_PSRLVV16HI, IX86_BUILTIN_PSRLVV8HI,
IX86_BUILTIN_CVTPS2DQ256_MASK, IX86_BUILTIN_CVTPS2DQ128_MASK,
IX86_BUILTIN_CVTPS2UDQ256, IX86_BUILTIN_CVTPS2UDQ128,
IX86_BUILTIN_CVTPS2QQ256, IX86_BUILTIN_CVTPS2QQ128,
IX86_BUILTIN_CVTPS2UQQ256, IX86_BUILTIN_CVTPS2UQQ128,
IX86_BUILTIN_GETMANTPS256, IX86_BUILTIN_GETMANTPS128,
IX86_BUILTIN_GETMANTPD256, IX86_BUILTIN_GETMANTPD128,
IX86_BUILTIN_MOVDDUP256_MASK, IX86_BUILTIN_MOVDDUP128_MASK,
IX86_BUILTIN_MOVSHDUP256_MASK, IX86_BUILTIN_MOVSHDUP128_MASK,
IX86_BUILTIN_MOVSLDUP256_MASK, IX86_BUILTIN_MOVSLDUP128_MASK,
IX86_BUILTIN_CVTQQ2PS256, IX86_BUILTIN_CVTQQ2PS128,
IX86_BUILTIN_CVTUQQ2PS256, IX86_BUILTIN_CVTUQQ2PS128,
IX86_BUILTIN_CVTQQ2PD256, IX86_BUILTIN_CVTQQ2PD128,
IX86_BUILTIN_CVTUQQ2PD256, IX86_BUILTIN_CVTUQQ2PD128,
IX86_BUILTIN_VPERMT2VARQ256, IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
IX86_BUILTIN_VPERMT2VARD256, IX86_BUILTIN_VPERMT2VARD256_MASKZ,
IX86_BUILTIN_VPERMI2VARQ256, IX86_BUILTIN_VPERMI2VARD256,
IX86_BUILTIN_VPERMT2VARPD256, IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
IX86_BUILTIN_VPERMT2VARPS256, IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
IX86_BUILTIN_VPERMI2VARPD256, IX86_BUILTIN_VPERMI2VARPS256,
IX86_BUILTIN_VPERMT2VARQ128, IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
IX86_BUILTIN_VPERMT2VARD128, IX86_BUILTIN_VPERMT2VARD128_MASKZ,
IX86_BUILTIN_VPERMI2VARQ128, IX86_BUILTIN_VPERMI2VARD128,
IX86_BUILTIN_VPERMT2VARPD128, IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
IX86_BUILTIN_VPERMT2VARPS128, IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
IX86_BUILTIN_VPERMI2VARPD128, IX86_BUILTIN_VPERMI2VARPS128,
IX86_BUILTIN_PSHUFB256_MASK, IX86_BUILTIN_PSHUFB128_MASK,
IX86_BUILTIN_PSHUFHW256_MASK, IX86_BUILTIN_PSHUFHW128_MASK,
IX86_BUILTIN_PSHUFLW256_MASK, IX86_BUILTIN_PSHUFLW128_MASK,
IX86_BUILTIN_PSHUFD256_MASK, IX86_BUILTIN_PSHUFD128_MASK,
IX86_BUILTIN_SHUFPD256_MASK, IX86_BUILTIN_SHUFPD128_MASK,
IX86_BUILTIN_SHUFPS256_MASK, IX86_BUILTIN_SHUFPS128_MASK,
IX86_BUILTIN_PROLVQ256, IX86_BUILTIN_PROLVQ128,
IX86_BUILTIN_PROLQ256, IX86_BUILTIN_PROLQ128,
IX86_BUILTIN_PRORVQ256, IX86_BUILTIN_PRORVQ128,
IX86_BUILTIN_PRORQ256, IX86_BUILTIN_PRORQ128,
IX86_BUILTIN_PSRAVQ128, IX86_BUILTIN_PSRAVQ256,
IX86_BUILTIN_PSLLVV4DI_MASK, IX86_BUILTIN_PSLLVV2DI_MASK,
IX86_BUILTIN_PSLLVV8SI_MASK, IX86_BUILTIN_PSLLVV4SI_MASK,
IX86_BUILTIN_PSRAVV8SI_MASK, IX86_BUILTIN_PSRAVV4SI_MASK,
IX86_BUILTIN_PSRLVV4DI_MASK, IX86_BUILTIN_PSRLVV2DI_MASK,
IX86_BUILTIN_PSRLVV8SI_MASK, IX86_BUILTIN_PSRLVV4SI_MASK,
IX86_BUILTIN_PSRAWI256_MASK, IX86_BUILTIN_PSRAW256_MASK,
IX86_BUILTIN_PSRAWI128_MASK, IX86_BUILTIN_PSRAW128_MASK,
IX86_BUILTIN_PSRLWI256_MASK, IX86_BUILTIN_PSRLW256_MASK,
IX86_BUILTIN_PSRLWI128_MASK, IX86_BUILTIN_PSRLW128_MASK,
IX86_BUILTIN_PRORVD256, IX86_BUILTIN_PROLVD256,
IX86_BUILTIN_PRORD256, IX86_BUILTIN_PROLD256,
IX86_BUILTIN_PRORVD128, IX86_BUILTIN_PROLVD128,
IX86_BUILTIN_PRORD128, IX86_BUILTIN_PROLD128,
IX86_BUILTIN_FPCLASSPD256, IX86_BUILTIN_FPCLASSPD128,
IX86_BUILTIN_FPCLASSSD, IX86_BUILTIN_FPCLASSPS256,
IX86_BUILTIN_FPCLASSPS128, IX86_BUILTIN_FPCLASSSS,
IX86_BUILTIN_CVTB2MASK128, IX86_BUILTIN_CVTB2MASK256,
IX86_BUILTIN_CVTW2MASK128, IX86_BUILTIN_CVTW2MASK256,
IX86_BUILTIN_CVTD2MASK128, IX86_BUILTIN_CVTD2MASK256,
IX86_BUILTIN_CVTQ2MASK128, IX86_BUILTIN_CVTQ2MASK256,
IX86_BUILTIN_CVTMASK2B128, IX86_BUILTIN_CVTMASK2B256,
IX86_BUILTIN_CVTMASK2W128, IX86_BUILTIN_CVTMASK2W256,
IX86_BUILTIN_CVTMASK2D128, IX86_BUILTIN_CVTMASK2D256,
IX86_BUILTIN_CVTMASK2Q128, IX86_BUILTIN_CVTMASK2Q256,
IX86_BUILTIN_PCMPEQB128_MASK, IX86_BUILTIN_PCMPEQB256_MASK,
IX86_BUILTIN_PCMPEQW128_MASK, IX86_BUILTIN_PCMPEQW256_MASK,
IX86_BUILTIN_PCMPEQD128_MASK, IX86_BUILTIN_PCMPEQD256_MASK,
IX86_BUILTIN_PCMPEQQ128_MASK, IX86_BUILTIN_PCMPEQQ256_MASK,
IX86_BUILTIN_PCMPGTB128_MASK, IX86_BUILTIN_PCMPGTB256_MASK,
IX86_BUILTIN_PCMPGTW128_MASK, IX86_BUILTIN_PCMPGTW256_MASK,
IX86_BUILTIN_PCMPGTD128_MASK, IX86_BUILTIN_PCMPGTD256_MASK,
IX86_BUILTIN_PCMPGTQ128_MASK, IX86_BUILTIN_PCMPGTQ256_MASK,
IX86_BUILTIN_PTESTMB128, IX86_BUILTIN_PTESTMB256,
IX86_BUILTIN_PTESTMW128, IX86_BUILTIN_PTESTMW256,
IX86_BUILTIN_PTESTMD128, IX86_BUILTIN_PTESTMD256,
IX86_BUILTIN_PTESTMQ128, IX86_BUILTIN_PTESTMQ256,
IX86_BUILTIN_PTESTNMB128, IX86_BUILTIN_PTESTNMB256,
IX86_BUILTIN_PTESTNMW128, IX86_BUILTIN_PTESTNMW256,
IX86_BUILTIN_PTESTNMD128, IX86_BUILTIN_PTESTNMD256,
IX86_BUILTIN_PTESTNMQ128, IX86_BUILTIN_PTESTNMQ256,
IX86_BUILTIN_PBROADCASTMB128, IX86_BUILTIN_PBROADCASTMB256,
IX86_BUILTIN_PBROADCASTMW128, IX86_BUILTIN_PBROADCASTMW256,
IX86_BUILTIN_COMPRESSPD256, IX86_BUILTIN_COMPRESSPD128,
IX86_BUILTIN_COMPRESSPS256, IX86_BUILTIN_COMPRESSPS128,
IX86_BUILTIN_PCOMPRESSQ256, IX86_BUILTIN_PCOMPRESSQ128,
IX86_BUILTIN_PCOMPRESSD256, IX86_BUILTIN_PCOMPRESSD128,
IX86_BUILTIN_EXPANDPD256, IX86_BUILTIN_EXPANDPD128,
IX86_BUILTIN_EXPANDPS256, IX86_BUILTIN_EXPANDPS128,
IX86_BUILTIN_PEXPANDQ256, IX86_BUILTIN_PEXPANDQ128,
IX86_BUILTIN_PEXPANDD256, IX86_BUILTIN_PEXPANDD128,
IX86_BUILTIN_EXPANDPD256Z, IX86_BUILTIN_EXPANDPD128Z,
IX86_BUILTIN_EXPANDPS256Z, IX86_BUILTIN_EXPANDPS128Z,
IX86_BUILTIN_PEXPANDQ256Z, IX86_BUILTIN_PEXPANDQ128Z,
IX86_BUILTIN_PEXPANDD256Z, IX86_BUILTIN_PEXPANDD128Z,
IX86_BUILTIN_PMAXSD256_MASK, IX86_BUILTIN_PMINSD256_MASK,
IX86_BUILTIN_PMAXUD256_MASK, IX86_BUILTIN_PMINUD256_MASK,
IX86_BUILTIN_PMAXSD128_MASK, IX86_BUILTIN_PMINSD128_MASK,
IX86_BUILTIN_PMAXUD128_MASK, IX86_BUILTIN_PMINUD128_MASK,
IX86_BUILTIN_PMAXSQ256_MASK, IX86_BUILTIN_PMINSQ256_MASK,
IX86_BUILTIN_PMAXUQ256_MASK, IX86_BUILTIN_PMINUQ256_MASK,
IX86_BUILTIN_PMAXSQ128_MASK, IX86_BUILTIN_PMINSQ128_MASK,
IX86_BUILTIN_PMAXUQ128_MASK, IX86_BUILTIN_PMINUQ128_MASK,
IX86_BUILTIN_PMINSB256_MASK, IX86_BUILTIN_PMINUB256_MASK,
IX86_BUILTIN_PMAXSB256_MASK, IX86_BUILTIN_PMAXUB256_MASK,
IX86_BUILTIN_PMINSB128_MASK, IX86_BUILTIN_PMINUB128_MASK,
IX86_BUILTIN_PMAXSB128_MASK, IX86_BUILTIN_PMAXUB128_MASK,
IX86_BUILTIN_PMINSW256_MASK, IX86_BUILTIN_PMINUW256_MASK,
IX86_BUILTIN_PMAXSW256_MASK, IX86_BUILTIN_PMAXUW256_MASK,
IX86_BUILTIN_PMINSW128_MASK, IX86_BUILTIN_PMINUW128_MASK,
IX86_BUILTIN_PMAXSW128_MASK, IX86_BUILTIN_PMAXUW128_MASK,
IX86_BUILTIN_VPCONFLICTQ256, IX86_BUILTIN_VPCONFLICTD256,
IX86_BUILTIN_VPCLZCNTQ256, IX86_BUILTIN_VPCLZCNTD256,
IX86_BUILTIN_UNPCKHPD256_MASK, IX86_BUILTIN_UNPCKHPD128_MASK,
IX86_BUILTIN_UNPCKHPS256_MASK, IX86_BUILTIN_UNPCKHPS128_MASK,
IX86_BUILTIN_UNPCKLPD256_MASK, IX86_BUILTIN_UNPCKLPD128_MASK,
IX86_BUILTIN_UNPCKLPS256_MASK, IX86_BUILTIN_VPCONFLICTQ128,
IX86_BUILTIN_VPCONFLICTD128, IX86_BUILTIN_VPCLZCNTQ128,
IX86_BUILTIN_VPCLZCNTD128, IX86_BUILTIN_UNPCKLPS128_MASK,
IX86_BUILTIN_ALIGND256, IX86_BUILTIN_ALIGNQ256,
IX86_BUILTIN_ALIGND128, IX86_BUILTIN_ALIGNQ128,
IX86_BUILTIN_CVTPS2PH256_MASK, IX86_BUILTIN_CVTPS2PH_MASK,
IX86_BUILTIN_CVTPH2PS_MASK, IX86_BUILTIN_CVTPH2PS256_MASK,
IX86_BUILTIN_PUNPCKHDQ128_MASK, IX86_BUILTIN_PUNPCKHDQ256_MASK,
IX86_BUILTIN_PUNPCKHQDQ128_MASK, IX86_BUILTIN_PUNPCKHQDQ256_MASK,
IX86_BUILTIN_PUNPCKLDQ128_MASK, IX86_BUILTIN_PUNPCKLDQ256_MASK,
IX86_BUILTIN_PUNPCKLQDQ128_MASK, IX86_BUILTIN_PUNPCKLQDQ256_MASK,
IX86_BUILTIN_PUNPCKHBW128_MASK, IX86_BUILTIN_PUNPCKHBW256_MASK,
IX86_BUILTIN_PUNPCKHWD128_MASK, IX86_BUILTIN_PUNPCKHWD256_MASK,
IX86_BUILTIN_PUNPCKLBW128_MASK, IX86_BUILTIN_PUNPCKLBW256_MASK,
IX86_BUILTIN_PUNPCKLWD128_MASK, IX86_BUILTIN_PUNPCKLWD256_MASK,
IX86_BUILTIN_PSLLVV16HI, IX86_BUILTIN_PSLLVV8HI,
IX86_BUILTIN_PACKSSDW256_MASK, IX86_BUILTIN_PACKSSDW128_MASK,
IX86_BUILTIN_PACKUSDW256_MASK, IX86_BUILTIN_PACKUSDW128_MASK,
IX86_BUILTIN_PAVGB256_MASK, IX86_BUILTIN_PAVGW256_MASK,
IX86_BUILTIN_PAVGB128_MASK, IX86_BUILTIN_PAVGW128_MASK,
IX86_BUILTIN_VPERMVARSF256_MASK, IX86_BUILTIN_VPERMVARDF256_MASK,
IX86_BUILTIN_VPERMDF256_MASK, IX86_BUILTIN_PABSB256_MASK,
IX86_BUILTIN_PABSB128_MASK, IX86_BUILTIN_PABSW256_MASK,
IX86_BUILTIN_PABSW128_MASK, IX86_BUILTIN_VPERMILVARPD_MASK,
IX86_BUILTIN_VPERMILVARPS_MASK, IX86_BUILTIN_VPERMILVARPD256_MASK,
IX86_BUILTIN_VPERMILVARPS256_MASK, IX86_BUILTIN_VPERMILPD_MASK,
IX86_BUILTIN_VPERMILPS_MASK, IX86_BUILTIN_VPERMILPD256_MASK,
IX86_BUILTIN_VPERMILPS256_MASK, IX86_BUILTIN_BLENDMQ256,
IX86_BUILTIN_BLENDMD256, IX86_BUILTIN_BLENDMPD256,
IX86_BUILTIN_BLENDMPS256, IX86_BUILTIN_BLENDMQ128,
IX86_BUILTIN_BLENDMD128, IX86_BUILTIN_BLENDMPD128,
IX86_BUILTIN_BLENDMPS128, IX86_BUILTIN_BLENDMW256,
IX86_BUILTIN_BLENDMB256, IX86_BUILTIN_BLENDMW128,
IX86_BUILTIN_BLENDMB128, IX86_BUILTIN_PMULLD256_MASK,
IX86_BUILTIN_PMULLD128_MASK, IX86_BUILTIN_PMULUDQ256_MASK,
IX86_BUILTIN_PMULDQ256_MASK, IX86_BUILTIN_PMULDQ128_MASK,
IX86_BUILTIN_PMULUDQ128_MASK, IX86_BUILTIN_CVTPD2PS256_MASK,
IX86_BUILTIN_CVTPD2PS_MASK, IX86_BUILTIN_VPERMVARSI256_MASK,
IX86_BUILTIN_VPERMVARDI256_MASK, IX86_BUILTIN_VPERMDI256_MASK,
IX86_BUILTIN_CMPQ256, IX86_BUILTIN_CMPD256,
IX86_BUILTIN_UCMPQ256, IX86_BUILTIN_UCMPD256,
IX86_BUILTIN_CMPB256, IX86_BUILTIN_CMPW256,
IX86_BUILTIN_UCMPB256, IX86_BUILTIN_UCMPW256,
IX86_BUILTIN_CMPPD256_MASK, IX86_BUILTIN_CMPPS256_MASK,
IX86_BUILTIN_CMPQ128, IX86_BUILTIN_CMPD128,
IX86_BUILTIN_UCMPQ128, IX86_BUILTIN_UCMPD128,
IX86_BUILTIN_CMPB128, IX86_BUILTIN_CMPW128,
IX86_BUILTIN_UCMPB128, IX86_BUILTIN_UCMPW128,
IX86_BUILTIN_CMPPD128_MASK, IX86_BUILTIN_CMPPS128_MASK,
IX86_BUILTIN_GATHER3SIV8SF, IX86_BUILTIN_GATHER3SIV4SF,
IX86_BUILTIN_GATHER3SIV4DF, IX86_BUILTIN_GATHER3SIV2DF,
IX86_BUILTIN_GATHER3DIV8SF, IX86_BUILTIN_GATHER3DIV4SF,
IX86_BUILTIN_GATHER3DIV4DF, IX86_BUILTIN_GATHER3DIV2DF,
IX86_BUILTIN_GATHER3SIV8SI, IX86_BUILTIN_GATHER3SIV4SI,
IX86_BUILTIN_GATHER3SIV4DI, IX86_BUILTIN_GATHER3SIV2DI,
IX86_BUILTIN_GATHER3DIV8SI, IX86_BUILTIN_GATHER3DIV4SI,
IX86_BUILTIN_GATHER3DIV4DI, IX86_BUILTIN_GATHER3DIV2DI,
IX86_BUILTIN_SCATTERSIV8SF, IX86_BUILTIN_SCATTERSIV4SF,
IX86_BUILTIN_SCATTERSIV4DF, IX86_BUILTIN_SCATTERSIV2DF,
IX86_BUILTIN_SCATTERDIV8SF, IX86_BUILTIN_SCATTERDIV4SF,
IX86_BUILTIN_SCATTERDIV4DF, IX86_BUILTIN_SCATTERDIV2DF,
IX86_BUILTIN_SCATTERSIV8SI, IX86_BUILTIN_SCATTERSIV4SI,
IX86_BUILTIN_SCATTERSIV4DI, IX86_BUILTIN_SCATTERSIV2DI,
IX86_BUILTIN_SCATTERDIV8SI, IX86_BUILTIN_SCATTERDIV4SI,
IX86_BUILTIN_SCATTERDIV4DI, IX86_BUILTIN_SCATTERDIV2DI,
IX86_BUILTIN_RANGESD128, IX86_BUILTIN_RANGESS128,
IX86_BUILTIN_KUNPCKWD, IX86_BUILTIN_KUNPCKDQ,
IX86_BUILTIN_BROADCASTF32x2_512, IX86_BUILTIN_BROADCASTI32x2_512,
IX86_BUILTIN_BROADCASTF64X2_512, IX86_BUILTIN_BROADCASTI64X2_512,
IX86_BUILTIN_BROADCASTF32X8_512, IX86_BUILTIN_BROADCASTI32X8_512,
IX86_BUILTIN_EXTRACTF64X2_512, IX86_BUILTIN_EXTRACTF32X8,
IX86_BUILTIN_EXTRACTI64X2_512, IX86_BUILTIN_EXTRACTI32X8,
IX86_BUILTIN_REDUCEPD512_MASK, IX86_BUILTIN_REDUCEPS512_MASK,
IX86_BUILTIN_PMULLQ512, IX86_BUILTIN_XORPD512,
IX86_BUILTIN_XORPS512, IX86_BUILTIN_ORPD512,
IX86_BUILTIN_ORPS512, IX86_BUILTIN_ANDPD512,
IX86_BUILTIN_ANDPS512, IX86_BUILTIN_ANDNPD512,
IX86_BUILTIN_ANDNPS512, IX86_BUILTIN_INSERTF32X8,
IX86_BUILTIN_INSERTI32X8, IX86_BUILTIN_INSERTF64X2_512,
IX86_BUILTIN_INSERTI64X2_512, IX86_BUILTIN_FPCLASSPD512,
IX86_BUILTIN_FPCLASSPS512, IX86_BUILTIN_CVTD2MASK512,
IX86_BUILTIN_CVTQ2MASK512, IX86_BUILTIN_CVTMASK2D512,
IX86_BUILTIN_CVTMASK2Q512, IX86_BUILTIN_CVTPD2QQ512,
IX86_BUILTIN_CVTPS2QQ512, IX86_BUILTIN_CVTPD2UQQ512,
IX86_BUILTIN_CVTPS2UQQ512, IX86_BUILTIN_CVTQQ2PS512,
IX86_BUILTIN_CVTUQQ2PS512, IX86_BUILTIN_CVTQQ2PD512,
IX86_BUILTIN_CVTUQQ2PD512, IX86_BUILTIN_CVTTPS2QQ512,
IX86_BUILTIN_CVTTPS2UQQ512, IX86_BUILTIN_CVTTPD2QQ512,
IX86_BUILTIN_CVTTPD2UQQ512, IX86_BUILTIN_RANGEPS512,
IX86_BUILTIN_RANGEPD512, IX86_BUILTIN_PACKUSDW512,
IX86_BUILTIN_PACKSSDW512, IX86_BUILTIN_LOADDQUHI512_MASK,
IX86_BUILTIN_LOADDQUQI512_MASK, IX86_BUILTIN_PSLLDQ512,
IX86_BUILTIN_PSRLDQ512, IX86_BUILTIN_STOREDQUHI512_MASK,
IX86_BUILTIN_STOREDQUQI512_MASK, IX86_BUILTIN_PALIGNR512,
IX86_BUILTIN_PALIGNR512_MASK, IX86_BUILTIN_MOVDQUHI512_MASK,
IX86_BUILTIN_MOVDQUQI512_MASK, IX86_BUILTIN_PSADBW512,
IX86_BUILTIN_DBPSADBW512, IX86_BUILTIN_PBROADCASTB512,
IX86_BUILTIN_PBROADCASTB512_GPR, IX86_BUILTIN_PBROADCASTW512,
IX86_BUILTIN_PBROADCASTW512_GPR, IX86_BUILTIN_PMOVSXBW512_MASK,
IX86_BUILTIN_PMOVZXBW512_MASK, IX86_BUILTIN_VPERMVARHI512_MASK,
IX86_BUILTIN_VPERMT2VARHI512, IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
IX86_BUILTIN_VPERMI2VARHI512, IX86_BUILTIN_PAVGB512,
IX86_BUILTIN_PAVGW512, IX86_BUILTIN_PADDB512,
IX86_BUILTIN_PSUBB512, IX86_BUILTIN_PSUBSB512,
IX86_BUILTIN_PADDSB512, IX86_BUILTIN_PSUBUSB512,
IX86_BUILTIN_PADDUSB512, IX86_BUILTIN_PSUBW512,
IX86_BUILTIN_PADDW512, IX86_BUILTIN_PSUBSW512,
IX86_BUILTIN_PADDSW512, IX86_BUILTIN_PSUBUSW512,
IX86_BUILTIN_PADDUSW512, IX86_BUILTIN_PMAXUW512,
IX86_BUILTIN_PMAXSW512, IX86_BUILTIN_PMINUW512,
IX86_BUILTIN_PMINSW512, IX86_BUILTIN_PMAXUB512,
IX86_BUILTIN_PMAXSB512, IX86_BUILTIN_PMINUB512,
IX86_BUILTIN_PMINSB512, IX86_BUILTIN_PMOVWB512,
IX86_BUILTIN_PMOVSWB512, IX86_BUILTIN_PMOVUSWB512,
IX86_BUILTIN_PMULHRSW512_MASK, IX86_BUILTIN_PMULHUW512_MASK,
IX86_BUILTIN_PMULHW512_MASK, IX86_BUILTIN_PMULLW512_MASK,
IX86_BUILTIN_PSLLWI512_MASK, IX86_BUILTIN_PSLLW512_MASK,
IX86_BUILTIN_PACKSSWB512, IX86_BUILTIN_PACKUSWB512,
IX86_BUILTIN_PSRAVV32HI, IX86_BUILTIN_PMADDUBSW512_MASK,
IX86_BUILTIN_PMADDWD512_MASK, IX86_BUILTIN_PSRLVV32HI,
IX86_BUILTIN_PUNPCKHBW512, IX86_BUILTIN_PUNPCKHWD512,
IX86_BUILTIN_PUNPCKLBW512, IX86_BUILTIN_PUNPCKLWD512,
IX86_BUILTIN_PSHUFB512, IX86_BUILTIN_PSHUFHW512,
IX86_BUILTIN_PSHUFLW512, IX86_BUILTIN_PSRAWI512,
IX86_BUILTIN_PSRAW512, IX86_BUILTIN_PSRLWI512,
IX86_BUILTIN_PSRLW512, IX86_BUILTIN_CVTB2MASK512,
IX86_BUILTIN_CVTW2MASK512, IX86_BUILTIN_CVTMASK2B512,
IX86_BUILTIN_CVTMASK2W512, IX86_BUILTIN_PCMPEQB512_MASK,
IX86_BUILTIN_PCMPEQW512_MASK, IX86_BUILTIN_PCMPGTB512_MASK,
IX86_BUILTIN_PCMPGTW512_MASK, IX86_BUILTIN_PTESTMB512,
IX86_BUILTIN_PTESTMW512, IX86_BUILTIN_PTESTNMB512,
IX86_BUILTIN_PTESTNMW512, IX86_BUILTIN_PSLLVV32HI,
IX86_BUILTIN_PABSB512, IX86_BUILTIN_PABSW512,
IX86_BUILTIN_BLENDMW512, IX86_BUILTIN_BLENDMB512,
IX86_BUILTIN_CMPB512, IX86_BUILTIN_CMPW512,
IX86_BUILTIN_UCMPB512, IX86_BUILTIN_UCMPW512.
(bdesc_special_args):
Add __builtin_ia32_loaddquhi512_mask, __builtin_ia32_loaddquqi512_mask,
__builtin_ia32_storedquhi512_mask, __builtin_ia32_storedquqi512_mask,
__builtin_ia32_loaddquhi256_mask, __builtin_ia32_loaddquhi128_mask,
__builtin_ia32_loaddquqi256_mask, __builtin_ia32_loaddquqi128_mask,
__builtin_ia32_movdqa64load256_mask, __builtin_ia32_movdqa64load128_mask,
__builtin_ia32_movdqa32load256_mask, __builtin_ia32_movdqa32load128_mask,
__builtin_ia32_movdqa64store256_mask, __builtin_ia32_movdqa64store128_mask,
__builtin_ia32_movdqa32store256_mask, __builtin_ia32_movdqa32store128_mask,
__builtin_ia32_loadapd256_mask, __builtin_ia32_loadapd128_mask,
__builtin_ia32_loadaps256_mask, __builtin_ia32_loadaps128_mask,
__builtin_ia32_storeapd256_mask, __builtin_ia32_storeapd128_mask,
__builtin_ia32_storeaps256_mask, __builtin_ia32_storeaps128_mask,
__builtin_ia32_loadupd256_mask, __builtin_ia32_loadupd128_mask,
__builtin_ia32_loadups256_mask, __builtin_ia32_loadups128_mask,
__builtin_ia32_storeupd256_mask, __builtin_ia32_storeupd128_mask,
__builtin_ia32_storeups256_mask, __builtin_ia32_storeups128_mask,
__builtin_ia32_loaddqudi256_mask, __builtin_ia32_loaddqudi128_mask,
__builtin_ia32_loaddqusi256_mask, __builtin_ia32_loaddqusi128_mask,
__builtin_ia32_storedqudi256_mask, __builtin_ia32_storedqudi128_mask,
__builtin_ia32_storedqusi256_mask, __builtin_ia32_storedqusi128_mask,
__builtin_ia32_storedquhi256_mask, __builtin_ia32_storedquhi128_mask,
__builtin_ia32_storedquqi256_mask, __builtin_ia32_storedquqi128_mask,
__builtin_ia32_compressstoredf256_mask, __builtin_ia32_compressstoredf128_mask,
__builtin_ia32_compressstoresf256_mask, __builtin_ia32_compressstoresf128_mask,
__builtin_ia32_compressstoredi256_mask, __builtin_ia32_compressstoredi128_mask,
__builtin_ia32_compressstoresi256_mask, __builtin_ia32_compressstoresi128_mask,
__builtin_ia32_expandloaddf256_mask, __builtin_ia32_expandloaddf128_mask,
__builtin_ia32_expandloadsf256_mask, __builtin_ia32_expandloadsf128_mask,
__builtin_ia32_expandloaddi256_mask, __builtin_ia32_expandloaddi128_mask,
__builtin_ia32_expandloadsi256_mask, __builtin_ia32_expandloadsi128_mask,
__builtin_ia32_expandloaddf256_maskz, __builtin_ia32_expandloaddf128_maskz,
__builtin_ia32_expandloadsf256_maskz, __builtin_ia32_expandloadsf128_maskz,
__builtin_ia32_expandloaddi256_maskz, __builtin_ia32_expandloaddi128_maskz,
__builtin_ia32_expandloadsi256_maskz, __builtin_ia32_expandloadsi128_maskz,
__builtin_ia32_pmovqd256mem_mask, __builtin_ia32_pmovqd128mem_mask,
__builtin_ia32_pmovsqd256mem_mask, __builtin_ia32_pmovsqd128mem_mask,
__builtin_ia32_pmovusqd256mem_mask, __builtin_ia32_pmovusqd128mem_mask,
__builtin_ia32_pmovqw256mem_mask, __builtin_ia32_pmovqw128mem_mask,
__builtin_ia32_pmovsqw256mem_mask, __builtin_ia32_pmovsqw128mem_mask,
__builtin_ia32_pmovusqw256mem_mask, __builtin_ia32_pmovusqw128mem_mask,
__builtin_ia32_pmovqb256mem_mask, __builtin_ia32_pmovqb128mem_mask,
__builtin_ia32_pmovsqb256mem_mask, __builtin_ia32_pmovsqb128mem_mask,
__builtin_ia32_pmovusqb256mem_mask, __builtin_ia32_pmovusqb128mem_mask,
__builtin_ia32_pmovdb256mem_mask, __builtin_ia32_pmovdb128mem_mask,
__builtin_ia32_pmovsdb256mem_mask, __builtin_ia32_pmovsdb128mem_mask,
__builtin_ia32_pmovusdb256mem_mask, __builtin_ia32_pmovusdb128mem_mask,
__builtin_ia32_pmovdw256mem_mask, __builtin_ia32_pmovdw128mem_mask,
__builtin_ia32_pmovsdw256mem_mask, __builtin_ia32_pmovsdw128mem_mask,
__builtin_ia32_pmovusdw256mem_mask, __builtin_ia32_pmovusdw128mem_mask,
__builtin_ia32_palignr256_mask, __builtin_ia32_palignr128_mask,
__builtin_ia32_movdqa64_256_mask, __builtin_ia32_movdqa64_128_mask,
__builtin_ia32_movdqa32_256_mask, __builtin_ia32_movdqa32_128_mask,
__builtin_ia32_movapd256_mask, __builtin_ia32_movapd128_mask,
__builtin_ia32_movaps256_mask, __builtin_ia32_movaps128_mask,
__builtin_ia32_movdquhi256_mask, __builtin_ia32_movdquhi128_mask,
__builtin_ia32_movdquqi256_mask, __builtin_ia32_movdquqi128_mask,
__builtin_ia32_minps_mask, __builtin_ia32_maxps_mask,
__builtin_ia32_minpd_mask, __builtin_ia32_maxpd_mask,
__builtin_ia32_maxpd256_mask, __builtin_ia32_maxps256_mask,
__builtin_ia32_minpd256_mask, __builtin_ia32_minps256_mask,
__builtin_ia32_mulps_mask, __builtin_ia32_divps_mask,
__builtin_ia32_mulpd_mask, __builtin_ia32_divpd_mask,
__builtin_ia32_divpd256_mask, __builtin_ia32_divps256_mask,
__builtin_ia32_mulpd256_mask, __builtin_ia32_mulps256_mask,
__builtin_ia32_addpd128_mask, __builtin_ia32_addpd256_mask,
__builtin_ia32_addps128_mask, __builtin_ia32_addps256_mask,
__builtin_ia32_subpd128_mask, __builtin_ia32_subpd256_mask,
__builtin_ia32_subps128_mask, __builtin_ia32_subps256_mask,
__builtin_ia32_xorpd256_mask, __builtin_ia32_xorpd128_mask,
__builtin_ia32_xorps256_mask, __builtin_ia32_xorps128_mask,
__builtin_ia32_orpd256_mask, __builtin_ia32_orpd128_mask,
__builtin_ia32_orps256_mask, __builtin_ia32_orps128_mask,
__builtin_ia32_broadcastf32x2_256_mask, __builtin_ia32_broadcasti32x2_256_mask,
__builtin_ia32_broadcasti32x2_128_mask, __builtin_ia32_broadcastf64x2_256_mask,
__builtin_ia32_broadcasti64x2_256_mask, __builtin_ia32_broadcastf32x4_256_mask,
__builtin_ia32_broadcasti32x4_256_mask, __builtin_ia32_extractf32x4_256_mask,
__builtin_ia32_extracti32x4_256_mask, __builtin_ia32_dbpsadbw256_mask,
__builtin_ia32_dbpsadbw128_mask, __builtin_ia32_cvttpd2qq256_mask,
__builtin_ia32_cvttpd2qq128_mask, __builtin_ia32_cvttpd2uqq256_mask,
__builtin_ia32_cvttpd2uqq128_mask, __builtin_ia32_cvtpd2qq256_mask,
__builtin_ia32_cvtpd2qq128_mask, __builtin_ia32_cvtpd2uqq256_mask,
__builtin_ia32_cvtpd2uqq128_mask, __builtin_ia32_cvtpd2udq256_mask,
__builtin_ia32_cvtpd2udq128_mask, __builtin_ia32_cvttps2qq256_mask,
__builtin_ia32_cvttps2qq128_mask, __builtin_ia32_cvttps2uqq256_mask,
__builtin_ia32_cvttps2uqq128_mask, __builtin_ia32_cvttps2dq256_mask,
__builtin_ia32_cvttps2dq128_mask, __builtin_ia32_cvttps2udq256_mask,
__builtin_ia32_cvttps2udq128_mask, __builtin_ia32_cvttpd2dq256_mask,
__builtin_ia32_cvttpd2dq128_mask, __builtin_ia32_cvttpd2udq256_mask,
__builtin_ia32_cvttpd2udq128_mask, __builtin_ia32_cvtpd2dq256_mask,
__builtin_ia32_cvtpd2dq128_mask, __builtin_ia32_cvtdq2pd256_mask,
__builtin_ia32_cvtdq2pd128_mask, __builtin_ia32_cvtudq2pd256_mask,
__builtin_ia32_cvtudq2pd128_mask, __builtin_ia32_cvtdq2ps256_mask,
__builtin_ia32_cvtdq2ps128_mask, __builtin_ia32_cvtudq2ps256_mask,
__builtin_ia32_cvtudq2ps128_mask, __builtin_ia32_cvtps2pd256_mask,
__builtin_ia32_cvtps2pd128_mask, __builtin_ia32_pbroadcastb256_mask,
__builtin_ia32_pbroadcastb256_gpr_mask, __builtin_ia32_pbroadcastb128_mask,
__builtin_ia32_pbroadcastb128_gpr_mask, __builtin_ia32_pbroadcastw256_mask,
__builtin_ia32_pbroadcastw256_gpr_mask, __builtin_ia32_pbroadcastw128_mask,
__builtin_ia32_pbroadcastw128_gpr_mask, __builtin_ia32_pbroadcastd256_mask,
__builtin_ia32_pbroadcastd256_gpr_mask, __builtin_ia32_pbroadcastd128_mask,
__builtin_ia32_pbroadcastd128_gpr_mask, __builtin_ia32_pbroadcastq256_mask,
__builtin_ia32_pbroadcastq256_gpr_mask, __builtin_ia32_pbroadcastq256_mem_mask,
__builtin_ia32_pbroadcastq128_mask, __builtin_ia32_pbroadcastq128_gpr_mask,
__builtin_ia32_pbroadcastq128_mem_mask, __builtin_ia32_broadcastss256_mask,
__builtin_ia32_broadcastss128_mask, __builtin_ia32_broadcastsd256_mask,
__builtin_ia32_extractf64x2_256_mask, __builtin_ia32_extracti64x2_256_mask,
__builtin_ia32_insertf32x4_256_mask, __builtin_ia32_inserti32x4_256_mask,
__builtin_ia32_pmovsxbw256_mask, __builtin_ia32_pmovsxbw128_mask,
__builtin_ia32_pmovsxbd256_mask, __builtin_ia32_pmovsxbd128_mask,
__builtin_ia32_pmovsxbq256_mask, __builtin_ia32_pmovsxbq128_mask,
__builtin_ia32_pmovsxwd256_mask, __builtin_ia32_pmovsxwd128_mask,
__builtin_ia32_pmovsxwq256_mask, __builtin_ia32_pmovsxwq128_mask,
__builtin_ia32_pmovsxdq256_mask, __builtin_ia32_pmovsxdq128_mask,
__builtin_ia32_pmovzxbw256_mask, __builtin_ia32_pmovzxbw128_mask,
__builtin_ia32_pmovzxbd256_mask, __builtin_ia32_pmovzxbd128_mask,
__builtin_ia32_pmovzxbq256_mask, __builtin_ia32_pmovzxbq128_mask,
__builtin_ia32_pmovzxwd256_mask, __builtin_ia32_pmovzxwd128_mask,
__builtin_ia32_pmovzxwq256_mask, __builtin_ia32_pmovzxwq128_mask,
__builtin_ia32_pmovzxdq256_mask, __builtin_ia32_pmovzxdq128_mask,
__builtin_ia32_reducepd256_mask, __builtin_ia32_reducepd128_mask,
__builtin_ia32_reduceps256_mask, __builtin_ia32_reduceps128_mask,
__builtin_ia32_reducesd, __builtin_ia32_reducess,
__builtin_ia32_permvarhi256_mask, __builtin_ia32_permvarhi128_mask,
__builtin_ia32_vpermt2varhi256_mask, __builtin_ia32_vpermt2varhi256_maskz,
__builtin_ia32_vpermt2varhi128_mask, __builtin_ia32_vpermt2varhi128_maskz,
__builtin_ia32_vpermi2varhi256_mask, __builtin_ia32_vpermi2varhi128_mask,
__builtin_ia32_rcp14pd256_mask, __builtin_ia32_rcp14pd128_mask,
__builtin_ia32_rcp14ps256_mask, __builtin_ia32_rcp14ps128_mask,
__builtin_ia32_rsqrt14pd256_mask, __builtin_ia32_rsqrt14pd128_mask,
__builtin_ia32_rsqrt14ps256_mask, __builtin_ia32_rsqrt14ps128_mask,
__builtin_ia32_sqrtpd256_mask, __builtin_ia32_sqrtpd128_mask,
__builtin_ia32_sqrtps256_mask, __builtin_ia32_sqrtps128_mask,
__builtin_ia32_paddb128_mask, __builtin_ia32_paddw128_mask,
__builtin_ia32_paddd128_mask, __builtin_ia32_paddq128_mask,
__builtin_ia32_psubb128_mask, __builtin_ia32_psubw128_mask,
__builtin_ia32_psubd128_mask, __builtin_ia32_psubq128_mask,
__builtin_ia32_paddsb128_mask, __builtin_ia32_paddsw128_mask,
__builtin_ia32_psubsb128_mask, __builtin_ia32_psubsw128_mask,
__builtin_ia32_paddusb128_mask, __builtin_ia32_paddusw128_mask,
__builtin_ia32_psubusb128_mask, __builtin_ia32_psubusw128_mask,
__builtin_ia32_paddb256_mask, __builtin_ia32_paddw256_mask,
__builtin_ia32_paddd256_mask, __builtin_ia32_paddq256_mask,
__builtin_ia32_paddsb256_mask, __builtin_ia32_paddsw256_mask,
__builtin_ia32_paddusb256_mask, __builtin_ia32_paddusw256_mask,
__builtin_ia32_psubb256_mask, __builtin_ia32_psubw256_mask,
__builtin_ia32_psubd256_mask, __builtin_ia32_psubq256_mask,
__builtin_ia32_psubsb256_mask, __builtin_ia32_psubsw256_mask,
__builtin_ia32_psubusb256_mask, __builtin_ia32_psubusw256_mask,
__builtin_ia32_shuf_f64x2_256_mask, __builtin_ia32_shuf_i64x2_256_mask,
__builtin_ia32_shuf_i32x4_256_mask, __builtin_ia32_shuf_f32x4_256_mask,
__builtin_ia32_pmovwb128_mask, __builtin_ia32_pmovwb256_mask,
__builtin_ia32_pmovswb128_mask, __builtin_ia32_pmovswb256_mask,
__builtin_ia32_pmovuswb128_mask, __builtin_ia32_pmovuswb256_mask,
__builtin_ia32_pmovdb128_mask, __builtin_ia32_pmovdb256_mask,
__builtin_ia32_pmovsdb128_mask, __builtin_ia32_pmovsdb256_mask,
__builtin_ia32_pmovusdb128_mask, __builtin_ia32_pmovusdb256_mask,
__builtin_ia32_pmovdw128_mask, __builtin_ia32_pmovdw256_mask,
__builtin_ia32_pmovsdw128_mask, __builtin_ia32_pmovsdw256_mask,
__builtin_ia32_pmovusdw128_mask, __builtin_ia32_pmovusdw256_mask,
__builtin_ia32_pmovqb128_mask, __builtin_ia32_pmovqb256_mask,
__builtin_ia32_pmovsqb128_mask, __builtin_ia32_pmovsqb256_mask,
__builtin_ia32_pmovusqb128_mask, __builtin_ia32_pmovusqb256_mask,
__builtin_ia32_pmovqw128_mask, __builtin_ia32_pmovqw256_mask,
__builtin_ia32_pmovsqw128_mask, __builtin_ia32_pmovsqw256_mask,
__builtin_ia32_pmovusqw128_mask, __builtin_ia32_pmovusqw256_mask,
__builtin_ia32_pmovqd128_mask, __builtin_ia32_pmovqd256_mask,
__builtin_ia32_pmovsqd128_mask, __builtin_ia32_pmovsqd256_mask,
__builtin_ia32_pmovusqd128_mask, __builtin_ia32_pmovusqd256_mask,
__builtin_ia32_rangepd256_mask, __builtin_ia32_rangepd128_mask,
__builtin_ia32_rangeps256_mask, __builtin_ia32_rangeps128_mask,
__builtin_ia32_getexpps256_mask, __builtin_ia32_getexppd256_mask,
__builtin_ia32_getexpps128_mask, __builtin_ia32_getexppd128_mask,
__builtin_ia32_fixupimmpd256, __builtin_ia32_fixupimmpd256_mask,
__builtin_ia32_fixupimmpd256_maskz, __builtin_ia32_fixupimmps256,
__builtin_ia32_fixupimmps256_mask, __builtin_ia32_fixupimmps256_maskz,
__builtin_ia32_fixupimmpd128, __builtin_ia32_fixupimmpd128_mask,
__builtin_ia32_fixupimmpd128_maskz, __builtin_ia32_fixupimmps128,
__builtin_ia32_fixupimmps128_mask, __builtin_ia32_fixupimmps128_maskz,
__builtin_ia32_pabsq256_mask, __builtin_ia32_pabsq128_mask,
__builtin_ia32_pabsd256_mask, __builtin_ia32_pabsd128_mask,
__builtin_ia32_pmulhrsw256_mask, __builtin_ia32_pmulhrsw128_mask,
__builtin_ia32_pmulhuw128_mask, __builtin_ia32_pmulhuw256_mask,
__builtin_ia32_pmulhw256_mask, __builtin_ia32_pmulhw128_mask,
__builtin_ia32_pmullw256_mask, __builtin_ia32_pmullw128_mask,
__builtin_ia32_pmullq256_mask, __builtin_ia32_pmullq128_mask,
__builtin_ia32_andpd256_mask, __builtin_ia32_andpd128_mask,
__builtin_ia32_andps256_mask, __builtin_ia32_andps128_mask,
__builtin_ia32_andnpd256_mask, __builtin_ia32_andnpd128_mask,
__builtin_ia32_andnps256_mask, __builtin_ia32_andnps128_mask,
__builtin_ia32_psllwi128_mask, __builtin_ia32_pslldi128_mask,
__builtin_ia32_psllqi128_mask, __builtin_ia32_psllw128_mask,
__builtin_ia32_pslld128_mask, __builtin_ia32_psllq128_mask,
__builtin_ia32_psllwi256_mask, __builtin_ia32_psllw256_mask,
__builtin_ia32_pslldi256_mask, __builtin_ia32_pslld256_mask,
__builtin_ia32_psllqi256_mask, __builtin_ia32_psllq256_mask,
__builtin_ia32_psradi128_mask, __builtin_ia32_psrad128_mask,
__builtin_ia32_psradi256_mask, __builtin_ia32_psrad256_mask,
__builtin_ia32_psraqi128_mask, __builtin_ia32_psraq128_mask,
__builtin_ia32_psraqi256_mask, __builtin_ia32_psraq256_mask,
__builtin_ia32_pandd256_mask, __builtin_ia32_pandd128_mask,
__builtin_ia32_psrldi128_mask, __builtin_ia32_psrld128_mask,
__builtin_ia32_psrldi256_mask, __builtin_ia32_psrld256_mask,
__builtin_ia32_psrlqi128_mask, __builtin_ia32_psrlq128_mask,
__builtin_ia32_psrlqi256_mask, __builtin_ia32_psrlq256_mask,
__builtin_ia32_pandq256_mask, __builtin_ia32_pandq128_mask,
__builtin_ia32_pandnd256_mask, __builtin_ia32_pandnd128_mask,
__builtin_ia32_pandnq256_mask, __builtin_ia32_pandnq128_mask,
__builtin_ia32_pord256_mask, __builtin_ia32_pord128_mask,
__builtin_ia32_porq256_mask, __builtin_ia32_porq128_mask,
__builtin_ia32_pxord256_mask, __builtin_ia32_pxord128_mask,
__builtin_ia32_pxorq256_mask, __builtin_ia32_pxorq128_mask,
__builtin_ia32_packsswb256_mask, __builtin_ia32_packsswb128_mask,
__builtin_ia32_packuswb256_mask, __builtin_ia32_packuswb128_mask,
__builtin_ia32_rndscaleps_256_mask, __builtin_ia32_rndscalepd_256_mask,
__builtin_ia32_rndscaleps_128_mask, __builtin_ia32_rndscalepd_128_mask,
__builtin_ia32_pternlogq256_mask, __builtin_ia32_pternlogq256_maskz,
__builtin_ia32_pternlogd256_mask, __builtin_ia32_pternlogd256_maskz,
__builtin_ia32_pternlogq128_mask, __builtin_ia32_pternlogq128_maskz,
__builtin_ia32_pternlogd128_mask, __builtin_ia32_pternlogd128_maskz,
__builtin_ia32_scalefpd256_mask, __builtin_ia32_scalefps256_mask,
__builtin_ia32_scalefpd128_mask, __builtin_ia32_scalefps128_mask,
__builtin_ia32_vfmaddpd256_mask, __builtin_ia32_vfmaddpd256_mask3,
__builtin_ia32_vfmaddpd256_maskz, __builtin_ia32_vfmaddpd128_mask,
__builtin_ia32_vfmaddpd128_mask3, __builtin_ia32_vfmaddpd128_maskz,
__builtin_ia32_vfmaddps256_mask, __builtin_ia32_vfmaddps256_mask3,
__builtin_ia32_vfmaddps256_maskz, __builtin_ia32_vfmaddps128_mask,
__builtin_ia32_vfmaddps128_mask3, __builtin_ia32_vfmaddps128_maskz,
__builtin_ia32_vfmsubpd256_mask3, __builtin_ia32_vfmsubpd128_mask3,
__builtin_ia32_vfmsubps256_mask3, __builtin_ia32_vfmsubps128_mask3,
__builtin_ia32_vfnmaddpd256_mask, __builtin_ia32_vfnmaddpd128_mask,
__builtin_ia32_vfnmaddps256_mask, __builtin_ia32_vfnmaddps128_mask,
__builtin_ia32_vfnmsubpd256_mask, __builtin_ia32_vfnmsubpd256_mask3,
__builtin_ia32_vfnmsubpd128_mask, __builtin_ia32_vfnmsubpd128_mask3,
__builtin_ia32_vfnmsubps256_mask, __builtin_ia32_vfnmsubps256_mask3,
__builtin_ia32_vfnmsubps128_mask, __builtin_ia32_vfnmsubps128_mask3,
__builtin_ia32_vfmaddsubpd256_mask, __builtin_ia32_vfmaddsubpd256_mask3,
__builtin_ia32_vfmaddsubpd256_maskz, __builtin_ia32_vfmaddsubpd128_mask,
__builtin_ia32_vfmaddsubpd128_mask3, __builtin_ia32_vfmaddsubpd128_maskz,
__builtin_ia32_vfmaddsubps256_mask, __builtin_ia32_vfmaddsubps256_mask3,
__builtin_ia32_vfmaddsubps256_maskz, __builtin_ia32_vfmaddsubps128_mask,
__builtin_ia32_vfmaddsubps128_mask3, __builtin_ia32_vfmaddsubps128_maskz,
__builtin_ia32_vfmsubaddpd256_mask3, __builtin_ia32_vfmsubaddpd128_mask3,
__builtin_ia32_vfmsubaddps256_mask3, __builtin_ia32_vfmsubaddps128_mask3,
__builtin_ia32_insertf64x2_256_mask, __builtin_ia32_inserti64x2_256_mask,
__builtin_ia32_psrav16hi_mask, __builtin_ia32_psrav8hi_mask,
__builtin_ia32_pmaddubsw256_mask, __builtin_ia32_pmaddubsw128_mask,
__builtin_ia32_pmaddwd256_mask, __builtin_ia32_pmaddwd128_mask,
__builtin_ia32_psrlv16hi_mask, __builtin_ia32_psrlv8hi_mask,
__builtin_ia32_cvtps2dq256_mask, __builtin_ia32_cvtps2dq128_mask,
__builtin_ia32_cvtps2udq256_mask, __builtin_ia32_cvtps2udq128_mask,
__builtin_ia32_cvtps2qq256_mask, __builtin_ia32_cvtps2qq128_mask,
__builtin_ia32_cvtps2uqq256_mask, __builtin_ia32_cvtps2uqq128_mask,
__builtin_ia32_getmantps256_mask, __builtin_ia32_getmantps128_mask,
__builtin_ia32_getmantpd256_mask, __builtin_ia32_getmantpd128_mask,
__builtin_ia32_movddup256_mask, __builtin_ia32_movddup128_mask,
__builtin_ia32_movshdup256_mask, __builtin_ia32_movshdup128_mask,
__builtin_ia32_movsldup256_mask, __builtin_ia32_movsldup128_mask,
__builtin_ia32_cvtqq2ps256_mask, __builtin_ia32_cvtqq2ps128_mask,
__builtin_ia32_cvtuqq2ps256_mask, __builtin_ia32_cvtuqq2ps128_mask,
__builtin_ia32_cvtqq2pd256_mask, __builtin_ia32_cvtqq2pd128_mask,
__builtin_ia32_cvtuqq2pd256_mask, __builtin_ia32_cvtuqq2pd128_mask,
__builtin_ia32_vpermt2varq256_mask, __builtin_ia32_vpermt2varq256_maskz,
__builtin_ia32_vpermt2vard256_mask, __builtin_ia32_vpermt2vard256_maskz,
__builtin_ia32_vpermi2varq256_mask, __builtin_ia32_vpermi2vard256_mask,
__builtin_ia32_vpermt2varpd256_mask, __builtin_ia32_vpermt2varpd256_maskz,
__builtin_ia32_vpermt2varps256_mask, __builtin_ia32_vpermt2varps256_maskz,
__builtin_ia32_vpermi2varpd256_mask, __builtin_ia32_vpermi2varps256_mask,
__builtin_ia32_vpermt2varq128_mask, __builtin_ia32_vpermt2varq128_maskz,
__builtin_ia32_vpermt2vard128_mask, __builtin_ia32_vpermt2vard128_maskz,
__builtin_ia32_vpermi2varq128_mask, __builtin_ia32_vpermi2vard128_mask,
__builtin_ia32_vpermt2varpd128_mask, __builtin_ia32_vpermt2varpd128_maskz,
__builtin_ia32_vpermt2varps128_mask, __builtin_ia32_vpermt2varps128_maskz,
__builtin_ia32_vpermi2varpd128_mask, __builtin_ia32_vpermi2varps128_mask,
__builtin_ia32_pshufb256_mask, __builtin_ia32_pshufb128_mask,
__builtin_ia32_pshufhw256_mask, __builtin_ia32_pshufhw128_mask,
__builtin_ia32_pshuflw256_mask, __builtin_ia32_pshuflw128_mask,
__builtin_ia32_pshufd256_mask, __builtin_ia32_pshufd128_mask,
__builtin_ia32_shufpd256_mask, __builtin_ia32_shufpd128_mask,
__builtin_ia32_shufps256_mask, __builtin_ia32_shufps128_mask,
__builtin_ia32_prolvq256_mask, __builtin_ia32_prolvq128_mask,
__builtin_ia32_prolq256_mask, __builtin_ia32_prolq128_mask,
__builtin_ia32_prorvq256_mask, __builtin_ia32_prorvq128_mask,
__builtin_ia32_prorq256_mask, __builtin_ia32_prorq128_mask,
__builtin_ia32_psravq128_mask, __builtin_ia32_psravq256_mask,
__builtin_ia32_psllv4di_mask, __builtin_ia32_psllv2di_mask,
__builtin_ia32_psllv8si_mask, __builtin_ia32_psllv4si_mask,
__builtin_ia32_psrav8si_mask, __builtin_ia32_psrav4si_mask,
__builtin_ia32_psrlv4di_mask, __builtin_ia32_psrlv2di_mask,
__builtin_ia32_psrlv8si_mask, __builtin_ia32_psrlv4si_mask,
__builtin_ia32_psrawi256_mask, __builtin_ia32_psraw256_mask,
__builtin_ia32_psrawi128_mask, __builtin_ia32_psraw128_mask,
__builtin_ia32_psrlwi256_mask, __builtin_ia32_psrlw256_mask,
__builtin_ia32_psrlwi128_mask, __builtin_ia32_psrlw128_mask,
__builtin_ia32_prorvd256_mask, __builtin_ia32_prolvd256_mask,
__builtin_ia32_prord256_mask, __builtin_ia32_prold256_mask,
__builtin_ia32_prorvd128_mask, __builtin_ia32_prolvd128_mask,
__builtin_ia32_prord128_mask, __builtin_ia32_prold128_mask,
__builtin_ia32_fpclasspd256_mask, __builtin_ia32_fpclasspd128_mask,
__builtin_ia32_fpclasssd, __builtin_ia32_fpclassps256_mask,
__builtin_ia32_fpclassps128_mask, __builtin_ia32_fpclassss,
__builtin_ia32_cvtb2mask128, __builtin_ia32_cvtb2mask256,
__builtin_ia32_cvtw2mask128, __builtin_ia32_cvtw2mask256,
__builtin_ia32_cvtd2mask128, __builtin_ia32_cvtd2mask256,
__builtin_ia32_cvtq2mask128, __builtin_ia32_cvtq2mask256,
__builtin_ia32_cvtmask2b128, __builtin_ia32_cvtmask2b256,
__builtin_ia32_cvtmask2w128, __builtin_ia32_cvtmask2w256,
__builtin_ia32_cvtmask2d128, __builtin_ia32_cvtmask2d256,
__builtin_ia32_cvtmask2q128, __builtin_ia32_cvtmask2q256,
__builtin_ia32_pcmpeqb128_mask, __builtin_ia32_pcmpeqb256_mask,
__builtin_ia32_pcmpeqw128_mask, __builtin_ia32_pcmpeqw256_mask,
__builtin_ia32_pcmpeqd128_mask, __builtin_ia32_pcmpeqd256_mask,
__builtin_ia32_pcmpeqq128_mask, __builtin_ia32_pcmpeqq256_mask,
__builtin_ia32_pcmpgtb128_mask, __builtin_ia32_pcmpgtb256_mask,
__builtin_ia32_pcmpgtw128_mask, __builtin_ia32_pcmpgtw256_mask,
__builtin_ia32_pcmpgtd128_mask, __builtin_ia32_pcmpgtd256_mask,
__builtin_ia32_pcmpgtq128_mask, __builtin_ia32_pcmpgtq256_mask,
__builtin_ia32_ptestmb128, __builtin_ia32_ptestmb256,
__builtin_ia32_ptestmw128, __builtin_ia32_ptestmw256,
__builtin_ia32_ptestmd128, __builtin_ia32_ptestmd256,
__builtin_ia32_ptestmq128, __builtin_ia32_ptestmq256,
__builtin_ia32_ptestnmb128, __builtin_ia32_ptestnmb256,
__builtin_ia32_ptestnmw128, __builtin_ia32_ptestnmw256,
__builtin_ia32_ptestnmd128, __builtin_ia32_ptestnmd256,
__builtin_ia32_ptestnmq128, __builtin_ia32_ptestnmq256,
__builtin_ia32_broadcastmb128, __builtin_ia32_broadcastmb256,
__builtin_ia32_broadcastmw128, __builtin_ia32_broadcastmw256,
__builtin_ia32_compressdf256_mask, __builtin_ia32_compressdf128_mask,
__builtin_ia32_compresssf256_mask, __builtin_ia32_compresssf128_mask,
__builtin_ia32_compressdi256_mask, __builtin_ia32_compressdi128_mask,
__builtin_ia32_compresssi256_mask, __builtin_ia32_compresssi128_mask,
__builtin_ia32_expanddf256_mask, __builtin_ia32_expanddf128_mask,
__builtin_ia32_expandsf256_mask, __builtin_ia32_expandsf128_mask,
__builtin_ia32_expanddi256_mask, __builtin_ia32_expanddi128_mask,
__builtin_ia32_expandsi256_mask, __builtin_ia32_expandsi128_mask,
__builtin_ia32_expanddf256_maskz, __builtin_ia32_expanddf128_maskz,
__builtin_ia32_expandsf256_maskz, __builtin_ia32_expandsf128_maskz,
__builtin_ia32_expanddi256_maskz, __builtin_ia32_expanddi128_maskz,
__builtin_ia32_expandsi256_maskz, __builtin_ia32_expandsi128_maskz,
__builtin_ia32_pmaxsd256_mask, __builtin_ia32_pminsd256_mask,
__builtin_ia32_pmaxud256_mask, __builtin_ia32_pminud256_mask,
__builtin_ia32_pmaxsd128_mask, __builtin_ia32_pminsd128_mask,
__builtin_ia32_pmaxud128_mask, __builtin_ia32_pminud128_mask,
__builtin_ia32_pmaxsq256_mask, __builtin_ia32_pminsq256_mask,
__builtin_ia32_pmaxuq256_mask, __builtin_ia32_pminuq256_mask,
__builtin_ia32_pmaxsq128_mask, __builtin_ia32_pminsq128_mask,
__builtin_ia32_pmaxuq128_mask, __builtin_ia32_pminuq128_mask,
__builtin_ia32_pminsb256_mask, __builtin_ia32_pminub256_mask,
__builtin_ia32_pmaxsb256_mask, __builtin_ia32_pmaxub256_mask,
__builtin_ia32_pminsb128_mask, __builtin_ia32_pminub128_mask,
__builtin_ia32_pmaxsb128_mask, __builtin_ia32_pmaxub128_mask,
__builtin_ia32_pminsw256_mask, __builtin_ia32_pminuw256_mask,
__builtin_ia32_pmaxsw256_mask, __builtin_ia32_pmaxuw256_mask,
__builtin_ia32_pminsw128_mask, __builtin_ia32_pminuw128_mask,
__builtin_ia32_pmaxsw128_mask, __builtin_ia32_pmaxuw128_mask,
__builtin_ia32_vpconflictdi_256_mask, __builtin_ia32_vpconflictsi_256_mask,
__builtin_ia32_vplzcntq_256_mask, __builtin_ia32_vplzcntd_256_mask,
__builtin_ia32_unpckhpd256_mask, __builtin_ia32_unpckhpd128_mask,
__builtin_ia32_unpckhps256_mask, __builtin_ia32_unpckhps128_mask,
__builtin_ia32_unpcklpd256_mask, __builtin_ia32_unpcklpd128_mask,
__builtin_ia32_unpcklps256_mask, __builtin_ia32_vpconflictdi_128_mask,
__builtin_ia32_vpconflictsi_128_mask, __builtin_ia32_vplzcntq_128_mask,
__builtin_ia32_vplzcntd_128_mask, __builtin_ia32_unpcklps128_mask,
__builtin_ia32_alignd256_mask, __builtin_ia32_alignq256_mask,
__builtin_ia32_alignd128_mask, __builtin_ia32_alignq128_mask,
__builtin_ia32_vcvtps2ph256_mask, __builtin_ia32_vcvtps2ph_mask,
__builtin_ia32_vcvtph2ps_mask, __builtin_ia32_vcvtph2ps256_mask,
__builtin_ia32_punpckhdq128_mask, __builtin_ia32_punpckhdq256_mask,
__builtin_ia32_punpckhqdq128_mask, __builtin_ia32_punpckhqdq256_mask,
__builtin_ia32_punpckldq128_mask, __builtin_ia32_punpckldq256_mask,
__builtin_ia32_punpcklqdq128_mask, __builtin_ia32_punpcklqdq256_mask,
__builtin_ia32_punpckhbw128_mask, __builtin_ia32_punpckhbw256_mask,
__builtin_ia32_punpckhwd128_mask, __builtin_ia32_punpckhwd256_mask,
__builtin_ia32_punpcklbw128_mask, __builtin_ia32_punpcklbw256_mask,
__builtin_ia32_punpcklwd128_mask, __builtin_ia32_punpcklwd256_mask,
__builtin_ia32_psllv16hi_mask, __builtin_ia32_psllv8hi_mask,
__builtin_ia32_packssdw256_mask, __builtin_ia32_packssdw128_mask,
__builtin_ia32_packusdw256_mask, __builtin_ia32_packusdw128_mask,
__builtin_ia32_pavgb256_mask, __builtin_ia32_pavgw256_mask,
__builtin_ia32_pavgb128_mask, __builtin_ia32_pavgw128_mask,
__builtin_ia32_permvarsf256_mask, __builtin_ia32_permvardf256_mask,
__builtin_ia32_permdf256_mask, __builtin_ia32_pabsb256_mask,
__builtin_ia32_pabsb128_mask, __builtin_ia32_pabsw256_mask,
__builtin_ia32_pabsw128_mask, __builtin_ia32_vpermilvarpd_mask,
__builtin_ia32_vpermilvarps_mask, __builtin_ia32_vpermilvarpd256_mask,
__builtin_ia32_vpermilvarps256_mask, __builtin_ia32_vpermilpd_mask,
__builtin_ia32_vpermilps_mask, __builtin_ia32_vpermilpd256_mask,
__builtin_ia32_vpermilps256_mask, __builtin_ia32_blendmq_256_mask,
__builtin_ia32_blendmd_256_mask, __builtin_ia32_blendmpd_256_mask,
__builtin_ia32_blendmps_256_mask, __builtin_ia32_blendmq_128_mask,
__builtin_ia32_blendmd_128_mask, __builtin_ia32_blendmpd_128_mask,
__builtin_ia32_blendmps_128_mask, __builtin_ia32_blendmw_256_mask,
__builtin_ia32_blendmb_256_mask, __builtin_ia32_blendmw_128_mask,
__builtin_ia32_blendmb_128_mask, __builtin_ia32_pmulld256_mask,
__builtin_ia32_pmulld128_mask, __builtin_ia32_pmuludq256_mask,
__builtin_ia32_pmuldq256_mask, __builtin_ia32_pmuldq128_mask,
__builtin_ia32_pmuludq128_mask, __builtin_ia32_cvtpd2ps256_mask,
__builtin_ia32_cvtpd2ps_mask, __builtin_ia32_permvarsi256_mask,
__builtin_ia32_permvardi256_mask, __builtin_ia32_permdi256_mask,
__builtin_ia32_cmpq256_mask, __builtin_ia32_cmpd256_mask,
__builtin_ia32_ucmpq256_mask, __builtin_ia32_ucmpd256_mask,
__builtin_ia32_cmpb256_mask, __builtin_ia32_cmpw256_mask,
__builtin_ia32_ucmpb256_mask, __builtin_ia32_ucmpw256_mask,
__builtin_ia32_cmppd256_mask, __builtin_ia32_cmpps256_mask,
__builtin_ia32_cmpq128_mask, __builtin_ia32_cmpd128_mask,
__builtin_ia32_ucmpq128_mask, __builtin_ia32_ucmpd128_mask,
__builtin_ia32_cmpb128_mask, __builtin_ia32_cmpw128_mask,
__builtin_ia32_ucmpb128_mask, __builtin_ia32_ucmpw128_mask,
__builtin_ia32_cmppd128_mask, __builtin_ia32_cmpps128_mask,
__builtin_ia32_broadcastf32x2_512_mask, __builtin_ia32_broadcasti32x2_512_mask,
__builtin_ia32_broadcastf64x2_512_mask, __builtin_ia32_broadcasti64x2_512_mask,
__builtin_ia32_broadcastf32x8_512_mask, __builtin_ia32_broadcasti32x8_512_mask,
__builtin_ia32_extractf64x2_512_mask, __builtin_ia32_extractf32x8_mask,
__builtin_ia32_extracti64x2_512_mask, __builtin_ia32_extracti32x8_mask,
__builtin_ia32_reducepd512_mask, __builtin_ia32_reduceps512_mask,
__builtin_ia32_pmullq512_mask, __builtin_ia32_xorpd512_mask,
__builtin_ia32_xorps512_mask, __builtin_ia32_orpd512_mask,
__builtin_ia32_orps512_mask, __builtin_ia32_andpd512_mask,
__builtin_ia32_andps512_mask, __builtin_ia32_andnpd512_mask,
__builtin_ia32_andnps512_mask, __builtin_ia32_insertf32x8_mask,
__builtin_ia32_inserti32x8_mask, __builtin_ia32_insertf64x2_512_mask,
__builtin_ia32_inserti64x2_512_mask, __builtin_ia32_fpclasspd512_mask,
__builtin_ia32_fpclassps512_mask, __builtin_ia32_cvtd2mask512,
__builtin_ia32_cvtq2mask512, __builtin_ia32_cvtmask2d512,
__builtin_ia32_cvtmask2q512, __builtin_ia32_kunpcksi,
__builtin_ia32_kunpckdi, __builtin_ia32_packusdw512_mask,
__builtin_ia32_pslldq512, __builtin_ia32_psrldq512,
__builtin_ia32_packssdw512_mask, __builtin_ia32_palignr512,
__builtin_ia32_palignr512_mask, __builtin_ia32_movdquhi512_mask,
__builtin_ia32_movdquqi512_mask, __builtin_ia32_psadbw512,
__builtin_ia32_dbpsadbw512_mask, __builtin_ia32_pbroadcastb512_mask,
__builtin_ia32_pbroadcastb512_gpr_mask, __builtin_ia32_pbroadcastw512_mask,
__builtin_ia32_pbroadcastw512_gpr_mask, __builtin_ia32_pmovsxbw512_mask,
__builtin_ia32_pmovzxbw512_mask, __builtin_ia32_permvarhi512_mask,
__builtin_ia32_vpermt2varhi512_mask, __builtin_ia32_vpermt2varhi512_maskz,
__builtin_ia32_vpermi2varhi512_mask, __builtin_ia32_pavgb512_mask,
__builtin_ia32_pavgw512_mask, __builtin_ia32_paddb512_mask,
__builtin_ia32_psubb512_mask, __builtin_ia32_psubsb512_mask,
__builtin_ia32_paddsb512_mask, __builtin_ia32_psubusb512_mask,
__builtin_ia32_paddusb512_mask, __builtin_ia32_psubw512_mask,
__builtin_ia32_paddw512_mask, __builtin_ia32_psubsw512_mask,
__builtin_ia32_paddsw512_mask, __builtin_ia32_psubusw512_mask,
__builtin_ia32_paddusw512_mask, __builtin_ia32_pmaxuw512_mask,
__builtin_ia32_pmaxsw512_mask, __builtin_ia32_pminuw512_mask,
__builtin_ia32_pminsw512_mask, __builtin_ia32_pmaxub512_mask,
__builtin_ia32_pmaxsb512_mask, __builtin_ia32_pminub512_mask,
__builtin_ia32_pminsb512_mask, __builtin_ia32_pmovwb512_mask,
__builtin_ia32_pmovswb512_mask, __builtin_ia32_pmovuswb512_mask,
__builtin_ia32_pmulhrsw512_mask, __builtin_ia32_pmulhuw512_mask,
__builtin_ia32_pmulhw512_mask, __builtin_ia32_pmullw512_mask,
__builtin_ia32_psllwi512_mask, __builtin_ia32_psllw512_mask,
__builtin_ia32_packsswb512_mask, __builtin_ia32_packuswb512_mask,
__builtin_ia32_psrav32hi_mask, __builtin_ia32_pmaddubsw512_mask,
__builtin_ia32_pmaddwd512_mask, __builtin_ia32_psrlv32hi_mask,
__builtin_ia32_punpckhbw512_mask, __builtin_ia32_punpckhwd512_mask,
__builtin_ia32_punpcklbw512_mask, __builtin_ia32_punpcklwd512_mask,
__builtin_ia32_pshufb512_mask, __builtin_ia32_pshufhw512_mask,
__builtin_ia32_pshuflw512_mask, __builtin_ia32_psrawi512_mask,
__builtin_ia32_psraw512_mask, __builtin_ia32_psrlwi512_mask,
__builtin_ia32_psrlw512_mask, __builtin_ia32_cvtb2mask512,
__builtin_ia32_cvtw2mask512, __builtin_ia32_cvtmask2b512,
__builtin_ia32_cvtmask2w512, __builtin_ia32_pcmpeqb512_mask,
__builtin_ia32_pcmpeqw512_mask, __builtin_ia32_pcmpgtb512_mask,
__builtin_ia32_pcmpgtw512_mask, __builtin_ia32_ptestmb512,
__builtin_ia32_ptestmw512, __builtin_ia32_ptestnmb512,
__builtin_ia32_ptestnmw512, __builtin_ia32_psllv32hi_mask,
__builtin_ia32_pabsb512_mask, __builtin_ia32_pabsw512_mask,
__builtin_ia32_blendmw_512_mask, __builtin_ia32_blendmb_512_mask,
__builtin_ia32_cmpb512_mask, __builtin_ia32_cmpw512_mask,
__builtin_ia32_ucmpb512_mask, __builtin_ia32_ucmpw512_mask,
__builtin_ia32_rangesd128_round, __builtin_ia32_rangess128_round,
__builtin_ia32_cvtpd2qq512_mask, __builtin_ia32_cvtps2qq512_mask,
__builtin_ia32_cvtpd2uqq512_mask, __builtin_ia32_cvtps2uqq512_mask,
__builtin_ia32_cvtqq2ps512_mask, __builtin_ia32_cvtuqq2ps512_mask,
__builtin_ia32_cvtqq2pd512_mask, __builtin_ia32_cvtuqq2pd512_mask,
__builtin_ia32_cvttps2qq512_mask, __builtin_ia32_cvttps2uqq512_mask,
__builtin_ia32_cvttpd2qq512_mask, __builtin_ia32_cvttpd2uqq512_mask,
__builtin_ia32_rangeps512_mask, __builtin_ia32_rangepd512_mask.
(ix86_expand_args_builtin): Handle HI_FTYPE_V16QI, SI_FTYPE_V32QI,
DI_FTYPE_V64QI, V16QI_FTYPE_HI, V32QI_FTYPE_SI, V64QI_FTYPE_DI,
V8HI_FTYPE_QI, V16HI_FTYPE_HI, V32HI_FTYPE_SI, V4SI_FTYPE_QI,
V8SI_FTYPE_QI, V4SI_FTYPE_HI, V8SI_FTYPE_HI, QI_FTYPE_V8HI,
HI_FTYPE_V16HI, SI_FTYPE_V32HI, QI_FTYPE_V4SI, QI_FTYPE_V8SI,
HI_FTYPE_V16SI, QI_FTYPE_V2DI, QI_FTYPE_V4DI, QI_FTYPE_V8DI,
V2DI_FTYPE_QI, V4DI_FTYPE_QI, V8DI_FTYPE_V64QI_V64QI,
SI_FTYPE_SI_SI,DI_FTYPE_DI_DI, V8DI_FTYPE_V8DI_INT_CONVERT,
QI_FTYPE_V4SF_INT, QI_FTYPE_V2DF_INT,
V8SF_FTYPE_V4SF_V8SF_QI, V4DF_FTYPE_V2DF_V4DF_QI,
V8SI_FTYPE_V4SI_V8SI_QI, V8SI_FTYPE_SI_V8SI_QI,
V4SI_FTYPE_V4SI_V4SI_QI, V4SI_FTYPE_SI_V4SI_QI,
V4DI_FTYPE_V2DI_V4DI_QI, V4DI_FTYPE_DI_V4DI_QI,
V2DI_FTYPE_V2DI_V2DI_QI, V2DI_FTYPE_DI_V2DI_QI,
V64QI_FTYPE_V64QI_V64QI_DI, V64QI_FTYPE_V16QI_V64QI_DI,
V64QI_FTYPE_QI_V64QI_DI, V32QI_FTYPE_V32QI_V32QI_SI,
V32QI_FTYPE_V16QI_V32QI_SI, V32QI_FTYPE_QI_V32QI_SI,
V16QI_FTYPE_V16QI_V16QI_HI, V16QI_FTYPE_QI_V16QI_HI,
V32HI_FTYPE_V8HI_V32HI_SI, V32HI_FTYPE_HI_V32HI_SI,
V16HI_FTYPE_V8HI_V16HI_HI, V16HI_FTYPE_HI_V16HI_HI,
V8HI_FTYPE_V8HI_V8HI_QI, V8HI_FTYPE_HI_V8HI_QI,
V8SF_FTYPE_V8HI_V8SF_QI, V4SF_FTYPE_V8HI_V4SF_QI,
V8SI_FTYPE_V8SF_V8SI_QI, V4SI_FTYPE_V4SF_V4SI_QI,
V8DI_FTYPE_V8SF_V8DI_QI, V4DI_FTYPE_V4SF_V4DI_QI,
V2DI_FTYPE_V4SF_V2DI_QI, V8SF_FTYPE_V8DI_V8SF_QI,
V4SF_FTYPE_V4DI_V4SF_QI, V4SF_FTYPE_V2DI_V4SF_QI,
V8DF_FTYPE_V8DI_V8DF_QI, V4DF_FTYPE_V4DI_V4DF_QI,
V2DF_FTYPE_V2DI_V2DF_QI, V16QI_FTYPE_V8HI_V16QI_QI,
V16QI_FTYPE_V16HI_V16QI_HI, V16QI_FTYPE_V4SI_V16QI_QI,
V16QI_FTYPE_V8SI_V16QI_QI, V8HI_FTYPE_V4SI_V8HI_QI,
V8HI_FTYPE_V8SI_V8HI_QI, V16QI_FTYPE_V2DI_V16QI_QI,
V16QI_FTYPE_V4DI_V16QI_QI, V8HI_FTYPE_V2DI_V8HI_QI,
V8HI_FTYPE_V4DI_V8HI_QI, V4SI_FTYPE_V2DI_V4SI_QI,
V4SI_FTYPE_V4DI_V4SI_QI, V32QI_FTYPE_V32HI_V32QI_SI,
HI_FTYPE_V16QI_V16QI_HI, SI_FTYPE_V32QI_V32QI_SI,
DI_FTYPE_V64QI_V64QI_DI, QI_FTYPE_V8HI_V8HI_QI,
HI_FTYPE_V16HI_V16HI_HI, SI_FTYPE_V32HI_V32HI_SI,
QI_FTYPE_V4SI_V4SI_QI, QI_FTYPE_V8SI_V8SI_QI,
QI_FTYPE_V2DI_V2DI_QI, QI_FTYPE_V4DI_V4DI_QI,
V4SF_FTYPE_V2DF_V4SF_QI, V4SF_FTYPE_V4DF_V4SF_QI,
V2DI_FTYPE_V4SI_V2DI_QI, V2DI_FTYPE_V8HI_V2DI_QI,
V2DI_FTYPE_V16QI_V2DI_QI, V4DI_FTYPE_V4DI_V4DI_QI,
V4DI_FTYPE_V4SI_V4DI_QI, V4DI_FTYPE_V8HI_V4DI_QI,
V4DI_FTYPE_V16QI_V4DI_QI, V8DI_FTYPE_V8DF_V8DI_QI,
V4DI_FTYPE_V4DF_V4DI_QI, V2DI_FTYPE_V2DF_V2DI_QI,
V4SI_FTYPE_V4DF_V4SI_QI, V4SI_FTYPE_V2DF_V4SI_QI,
V4SI_FTYPE_V8HI_V4SI_QI, V4SI_FTYPE_V16QI_V4SI_QI,
V8SI_FTYPE_V8SI_V8SI_V8SI, V8SF_FTYPE_V8SF_V8SF_QI,
V8SF_FTYPE_V8SI_V8SF_QI, V4DF_FTYPE_V4DF_V4DF_QI,
V4SF_FTYPE_V4SF_V4SF_QI, V2DF_FTYPE_V2DF_V2DF_QI,
V2DF_FTYPE_V4SF_V2DF_QI, V2DF_FTYPE_V4SI_V2DF_QI,
V4SF_FTYPE_V4SI_V4SF_QI, V4DF_FTYPE_V4SF_V4DF_QI,
V4DF_FTYPE_V4SI_V4DF_QI, V8SI_FTYPE_V8SI_V8SI_QI,
V8SI_FTYPE_V8HI_V8SI_QI, V8SI_FTYPE_V16QI_V8SI_QI,
V16SF_FTYPE_V8SF_V16SF_HI, V16SI_FTYPE_V8SI_V16SI_HI,
V16HI_FTYPE_V16HI_V16HI_HI, V8HI_FTYPE_V16QI_V8HI_QI,
V16HI_FTYPE_V16QI_V16HI_HI, V32HI_FTYPE_V32HI_V32HI_SI,
V32HI_FTYPE_V32QI_V32HI_SI, V8DI_FTYPE_V8DI_V8DI_INT_CONVERT,
V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT, QI_FTYPE_V8DF_INT_QI,
QI_FTYPE_V4DF_INT_QI, QI_FTYPE_V2DF_INT_QI,
HI_FTYPE_V16SF_INT_HI, QI_FTYPE_V8SF_INT_QI,
QI_FTYPE_V4SF_INT_QI, V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT,
V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT, V32QI_FTYPE_V32QI_V32QI_V32QI_SI,
V32HI_FTYPE_V32HI_V32HI_V32HI_SI, V32HI_FTYPE_V64QI_V64QI_V32HI_SI,
V16SI_FTYPE_V32HI_V32HI_V16SI_HI, V64QI_FTYPE_V64QI_V64QI_V64QI_DI,
V32HI_FTYPE_V32HI_V8HI_V32HI_SI, V16HI_FTYPE_V16HI_V8HI_V16HI_HI,
V8SI_FTYPE_V8SI_V4SI_V8SI_QI, V4DI_FTYPE_V4DI_V2DI_V4DI_QI,
V64QI_FTYPE_V32HI_V32HI_V64QI_DI, V32QI_FTYPE_V16HI_V16HI_V32QI_SI,
V16QI_FTYPE_V8HI_V8HI_V16QI_HI, V32HI_FTYPE_V16SI_V16SI_V32HI_SI,
V16HI_FTYPE_V8SI_V8SI_V16HI_HI, V8HI_FTYPE_V4SI_V4SI_V8HI_QI,
V4DF_FTYPE_V4DF_V4DI_V4DF_QI, V8SF_FTYPE_V8SF_V8SI_V8SF_QI,
V4SF_FTYPE_V4SF_V4SI_V4SF_QI, V2DF_FTYPE_V2DF_V2DI_V2DF_QI,
V2DI_FTYPE_V4SI_V4SI_V2DI_QI, V4DI_FTYPE_V8SI_V8SI_V4DI_QI,
V4DF_FTYPE_V4DI_V4DF_V4DF_QI, V8SF_FTYPE_V8SI_V8SF_V8SF_QI,
V2DF_FTYPE_V2DI_V2DF_V2DF_QI, V4SF_FTYPE_V4SI_V4SF_V4SF_QI,
V8HI_FTYPE_V8HI_V8HI_V8HI_QI, V8SI_FTYPE_V8SI_V8SI_V8SI_QI,
V4SI_FTYPE_V4SI_V4SI_V4SI_QI, V8SF_FTYPE_V8SF_V8SF_V8SF_QI,
V16QI_FTYPE_V16QI_V16QI_V16QI_HI, V16HI_FTYPE_V16HI_V16HI_V16HI_HI,
V2DI_FTYPE_V2DI_V2DI_V2DI_QI, V4DI_FTYPE_V4DI_V4DI_V4DI_QI,
V4DF_FTYPE_V4DF_V4DF_V4DF_QI, V8HI_FTYPE_V16QI_V16QI_V8HI_QI,
V16HI_FTYPE_V32QI_V32QI_V16HI_HI, V8SI_FTYPE_V16HI_V16HI_V8SI_QI,
V4SI_FTYPE_V8HI_V8HI_V4SI_QI, QI_FTYPE_V4DI_V4DI_INT_QI,
QI_FTYPE_V8SI_V8SI_INT_QI, QI_FTYPE_V4DF_V4DF_INT_QI,
QI_FTYPE_V8SF_V8SF_INT_QI, QI_FTYPE_V2DI_V2DI_INT_QI,
QI_FTYPE_V4SI_V4SI_INT_QI, DI_FTYPE_V64QI_V64QI_INT_DI,
SI_FTYPE_V32QI_V32QI_INT_SI, HI_FTYPE_V16QI_V16QI_INT_HI,
SI_FTYPE_V32HI_V32HI_INT_SI, HI_FTYPE_V16HI_V16HI_INT_HI,
QI_FTYPE_V8HI_V8HI_INT_QI, V8SF_FTYPE_V8SF_INT_V8SF_QI,
V4SF_FTYPE_V4SF_INT_V4SF_QI, V2DF_FTYPE_V4DF_INT_V2DF_QI,
V2DI_FTYPE_V4DI_INT_V2DI_QI, V8SF_FTYPE_V16SF_INT_V8SF_QI,
V8SI_FTYPE_V16SI_INT_V8SI_QI, V2DF_FTYPE_V8DF_INT_V2DF_QI,
V2DI_FTYPE_V8DI_INT_V2DI_QI, V4SF_FTYPE_V8SF_INT_V4SF_QI,
V4SI_FTYPE_V8SI_INT_V4SI_QI, V8HI_FTYPE_V8SF_INT_V8HI_QI,
V8HI_FTYPE_V4SF_INT_V8HI_QI, V32HI_FTYPE_V32HI_INT_V32HI_SI,
V16HI_FTYPE_V16HI_INT_V16HI_HI, V8HI_FTYPE_V8HI_INT_V8HI_QI,
V4DI_FTYPE_V4DI_INT_V4DI_QI, V2DI_FTYPE_V2DI_INT_V2DI_QI,
V8SI_FTYPE_V8SI_INT_V8SI_QI, V4SI_FTYPE_V4SI_INT_V4SI_QI,
V4DF_FTYPE_V4DF_INT_V4DF_QI, V2DF_FTYPE_V2DF_INT_V2DF_QI,
V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI, V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI,
V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI, V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI,
V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI, V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI,
V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI, V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI,
V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI, V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI,
V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI, V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI,
V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI, V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI,
V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI, V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI,
V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI, V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI,
V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI, V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI,
V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI, V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI,
V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI, V8DI_FTYPE_V8DF_V8DI_QI_INT,
V8SF_FTYPE_V8DI_V8SF_QI_INT, V8DF_FTYPE_V8DI_V8DF_QI_INT,
V8DI_FTYPE_V8SF_V8DI_QI_INT, V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT,
V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT, VOID_FTYPE_PV4DI_V4DI_QI,
VOID_FTYPE_PV2DI_V2DI_QI, VOID_FTYPE_PV8SI_V8SI_QI,
VOID_FTYPE_PV4SI_V4SI_QI, VOID_FTYPE_PV4SI_V4DI_QI,
VOID_FTYPE_PV4SI_V2DI_QI, VOID_FTYPE_PV8HI_V4DI_QI,
VOID_FTYPE_PV8HI_V2DI_QI, VOID_FTYPE_PV8HI_V8SI_QI,
VOID_FTYPE_PV8HI_V4SI_QI, VOID_FTYPE_PV16QI_V4DI_QI,
VOID_FTYPE_PV16QI_V2DI_QI, VOID_FTYPE_PV16QI_V8SI_QI,
VOID_FTYPE_PV16QI_V4SI_QI, VOID_FTYPE_PV8HI_V8HI_QI,
VOID_FTYPE_PV16HI_V16HI_HI, VOID_FTYPE_PV32HI_V32HI_SI,
VOID_FTYPE_PV16QI_V16QI_HI, VOID_FTYPE_PV32QI_V32QI_SI,
VOID_FTYPE_PV64QI_V64QI_DI, VOID_FTYPE_PV4DF_V4DF_QI,
VOID_FTYPE_PV2DF_V2DF_QI, VOID_FTYPE_PV8SF_V8SF_QI,
VOID_FTYPE_PV4SF_V4SF_QI, V4SF_FTYPE_PCV4SF_V4SF_QI,
V8SF_FTYPE_PCV8SF_V8SF_QI, V4SI_FTYPE_PCV4SI_V4SI_QI,
V8SI_FTYPE_PCV8SI_V8SI_QI, V2DF_FTYPE_PCV2DF_V2DF_QI,
V4DF_FTYPE_PCV4DF_V4DF_QI, V2DI_FTYPE_PCV2DI_V2DI_QI,
V4DI_FTYPE_PCV4DI_V4DI_QI, V8HI_FTYPE_PCV8HI_V8HI_QI,
V16HI_FTYPE_PCV16HI_V16HI_HI, V32HI_FTYPE_PCV32HI_V32HI_SI,
V16QI_FTYPE_PCV16QI_V16QI_HI, V32QI_FTYPE_PCV32QI_V32QI_SI,
V64QI_FTYPE_PCV64QI_V64QI_DI, do not handle V8USI_FTYPE_V8USI.
* tree-core.h
(tree_function_decl): Widen function_code.
--
Thanks, K
AVX-512. 81/n. Add new builtins.
diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def
index 9161287..8315c5e 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -56,6 +56,7 @@ DEF_PRIMITIVE_TYPE (UHI, unsigned_intHI_type_node)
DEF_PRIMITIVE_TYPE (USI, unsigned_intSI_type_node)
DEF_PRIMITIVE_TYPE (UDI, long_long_unsigned_type_node)
# ??? Some of the types below should use the mode types above.
+DEF_PRIMITIVE_TYPE (SHORT, short_integer_type_node)
DEF_PRIMITIVE_TYPE (USHORT, short_unsigned_type_node)
DEF_PRIMITIVE_TYPE (INT, integer_type_node)
DEF_PRIMITIVE_TYPE (UINT, unsigned_type_node)
@@ -107,7 +108,14 @@ DEF_VECTOR_TYPE (V16SF, FLOAT)
DEF_VECTOR_TYPE (V8DF, DOUBLE)
DEF_VECTOR_TYPE (V8DI, DI)
DEF_VECTOR_TYPE (V16SI, SI)
+DEF_VECTOR_TYPE (V32HI, HI)
DEF_VECTOR_TYPE (V64QI, QI)
+DEF_VECTOR_TYPE (V12QI, QI)
+DEF_VECTOR_TYPE (V14QI, QI)
+DEF_VECTOR_TYPE (V32SI, SI)
+DEF_VECTOR_TYPE (V8UDI, UDI, V8DI)
+DEF_VECTOR_TYPE (V16USI, USI, V16SI)
+DEF_VECTOR_TYPE (V32UHI, UHI, V32HI)
DEF_POINTER_TYPE (PCCHAR, CHAR, CONST)
DEF_POINTER_TYPE (PCDOUBLE, DOUBLE, CONST)
@@ -119,6 +127,7 @@ DEF_POINTER_TYPE (PCVOID, VOID, CONST)
DEF_POINTER_TYPE (PVOID, VOID)
DEF_POINTER_TYPE (PDOUBLE, DOUBLE)
DEF_POINTER_TYPE (PFLOAT, FLOAT)
+DEF_POINTER_TYPE (PSHORT, SHORT)
DEF_POINTER_TYPE (PUSHORT, USHORT)
DEF_POINTER_TYPE (PINT, INT)
DEF_POINTER_TYPE (PLONGLONG, LONGLONG)
@@ -142,6 +151,9 @@ DEF_POINTER_TYPE (PV16QI, V16QI)
DEF_POINTER_TYPE (PV16HI, V16HI)
DEF_POINTER_TYPE (PV16SI, V16SI)
DEF_POINTER_TYPE (PV16SF, V16SF)
+DEF_POINTER_TYPE (PV32QI, V32QI)
+DEF_POINTER_TYPE (PV32HI, V32HI)
+DEF_POINTER_TYPE (PV64QI, V64QI)
DEF_POINTER_TYPE (PCV2SI, V2SI, CONST)
DEF_POINTER_TYPE (PCV2DF, V2DF, CONST)
@@ -155,9 +167,15 @@ DEF_POINTER_TYPE (PCV16SF, V16SF, CONST)
DEF_POINTER_TYPE (PCV2DI, V2DI, CONST)
DEF_POINTER_TYPE (PCV4SI, V4SI, CONST)
DEF_POINTER_TYPE (PCV4DI, V4DI, CONST)
+DEF_POINTER_TYPE (PCV8HI, V8HI, CONST)
DEF_POINTER_TYPE (PCV8SI, V8SI, CONST)
DEF_POINTER_TYPE (PCV8DI, V8DI, CONST)
+DEF_POINTER_TYPE (PCV16QI, V16QI, CONST)
+DEF_POINTER_TYPE (PCV16HI, V16HI, CONST)
DEF_POINTER_TYPE (PCV16SI, V16SI, CONST)
+DEF_POINTER_TYPE (PCV32QI, V32QI, CONST)
+DEF_POINTER_TYPE (PCV32HI, V32HI, CONST)
+DEF_POINTER_TYPE (PCV64QI, V64QI, CONST)
DEF_FUNCTION_TYPE (FLOAT128)
DEF_FUNCTION_TYPE (UINT64)
@@ -217,12 +235,15 @@ DEF_FUNCTION_TYPE (V8DF, V8DF)
DEF_FUNCTION_TYPE (V4HI, V4HI)
DEF_FUNCTION_TYPE (V4SF, PCFLOAT)
DEF_FUNCTION_TYPE (V4SF, V2DF)
+DEF_FUNCTION_TYPE (V4SF, V2DF, V4SF, QI)
DEF_FUNCTION_TYPE (V4SF, V4DF)
+DEF_FUNCTION_TYPE (V4SF, V4DF, V4SF, QI)
DEF_FUNCTION_TYPE (V4SF, V4SF)
DEF_FUNCTION_TYPE (V4SF, PCV4SF)
DEF_FUNCTION_TYPE (V4SF, V4SI)
DEF_FUNCTION_TYPE (V4SF, V8SF)
DEF_FUNCTION_TYPE (V4SF, V8HI)
+DEF_FUNCTION_TYPE (V4SF, V8HI, V4SF, QI)
DEF_FUNCTION_TYPE (V4SI, V16QI)
DEF_FUNCTION_TYPE (V4SI, V2DF)
DEF_FUNCTION_TYPE (V4SI, V4DF)
@@ -241,6 +262,7 @@ DEF_FUNCTION_TYPE (V8SF, V4SF)
DEF_FUNCTION_TYPE (V8SF, V8SF)
DEF_FUNCTION_TYPE (V8SF, V8SI)
DEF_FUNCTION_TYPE (V8SF, V8HI)
+DEF_FUNCTION_TYPE (V8SF, V8HI, V8SF, QI)
DEF_FUNCTION_TYPE (V16SF, V16SF)
DEF_FUNCTION_TYPE (V8SI, V8DI)
DEF_FUNCTION_TYPE (V8SI, V4SI)
@@ -251,6 +273,9 @@ DEF_FUNCTION_TYPE (V32QI, V32QI)
DEF_FUNCTION_TYPE (V32QI, V16QI)
DEF_FUNCTION_TYPE (V16HI, V16SI)
DEF_FUNCTION_TYPE (V16HI, V16HI)
+DEF_FUNCTION_TYPE (V16SF, V16HI)
+DEF_FUNCTION_TYPE (V16SF, V16HI, V16SF, HI)
+DEF_FUNCTION_TYPE (V16SF, V16SI)
DEF_FUNCTION_TYPE (V16HI, V8HI)
DEF_FUNCTION_TYPE (V8SI, V8SI)
DEF_FUNCTION_TYPE (VOID, PCVOID)
@@ -266,8 +291,10 @@ DEF_FUNCTION_TYPE (V4DI, V16QI)
DEF_FUNCTION_TYPE (V8SI, V8HI)
DEF_FUNCTION_TYPE (V4DI, V8HI)
DEF_FUNCTION_TYPE (V4DI, V4SI)
+DEF_FUNCTION_TYPE (V4DI, V4DI)
DEF_FUNCTION_TYPE (V4DI, PV4DI)
DEF_FUNCTION_TYPE (V4DI, V2DI)
+DEF_FUNCTION_TYPE (V16SI, V16SF)
DEF_FUNCTION_TYPE (V16SF, FLOAT)
DEF_FUNCTION_TYPE (V16SI, INT)
DEF_FUNCTION_TYPE (V8DF, DOUBLE)
@@ -290,10 +317,38 @@ DEF_FUNCTION_TYPE (V8DI, V8DI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, QI)
DEF_FUNCTION_TYPE (V16SI, PV4SI)
DEF_FUNCTION_TYPE (V16SF, PV4SF)
+DEF_FUNCTION_TYPE (V8DI, PV2DI)
+DEF_FUNCTION_TYPE (V8DF, PV2DF)
+DEF_FUNCTION_TYPE (V4DI, PV2DI)
+DEF_FUNCTION_TYPE (V4DF, PV2DF)
+DEF_FUNCTION_TYPE (V16SI, PV2SI)
+DEF_FUNCTION_TYPE (V16SF, PV2SF)
DEF_FUNCTION_TYPE (V8DI, PV4DI)
DEF_FUNCTION_TYPE (V8DF, PV4DF)
+DEF_FUNCTION_TYPE (V8SF, FLOAT)
+DEF_FUNCTION_TYPE (V4SF, FLOAT)
+DEF_FUNCTION_TYPE (V4DF, DOUBLE)
+DEF_FUNCTION_TYPE (V8SF, PV4SF)
+DEF_FUNCTION_TYPE (V8SI, PV4SI)
+DEF_FUNCTION_TYPE (V4SI, PV2SI)
+DEF_FUNCTION_TYPE (V8SF, PV2SF)
+DEF_FUNCTION_TYPE (V8SI, PV2SI)
+DEF_FUNCTION_TYPE (V16SF, PV8SF)
+DEF_FUNCTION_TYPE (V16SI, PV8SI)
+DEF_FUNCTION_TYPE (V8DI, V8SF)
+DEF_FUNCTION_TYPE (V4DI, V4SF)
+DEF_FUNCTION_TYPE (V2DI, V4SF)
+DEF_FUNCTION_TYPE (V64QI, QI)
+DEF_FUNCTION_TYPE (V32HI, HI)
DEF_FUNCTION_TYPE (V8UHI, V8UHI)
+DEF_FUNCTION_TYPE (V16UHI, V16UHI)
+DEF_FUNCTION_TYPE (V32UHI, V32UHI)
+DEF_FUNCTION_TYPE (V2UDI, V2UDI)
+DEF_FUNCTION_TYPE (V4UDI, V4UDI)
+DEF_FUNCTION_TYPE (V8UDI, V8UDI)
+DEF_FUNCTION_TYPE (V4USI, V4USI)
DEF_FUNCTION_TYPE (V8USI, V8USI)
+DEF_FUNCTION_TYPE (V16USI, V16USI)
DEF_FUNCTION_TYPE (V8DI, PV8DI)
DEF_FUNCTION_TYPE (DI, V2DI, INT)
@@ -336,9 +391,13 @@ DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V4SF)
DEF_FUNCTION_TYPE (V2DF, V4DF, INT)
+DEF_FUNCTION_TYPE (V2DF, V4DF, INT, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V8DF, INT)
+DEF_FUNCTION_TYPE (V2DF, V8DF, INT, V2DF, QI)
DEF_FUNCTION_TYPE (V2DI, V16QI, V16QI)
DEF_FUNCTION_TYPE (V2DI, V2DF, V2DF)
DEF_FUNCTION_TYPE (V2DI, V2DI, INT)
+DEF_FUNCTION_TYPE (V2DI, V2DI, INT, V2DI, QI)
DEF_FUNCTION_TYPE (V2DI, V2DI, SI)
DEF_FUNCTION_TYPE (V2DI, V2DI, V16QI)
DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI)
@@ -353,6 +412,7 @@ DEF_FUNCTION_TYPE (V2SI, V2SI, V2SI)
DEF_FUNCTION_TYPE (V2SI, V4HI, V4HI)
DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DI)
DEF_FUNCTION_TYPE (V4DF, V4DF, INT)
+DEF_FUNCTION_TYPE (V8DF, V8DF, INT)
DEF_FUNCTION_TYPE (V4DF, V8DF, INT)
DEF_FUNCTION_TYPE (V4DF, V8DF, INT, V4DF, QI)
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF)
@@ -377,25 +437,36 @@ DEF_FUNCTION_TYPE (V4SF, V4SF, V2SI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SI)
DEF_FUNCTION_TYPE (V4SF, V8SF, INT)
+DEF_FUNCTION_TYPE (V4SF, V8SF, INT, V4SF, QI)
DEF_FUNCTION_TYPE (V4SI, V2DF, V2DF)
+DEF_FUNCTION_TYPE (V4SI, V2DF, V4SI, QI)
DEF_FUNCTION_TYPE (V4SI, V4SF, V4SF)
DEF_FUNCTION_TYPE (V4SI, V4SI, INT)
+DEF_FUNCTION_TYPE (V4SI, V4SI, INT, V4SI, QI)
DEF_FUNCTION_TYPE (V4SI, V4SI, SI)
DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI)
DEF_FUNCTION_TYPE (V4SI, V8HI, V8HI)
+DEF_FUNCTION_TYPE (V4SI, V8HI, V8HI, V4SI, QI)
DEF_FUNCTION_TYPE (V4SI, V8SI, INT)
+DEF_FUNCTION_TYPE (V4SI, V8SI, INT, V4SI, QI)
DEF_FUNCTION_TYPE (V4SI, PCV4SI, V4SI)
DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI)
+DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI, V8HI, QI)
DEF_FUNCTION_TYPE (V8HI, V4SI, V4SI)
DEF_FUNCTION_TYPE (V8HI, V8HI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DI, INT)
DEF_FUNCTION_TYPE (V8HI, V8HI, SI)
DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI)
DEF_FUNCTION_TYPE (V8HI, V8SF, INT)
+DEF_FUNCTION_TYPE (V8HI, V8SF, INT, V8HI, QI)
DEF_FUNCTION_TYPE (V8HI, V4SF, INT)
+DEF_FUNCTION_TYPE (V8HI, V4SF, INT, V8HI, QI)
DEF_FUNCTION_TYPE (V8QI, V4HI, V4HI)
DEF_FUNCTION_TYPE (V8QI, V8QI, V8QI)
DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SI)
DEF_FUNCTION_TYPE (V8SF, V8SF, INT)
+DEF_FUNCTION_TYPE (V8SF, V16SF, INT)
+DEF_FUNCTION_TYPE (V8SF, V16SF, INT, V8SF, QI)
DEF_FUNCTION_TYPE (V16SF, V16SF, INT)
DEF_FUNCTION_TYPE (V4SF, V16SF, INT)
DEF_FUNCTION_TYPE (V4SF, V16SF, INT, V4SF, QI)
@@ -404,29 +475,46 @@ DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SI)
DEF_FUNCTION_TYPE (V32QI, V16HI, V16HI)
+DEF_FUNCTION_TYPE (V64QI, V32HI, V32HI)
DEF_FUNCTION_TYPE (V16HI, V8SI, V8SI)
+DEF_FUNCTION_TYPE (V32HI, V16SI, V16SI)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V2DF, INT)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V2DF, INT, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V4DF, INT, V8DF, QI)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, INT, V8DF, QI)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, INT, V8DF, QI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, INT, V8DF, QI)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DI, INT)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DI, INT, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DI, INT, QI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DI, INT, QI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, INT, V16SF, HI)
+DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, INT, V16SF, HI, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, INT, V16SF, HI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V4SI, INT, V16SI, HI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SI, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SI, INT, HI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SI, INT, HI, INT)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SI, INT, QI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SI, INT, QI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SI, INT, QI, INT)
-DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT, QI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT, QI, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V4SF, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V4SF, INT, V16SF, HI)
+DEF_FUNCTION_TYPE (V16SF, V16SF, V8SF, INT, V16SF, HI)
DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI)
DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI)
+DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI)
+DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI, V16HI, HI)
+DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI, V32HI, SI)
DEF_FUNCTION_TYPE (V16HI, V16HI, V8HI)
DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, INT)
DEF_FUNCTION_TYPE (V16HI, V16HI, INT)
DEF_FUNCTION_TYPE (V16HI, V16SF, INT)
DEF_FUNCTION_TYPE (V16HI, V16SF, INT, V16HI, HI)
@@ -438,13 +526,20 @@ DEF_FUNCTION_TYPE (V8SI, V4DF, V4DF)
DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V4SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V4SI, INT)
+DEF_FUNCTION_TYPE (V16SI, V16SI, V8SI, INT, V16SI, HI)
DEF_FUNCTION_TYPE (V4SI, V16SI, INT)
DEF_FUNCTION_TYPE (V4SI, V16SI, INT, V4SI, QI)
DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, INT, V16SI, HI)
DEF_FUNCTION_TYPE (V8SI, V16HI, V16HI)
+DEF_FUNCTION_TYPE (V16SI, V32HI, V32HI)
+DEF_FUNCTION_TYPE (V8SI, V16HI, V16HI, V8SI, QI)
+DEF_FUNCTION_TYPE (V16SI, V32HI, V32HI, V16SI, HI)
DEF_FUNCTION_TYPE (V8SI, V8SI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SI, INT, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V16SI, INT)
+DEF_FUNCTION_TYPE (V8SI, V16SI, INT, V8SI, QI)
DEF_FUNCTION_TYPE (V8SI, V8SI, SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, INT)
@@ -455,9 +550,17 @@ DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI)
DEF_FUNCTION_TYPE (V16SI, V8DF, V8DF)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, INT, V8DI, QI)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, INT, V8DI, DI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT, V4DI, SI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT, V2DI, HI)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V4DI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI, INT, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V4DI, INT, V8DI, QI)
DEF_FUNCTION_TYPE (V4DI, V8SI, V8SI)
DEF_FUNCTION_TYPE (V4UDI, V8USI, V8USI)
+DEF_FUNCTION_TYPE (V8DI, V16SI, V16SI)
+DEF_FUNCTION_TYPE (V8DI, V64QI, V64QI)
DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI)
DEF_FUNCTION_TYPE (V4DI, PCV4DI, V4DI)
@@ -466,8 +569,12 @@ DEF_FUNCTION_TYPE (V4DI, V8DI, INT, V4DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8DI, INT, V8DI, QI)
DEF_FUNCTION_TYPE (V4DI, V4DI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, INT, V4DI, QI)
DEF_FUNCTION_TYPE (V2DI, V4DI, INT)
DEF_FUNCTION_TYPE (VOID, PVOID, INT64)
+DEF_FUNCTION_TYPE (V2DI, V4DI, INT, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V8DI, INT)
+DEF_FUNCTION_TYPE (V2DI, V8DI, INT, V2DI, QI)
DEF_FUNCTION_TYPE (VOID, PCHAR, V16QI)
DEF_FUNCTION_TYPE (VOID, PCHAR, V32QI)
DEF_FUNCTION_TYPE (VOID, PDOUBLE, V2DF)
@@ -489,9 +596,72 @@ DEF_FUNCTION_TYPE (VOID, UNSIGNED, UNSIGNED)
DEF_FUNCTION_TYPE (VOID, PV8DI, V8DI)
# Instructions returning mask
+DEF_FUNCTION_TYPE (QI, QI)
DEF_FUNCTION_TYPE (HI, HI)
+DEF_FUNCTION_TYPE (SI, SI)
+DEF_FUNCTION_TYPE (DI, DI)
+DEF_FUNCTION_TYPE (HI, V16QI)
+DEF_FUNCTION_TYPE (SI, V32QI)
+DEF_FUNCTION_TYPE (DI, V64QI)
+DEF_FUNCTION_TYPE (QI, V8HI)
+DEF_FUNCTION_TYPE (HI, V16HI)
+DEF_FUNCTION_TYPE (SI, V32HI)
+DEF_FUNCTION_TYPE (QI, V4SI)
+DEF_FUNCTION_TYPE (QI, V8SI)
+DEF_FUNCTION_TYPE (HI, V16SI)
+DEF_FUNCTION_TYPE (QI, V2DI)
+DEF_FUNCTION_TYPE (QI, V4DI)
+DEF_FUNCTION_TYPE (QI, V8DI)
+DEF_FUNCTION_TYPE (V16QI, HI)
+DEF_FUNCTION_TYPE (V32QI, SI)
+DEF_FUNCTION_TYPE (V64QI, DI)
+DEF_FUNCTION_TYPE (V8HI, QI)
+DEF_FUNCTION_TYPE (V16HI, HI)
+DEF_FUNCTION_TYPE (V32HI, SI)
+DEF_FUNCTION_TYPE (V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, HI)
+DEF_FUNCTION_TYPE (V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, HI)
+DEF_FUNCTION_TYPE (V2DI, QI)
+DEF_FUNCTION_TYPE (V4DI, QI)
+DEF_FUNCTION_TYPE (QI, QI, QI)
DEF_FUNCTION_TYPE (HI, HI, HI)
+DEF_FUNCTION_TYPE (SI, SI, SI)
+DEF_FUNCTION_TYPE (DI, DI, DI)
+DEF_FUNCTION_TYPE (QI, QI, INT)
DEF_FUNCTION_TYPE (HI, HI, INT)
+DEF_FUNCTION_TYPE (SI, SI, INT)
+DEF_FUNCTION_TYPE (DI, DI, INT)
+DEF_FUNCTION_TYPE (HI, V16QI, V16QI)
+DEF_FUNCTION_TYPE (HI, V16QI, V16QI, HI)
+DEF_FUNCTION_TYPE (HI, V16QI, V16QI, INT, HI)
+DEF_FUNCTION_TYPE (SI, V32QI, V32QI)
+DEF_FUNCTION_TYPE (SI, V32QI, V32QI, SI)
+DEF_FUNCTION_TYPE (SI, V32QI, V32QI, INT, SI)
+DEF_FUNCTION_TYPE (DI, V64QI, V64QI)
+DEF_FUNCTION_TYPE (DI, V64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (DI, V64QI, V64QI, INT, DI)
+DEF_FUNCTION_TYPE (QI, V8HI, V8HI)
+DEF_FUNCTION_TYPE (QI, V8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (QI, V8HI, V8HI, INT, QI)
+DEF_FUNCTION_TYPE (HI, V16HI, V16HI)
+DEF_FUNCTION_TYPE (HI, V16HI, V16HI, HI)
+DEF_FUNCTION_TYPE (HI, V16HI, V16HI, INT, HI)
+DEF_FUNCTION_TYPE (SI, V32HI, V32HI)
+DEF_FUNCTION_TYPE (SI, V32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (SI, V32HI, V32HI, INT, SI)
+DEF_FUNCTION_TYPE (QI, V4SI, V4SI)
+DEF_FUNCTION_TYPE (QI, V4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (QI, V4SI, V4SI, INT, QI)
+DEF_FUNCTION_TYPE (QI, V8SI, V8SI)
+DEF_FUNCTION_TYPE (QI, V8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (QI, V8SI, V8SI, INT, QI)
+DEF_FUNCTION_TYPE (QI, V2DI, V2DI)
+DEF_FUNCTION_TYPE (QI, V2DI, V2DI, QI)
+DEF_FUNCTION_TYPE (QI, V2DI, V2DI, INT, QI)
+DEF_FUNCTION_TYPE (QI, V4DI, V4DI)
+DEF_FUNCTION_TYPE (QI, V4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (QI, V4DI, V4DI, INT, QI)
DEF_FUNCTION_TYPE (QI, V8DI, V8DI)
DEF_FUNCTION_TYPE (QI, V8DI, V8DI, QI)
DEF_FUNCTION_TYPE (HI, V16SI, V16SI)
@@ -518,6 +688,7 @@ DEF_FUNCTION_TYPE (V8DI, QI)
DEF_FUNCTION_TYPE (INT, V16QI, V16QI, INT)
DEF_FUNCTION_TYPE (UCHAR, UINT, UINT, UINT)
DEF_FUNCTION_TYPE (UCHAR, UINT64, UINT, UINT)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, V32HI)
DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, V16HI)
DEF_FUNCTION_TYPE (V16QI, V16QI, QI, INT)
DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, INT)
@@ -525,7 +696,10 @@ DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, V16QI)
DEF_FUNCTION_TYPE (V1DI, V1DI, V1DI, INT)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI, INT)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DF)
+DEF_FUNCTION_TYPE (V2DF, V2DI, V2DF, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DI, V2DF, QI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT)
DEF_FUNCTION_TYPE (V2DI, V2DI, DI, INT)
DEF_FUNCTION_TYPE (V2DI, V2DI, UINT, UINT)
@@ -533,9 +707,11 @@ DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT)
DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI)
DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, V32QI)
DEF_FUNCTION_TYPE (V4DF, V4DF, V2DF, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V2DF, INT, V4DF, QI)
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, INT)
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DF)
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, INT)
DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V4DI)
DEF_FUNCTION_TYPE (V4HI, V4HI, HI, INT)
DEF_FUNCTION_TYPE (V4SF, V4SF, FLOAT, INT)
@@ -544,6 +720,10 @@ DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, INT, INT)
DEF_FUNCTION_TYPE (V4SF, V4SF, V2DF, INT)
DEF_FUNCTION_TYPE (V2DF, V2DF, V4SF, INT)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF)
+DEF_FUNCTION_TYPE (V4SF, V4SI, V4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SI, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V2DF, V4SF, QI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SI, INT)
DEF_FUNCTION_TYPE (V4SI, V4SI, SI, INT)
DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, INT)
@@ -554,76 +734,263 @@ DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, INT)
DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, V4SI)
DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, V8HI)
DEF_FUNCTION_TYPE (V8SF, V8SF, V4SF, INT)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V4SF, INT, V8SF, QI)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, INT)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SF)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DF)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SF)
DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI, INT, V8SI, QI)
DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, INT)
DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI)
DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT)
DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI, INT, V4DI, QI)
# Instructions with masking
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V4SF, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V4SI, V2DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4SF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4SI, V4DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8SF, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8SI, V8DF, QI)
+DEF_FUNCTION_TYPE (V2DI, V4SI, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V8HI, V2DI, QI)
+DEF_FUNCTION_TYPE (V8DI, V8DF, V8DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DF, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DF, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT, V2DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT, V4DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8SI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8HI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, V16QI, V8DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V16QI, V2DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V16QI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4SI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V8HI, V4DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, V8DF)
DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DI, V8DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DI, V4DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DF, QI)
+DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, V16QI, HI)
+DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, V16HI, HI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI, HI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DF, QI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V4SF, V2DF, QI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, V32QI, SI)
+DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SI, V4SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SI, V8SF, QI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, HI)
DEF_FUNCTION_TYPE (V16SF, V16SI, V16SF, HI)
+DEF_FUNCTION_TYPE (V4SI, V16QI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V8HI, V4SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V8HI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V16QI, V8SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, INT, V4SI, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SI, V8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, INT, V8SI, QI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SF, HI)
DEF_FUNCTION_TYPE (V16SF, V16SI, V16SF, V16SF)
DEF_FUNCTION_TYPE (V16SF, V16SI, V16SF, V16SF, HI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SI, V16SF, HI)
-DEF_FUNCTION_TYPE (V4SF, V4SF, V2DF, V4SF, QI)
-DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V16SF, V8SF, V16SF, HI)
DEF_FUNCTION_TYPE (V16SF, V4SF, V16SF, HI)
DEF_FUNCTION_TYPE (V8DF, V4DF, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V2DF, V8DF, QI)
+DEF_FUNCTION_TYPE (V16SI, V8SI, V16SI, HI)
DEF_FUNCTION_TYPE (V16SI, V4SI, V16SI, HI)
DEF_FUNCTION_TYPE (V16SI, SI, V16SI, HI)
DEF_FUNCTION_TYPE (V16SI, V16HI, V16SI, HI)
DEF_FUNCTION_TYPE (V16SI, V16QI, V16SI, HI)
DEF_FUNCTION_TYPE (V8SI, V8DF, V8SI, QI)
DEF_FUNCTION_TYPE (V8DI, V4DI, V8DI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4DF, V4SI, QI)
DEF_FUNCTION_TYPE (V8DI, V2DI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, DI, V8DI, QI)
+DEF_FUNCTION_TYPE (V8DI, PCCHAR, V8DI, QI)
+DEF_FUNCTION_TYPE (V8SF, PCFLOAT, V8SF, QI)
+DEF_FUNCTION_TYPE (V4SF, PCFLOAT, V4SF, QI)
+DEF_FUNCTION_TYPE (V4DF, PCDOUBLE, V4DF, QI)
+DEF_FUNCTION_TYPE (V2DF, PCDOUBLE, V2DF, QI)
+DEF_FUNCTION_TYPE (V8SI, PCCHAR, V8SI, QI)
+DEF_FUNCTION_TYPE (V4SI, PCCHAR, V4SI, QI)
+DEF_FUNCTION_TYPE (V4DI, PCCHAR, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, PCCHAR, V2DI, QI)
+DEF_FUNCTION_TYPE (V16QI, V16SI, V16QI, HI)
+DEF_FUNCTION_TYPE (V16QI, V8DI, V16QI, QI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI, INT)
+DEF_FUNCTION_TYPE (V32HI, V32QI, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI, INT)
+DEF_FUNCTION_TYPE (V16HI, V16QI, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V16QI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI, INT)
+DEF_FUNCTION_TYPE (V8SF, V4SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V4DF, V2DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V8SI, V4SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, SI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4DI, V2DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, DI, V2DI, QI)
+DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V64QI, V16QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V64QI, QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, SI)
+DEF_FUNCTION_TYPE (V32QI, V16QI, V32QI, SI)
+DEF_FUNCTION_TYPE (V32QI, QI, V32QI, SI)
+DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, HI)
+DEF_FUNCTION_TYPE (V16QI, QI, V16QI, HI)
+DEF_FUNCTION_TYPE (V32HI, V8HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V32HI, HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V8HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V16HI, HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8HI, HI, V8HI, QI)
+DEF_FUNCTION_TYPE (V64QI, PCV64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V32HI, PCV32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V32QI, PCV32QI, V32QI, SI)
DEF_FUNCTION_TYPE (V16SF, PCV16SF, V16SF, HI)
+DEF_FUNCTION_TYPE (V16SF, PCV8SF, V16SF, HI)
DEF_FUNCTION_TYPE (V8DF, PCV8DF, V8DF, QI)
DEF_FUNCTION_TYPE (V16SI, PCV16SI, V16SI, HI)
+DEF_FUNCTION_TYPE (V16SI, PCV8SI, V16SI, HI)
+DEF_FUNCTION_TYPE (V16HI, PCV16HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V16QI, PCV16QI, V16QI, HI)
+DEF_FUNCTION_TYPE (V8DF, PCV2DF, V8DF, QI)
+DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SF, PCV4SF, V8SF, QI)
DEF_FUNCTION_TYPE (V8DI, PCV8DI, V8DI, QI)
-DEF_FUNCTION_TYPE (V2DF, PCDOUBLE, V2DF, QI)
-DEF_FUNCTION_TYPE (V4SF, PCFLOAT, V4SF, QI)
-DEF_FUNCTION_TYPE (V16QI, V16SI, V16QI, HI)
+DEF_FUNCTION_TYPE (V8DI, PCV2DI, V8DI, QI)
+DEF_FUNCTION_TYPE (V8SI, PCV8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, PCV4SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8HI, PCV8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (V4DF, PCV2DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4SF, PCV4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V4DI, PCV4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, PCV2DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4SI, PCV4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (V2DF, PCV2DF, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DI, PCV2DI, V2DI, QI)
DEF_FUNCTION_TYPE (V16HI, V16SI, V16HI, HI)
DEF_FUNCTION_TYPE (V8SI, V8DI, V8SI, QI)
DEF_FUNCTION_TYPE (V8HI, V8DI, V8HI, QI)
-DEF_FUNCTION_TYPE (V16QI, V8DI, V16QI, QI)
+DEF_FUNCTION_TYPE (V16QI, V8HI, V16QI, QI)
+DEF_FUNCTION_TYPE (V16QI, V16HI, V16QI, HI)
+DEF_FUNCTION_TYPE (V16QI, V4SI, V16QI, QI)
+DEF_FUNCTION_TYPE (V16QI, V8SI, V16QI, QI)
+DEF_FUNCTION_TYPE (V8HI, V4SI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8HI, V8SI, V8HI, QI)
+DEF_FUNCTION_TYPE (V16QI, V2DI, V16QI, QI)
+DEF_FUNCTION_TYPE (V16QI, V4DI, V16QI, QI)
+DEF_FUNCTION_TYPE (V8HI, V2DI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8HI, V4DI, V8HI, QI)
+DEF_FUNCTION_TYPE (V4SI, V2DI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4DI, V4SI, QI)
+DEF_FUNCTION_TYPE (V32QI, V32HI, V32QI, SI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, INT, V2DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, INT, V4DF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, INT, V4SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, INT, V8SF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, INT, V4DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT, V2DF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, INT, V8SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, INT, V4SF, QI)
DEF_FUNCTION_TYPE (VOID, PV8DF, V8DF, QI)
DEF_FUNCTION_TYPE (VOID, PV8SI, V8DI, QI)
DEF_FUNCTION_TYPE (VOID, PV8HI, V8DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V4DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V2DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4SI, V4DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4SI, V2DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V8SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V4SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4DF, V4DF, QI)
+DEF_FUNCTION_TYPE (VOID, PV2DF, V2DF, QI)
DEF_FUNCTION_TYPE (VOID, PV16SF, V16SF, HI)
+DEF_FUNCTION_TYPE (VOID, PV8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (VOID, PV4SF, V4SF, QI)
DEF_FUNCTION_TYPE (VOID, PV8DI, V8DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV2DI, V2DI, QI)
DEF_FUNCTION_TYPE (VOID, PV16SI, V16SI, HI)
DEF_FUNCTION_TYPE (VOID, PV16HI, V16SI, HI)
DEF_FUNCTION_TYPE (VOID, PV16QI, V16SI, HI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V8SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V4SI, QI)
DEF_FUNCTION_TYPE (VOID, PV16QI, V8DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V4DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V2DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (VOID, PV16HI, V16HI, HI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (VOID, PV64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (VOID, PV32QI, V32QI, SI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V16QI, HI)
DEF_FUNCTION_TYPE (VOID, PDOUBLE, V2DF, QI)
DEF_FUNCTION_TYPE (VOID, PFLOAT, V4SF, QI)
DEF_FUNCTION_TYPE (V16SI, V16SF, V16SI, HI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI, INT, QI)
+DEF_FUNCTION_TYPE (V8SI, V8SF, V8SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SF, V4SI, QI)
+DEF_FUNCTION_TYPE (V8DI, V8SF, V8DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4SF, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V4SF, V2DI, QI)
+DEF_FUNCTION_TYPE (V8SF, V8DI, V8SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4DI, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V2DI, V4SF, QI)
+DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DI, V4DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V2DI, V2DF, QI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, INT, V32HI, SI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V8HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V16HI, INT, V16HI, HI)
+DEF_FUNCTION_TYPE (V16HI, V16HI, V8HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V8HI, INT, V8HI, QI)
+DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI, INT, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI, INT, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI, INT, V8HI, QI)
+DEF_FUNCTION_TYPE (V64QI, V32HI, V32HI, V64QI, DI)
+DEF_FUNCTION_TYPE (V32QI, V16HI, V16HI, V32QI, SI)
+DEF_FUNCTION_TYPE (V16QI, V8HI, V8HI, V16QI, HI)
+DEF_FUNCTION_TYPE (V32HI, V16SI, V16SI, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V8SI, V8SI, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V4SI, V4SI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8DI, V16SI, V16SI, V8DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V8SI, V8SI, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V4SI, V4SI, V2DI, QI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI, INT, HI)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI, INT, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V4DI, INT, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI, INT, QI)
DEF_FUNCTION_TYPE (VOID, PCVOID, UNSIGNED, UNSIGNED)
DEF_FUNCTION_TYPE (VOID, PV2DF, V2DI, V2DF)
@@ -648,11 +1015,30 @@ DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DI)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DI, V2DF)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI, V4DF)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DI, V8DF)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SI, V4SF)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI, V8SF)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SI, V16SF)
-DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, INT, V4SF, QI)
-DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT, V2DF, QI)
-DEF_FUNCTION_TYPE (V8DI, V16SI, V16SI, V8DI, QI)
+
+DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI, V4DI, QI)
+
+DEF_FUNCTION_TYPE (QI, V8DF, INT)
+DEF_FUNCTION_TYPE (QI, V4DF, INT)
+DEF_FUNCTION_TYPE (QI, V4DF, V4DF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V2DF, INT)
+DEF_FUNCTION_TYPE (HI, V16SF, INT)
+DEF_FUNCTION_TYPE (QI, V8SF, INT)
+DEF_FUNCTION_TYPE (QI, V8SF, V8SF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V4SF, INT)
+DEF_FUNCTION_TYPE (QI, V8DF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V4DF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V2DF, INT, QI)
+DEF_FUNCTION_TYPE (HI, V16SF, INT, HI)
+DEF_FUNCTION_TYPE (QI, V8SF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V4SF, INT, QI)
DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, UINT, UINT)
DEF_FUNCTION_TYPE (V4HI, HI, HI, HI, HI)
@@ -688,6 +1074,10 @@ DEF_FUNCTION_TYPE (V8SI, V8DF, V8SI, QI, INT)
DEF_FUNCTION_TYPE (V8SF, V8DF, V8SF, QI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, QI, INT)
DEF_FUNCTION_TYPE (V8DF, V8SF, V8DF, QI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DF, V8DI, QI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8SF, V8DI, QI, INT)
+DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, QI, INT)
+DEF_FUNCTION_TYPE (V8SF, V8DI, V8SF, QI, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SF, HI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DF, QI, INT)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF, QI, INT)
@@ -736,16 +1126,53 @@ DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V8SI, QI, INT)
DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V16SI, QI, INT)
DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V8DI, QI, INT)
DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V8DI, QI, INT)
+DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V8SI, QI, INT)
+DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE, V2DI, QI, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V8SF, V8SF, PCFLOAT, V8SI, QI, INT)
+DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V2DI, QI, INT)
+DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V8SF, V8SF, PCFLOAT, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V2DI, V2DI, PCINT64, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V8SI, QI, INT)
+DEF_FUNCTION_TYPE (V2DI, V2DI, PCINT64, V2DI, QI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V8SI, QI, INT)
+DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V2DI, QI, INT)
+DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V4DI, QI, INT)
+
DEF_FUNCTION_TYPE (VOID, PFLOAT, HI, V16SI, V16SF, INT)
+DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V8SI, V8SF, INT)
+DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V4SI, V4SF, INT)
DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V8SI, V8DF, INT)
+DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4SI, V4DF, INT)
+DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4SI, V2DF, INT)
DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V8DI, V8SF, INT)
+DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V4DI, V4SF, INT)
+DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V2DI, V4SF, INT)
DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V8DI, V8DF, INT)
+DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4DI, V4DF, INT)
+DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V2DI, V2DF, INT)
DEF_FUNCTION_TYPE (VOID, PINT, HI, V16SI, V16SI, INT)
+DEF_FUNCTION_TYPE (VOID, PINT, QI, V8SI, V8SI, INT)
+DEF_FUNCTION_TYPE (VOID, PINT, QI, V4SI, V4SI, INT)
DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V8SI, V8DI, INT)
+DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4SI, V4DI, INT)
+DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4SI, V2DI, INT)
DEF_FUNCTION_TYPE (VOID, PINT, QI, V8DI, V8SI, INT)
+DEF_FUNCTION_TYPE (VOID, PINT, QI, V4DI, V4SI, INT)
+DEF_FUNCTION_TYPE (VOID, PINT, QI, V2DI, V4SI, INT)
DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V8DI, V8DI, INT)
DEF_FUNCTION_TYPE (VOID, QI, V8SI, PCINT64, INT, INT)
+DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4DI, V4DI, INT)
+DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V2DI, V2DI, INT)
DEF_FUNCTION_TYPE (VOID, HI, V16SI, PCINT, INT, INT)
DEF_FUNCTION_TYPE (VOID, QI, V8DI, PCINT64, INT, INT)
DEF_FUNCTION_TYPE (VOID, QI, V8DI, PCINT, INT, INT)
@@ -793,8 +1220,13 @@ DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_V2DI, COUNT)
DEF_FUNCTION_TYPE_ALIAS (V2DF_FTYPE_V2DF_V2DF, SWAP)
DEF_FUNCTION_TYPE_ALIAS (V4SF_FTYPE_V4SF_V4SF, SWAP)
+DEF_FUNCTION_TYPE_ALIAS (V8DI_FTYPE_V8DI_INT, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_INT, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V2DI_FTYPE_V2DI_INT, CONVERT)
+DEF_FUNCTION_TYPE_ALIAS (V8DI_FTYPE_V8DI_V8DI_INT, CONVERT)
+DEF_FUNCTION_TYPE_ALIAS (V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI, CONVERT)
+DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI, CONVERT)
+DEF_FUNCTION_TYPE_ALIAS (V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_V4DI_INT, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V2DI_FTYPE_V2DI_V2DI_INT, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V1DI_FTYPE_V1DI_V1DI_INT, CONVERT)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 33b21f4..dd6e693 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -28635,6 +28635,999 @@ enum ix86_builtins
IX86_BUILTIN_KXOR16,
IX86_BUILTIN_KMOV16,
+ /* AVX512VL. */
+ IX86_BUILTIN_PMOVUSQD256_MEM,
+ IX86_BUILTIN_PMOVUSQD128_MEM,
+ IX86_BUILTIN_PMOVSQD256_MEM,
+ IX86_BUILTIN_PMOVSQD128_MEM,
+ IX86_BUILTIN_PMOVQD256_MEM,
+ IX86_BUILTIN_PMOVQD128_MEM,
+ IX86_BUILTIN_PMOVUSQW256_MEM,
+ IX86_BUILTIN_PMOVUSQW128_MEM,
+ IX86_BUILTIN_PMOVSQW256_MEM,
+ IX86_BUILTIN_PMOVSQW128_MEM,
+ IX86_BUILTIN_PMOVQW256_MEM,
+ IX86_BUILTIN_PMOVQW128_MEM,
+ IX86_BUILTIN_PMOVUSQB256_MEM,
+ IX86_BUILTIN_PMOVUSQB128_MEM,
+ IX86_BUILTIN_PMOVSQB256_MEM,
+ IX86_BUILTIN_PMOVSQB128_MEM,
+ IX86_BUILTIN_PMOVQB256_MEM,
+ IX86_BUILTIN_PMOVQB128_MEM,
+ IX86_BUILTIN_PMOVUSDW256_MEM,
+ IX86_BUILTIN_PMOVUSDW128_MEM,
+ IX86_BUILTIN_PMOVSDW256_MEM,
+ IX86_BUILTIN_PMOVSDW128_MEM,
+ IX86_BUILTIN_PMOVDW256_MEM,
+ IX86_BUILTIN_PMOVDW128_MEM,
+ IX86_BUILTIN_PMOVUSDB256_MEM,
+ IX86_BUILTIN_PMOVUSDB128_MEM,
+ IX86_BUILTIN_PMOVSDB256_MEM,
+ IX86_BUILTIN_PMOVSDB128_MEM,
+ IX86_BUILTIN_PMOVDB256_MEM,
+ IX86_BUILTIN_PMOVDB128_MEM,
+ IX86_BUILTIN_MOVDQA64LOAD256_MASK,
+ IX86_BUILTIN_MOVDQA64LOAD128_MASK,
+ IX86_BUILTIN_MOVDQA32LOAD256_MASK,
+ IX86_BUILTIN_MOVDQA32LOAD128_MASK,
+ IX86_BUILTIN_MOVDQA64STORE256_MASK,
+ IX86_BUILTIN_MOVDQA64STORE128_MASK,
+ IX86_BUILTIN_MOVDQA32STORE256_MASK,
+ IX86_BUILTIN_MOVDQA32STORE128_MASK,
+ IX86_BUILTIN_LOADAPD256_MASK,
+ IX86_BUILTIN_LOADAPD128_MASK,
+ IX86_BUILTIN_LOADAPS256_MASK,
+ IX86_BUILTIN_LOADAPS128_MASK,
+ IX86_BUILTIN_STOREAPD256_MASK,
+ IX86_BUILTIN_STOREAPD128_MASK,
+ IX86_BUILTIN_STOREAPS256_MASK,
+ IX86_BUILTIN_STOREAPS128_MASK,
+ IX86_BUILTIN_LOADUPD256_MASK,
+ IX86_BUILTIN_LOADUPD128_MASK,
+ IX86_BUILTIN_LOADUPS256_MASK,
+ IX86_BUILTIN_LOADUPS128_MASK,
+ IX86_BUILTIN_STOREUPD256_MASK,
+ IX86_BUILTIN_STOREUPD128_MASK,
+ IX86_BUILTIN_STOREUPS256_MASK,
+ IX86_BUILTIN_STOREUPS128_MASK,
+ IX86_BUILTIN_LOADDQUDI256_MASK,
+ IX86_BUILTIN_LOADDQUDI128_MASK,
+ IX86_BUILTIN_LOADDQUSI256_MASK,
+ IX86_BUILTIN_LOADDQUSI128_MASK,
+ IX86_BUILTIN_LOADDQUHI256_MASK,
+ IX86_BUILTIN_LOADDQUHI128_MASK,
+ IX86_BUILTIN_LOADDQUQI256_MASK,
+ IX86_BUILTIN_LOADDQUQI128_MASK,
+ IX86_BUILTIN_STOREDQUDI256_MASK,
+ IX86_BUILTIN_STOREDQUDI128_MASK,
+ IX86_BUILTIN_STOREDQUSI256_MASK,
+ IX86_BUILTIN_STOREDQUSI128_MASK,
+ IX86_BUILTIN_STOREDQUHI256_MASK,
+ IX86_BUILTIN_STOREDQUHI128_MASK,
+ IX86_BUILTIN_STOREDQUQI256_MASK,
+ IX86_BUILTIN_STOREDQUQI128_MASK,
+ IX86_BUILTIN_COMPRESSPDSTORE256,
+ IX86_BUILTIN_COMPRESSPDSTORE128,
+ IX86_BUILTIN_COMPRESSPSSTORE256,
+ IX86_BUILTIN_COMPRESSPSSTORE128,
+ IX86_BUILTIN_PCOMPRESSQSTORE256,
+ IX86_BUILTIN_PCOMPRESSQSTORE128,
+ IX86_BUILTIN_PCOMPRESSDSTORE256,
+ IX86_BUILTIN_PCOMPRESSDSTORE128,
+ IX86_BUILTIN_EXPANDPDLOAD256,
+ IX86_BUILTIN_EXPANDPDLOAD128,
+ IX86_BUILTIN_EXPANDPSLOAD256,
+ IX86_BUILTIN_EXPANDPSLOAD128,
+ IX86_BUILTIN_PEXPANDQLOAD256,
+ IX86_BUILTIN_PEXPANDQLOAD128,
+ IX86_BUILTIN_PEXPANDDLOAD256,
+ IX86_BUILTIN_PEXPANDDLOAD128,
+ IX86_BUILTIN_EXPANDPDLOAD256Z,
+ IX86_BUILTIN_EXPANDPDLOAD128Z,
+ IX86_BUILTIN_EXPANDPSLOAD256Z,
+ IX86_BUILTIN_EXPANDPSLOAD128Z,
+ IX86_BUILTIN_PEXPANDQLOAD256Z,
+ IX86_BUILTIN_PEXPANDQLOAD128Z,
+ IX86_BUILTIN_PEXPANDDLOAD256Z,
+ IX86_BUILTIN_PEXPANDDLOAD128Z,
+ IX86_BUILTIN_PALIGNR256_MASK,
+ IX86_BUILTIN_PALIGNR128_MASK,
+ IX86_BUILTIN_MOVDQA64_256_MASK,
+ IX86_BUILTIN_MOVDQA64_128_MASK,
+ IX86_BUILTIN_MOVDQA32_256_MASK,
+ IX86_BUILTIN_MOVDQA32_128_MASK,
+ IX86_BUILTIN_MOVAPD256_MASK,
+ IX86_BUILTIN_MOVAPD128_MASK,
+ IX86_BUILTIN_MOVAPS256_MASK,
+ IX86_BUILTIN_MOVAPS128_MASK,
+ IX86_BUILTIN_MOVDQUHI256_MASK,
+ IX86_BUILTIN_MOVDQUHI128_MASK,
+ IX86_BUILTIN_MOVDQUQI256_MASK,
+ IX86_BUILTIN_MOVDQUQI128_MASK,
+ IX86_BUILTIN_MINPS128_MASK,
+ IX86_BUILTIN_MAXPS128_MASK,
+ IX86_BUILTIN_MINPD128_MASK,
+ IX86_BUILTIN_MAXPD128_MASK,
+ IX86_BUILTIN_MAXPD256_MASK,
+ IX86_BUILTIN_MAXPS256_MASK,
+ IX86_BUILTIN_MINPD256_MASK,
+ IX86_BUILTIN_MINPS256_MASK,
+ IX86_BUILTIN_MULPS128_MASK,
+ IX86_BUILTIN_DIVPS128_MASK,
+ IX86_BUILTIN_MULPD128_MASK,
+ IX86_BUILTIN_DIVPD128_MASK,
+ IX86_BUILTIN_DIVPD256_MASK,
+ IX86_BUILTIN_DIVPS256_MASK,
+ IX86_BUILTIN_MULPD256_MASK,
+ IX86_BUILTIN_MULPS256_MASK,
+ IX86_BUILTIN_ADDPD128_MASK,
+ IX86_BUILTIN_ADDPD256_MASK,
+ IX86_BUILTIN_ADDPS128_MASK,
+ IX86_BUILTIN_ADDPS256_MASK,
+ IX86_BUILTIN_SUBPD128_MASK,
+ IX86_BUILTIN_SUBPD256_MASK,
+ IX86_BUILTIN_SUBPS128_MASK,
+ IX86_BUILTIN_SUBPS256_MASK,
+ IX86_BUILTIN_XORPD256_MASK,
+ IX86_BUILTIN_XORPD128_MASK,
+ IX86_BUILTIN_XORPS256_MASK,
+ IX86_BUILTIN_XORPS128_MASK,
+ IX86_BUILTIN_ORPD256_MASK,
+ IX86_BUILTIN_ORPD128_MASK,
+ IX86_BUILTIN_ORPS256_MASK,
+ IX86_BUILTIN_ORPS128_MASK,
+ IX86_BUILTIN_BROADCASTF32x2_256,
+ IX86_BUILTIN_BROADCASTI32x2_256,
+ IX86_BUILTIN_BROADCASTI32x2_128,
+ IX86_BUILTIN_BROADCASTF64X2_256,
+ IX86_BUILTIN_BROADCASTI64X2_256,
+ IX86_BUILTIN_BROADCASTF32X4_256,
+ IX86_BUILTIN_BROADCASTI32X4_256,
+ IX86_BUILTIN_EXTRACTF32X4_256,
+ IX86_BUILTIN_EXTRACTI32X4_256,
+ IX86_BUILTIN_DBPSADBW256,
+ IX86_BUILTIN_DBPSADBW128,
+ IX86_BUILTIN_CVTTPD2QQ256,
+ IX86_BUILTIN_CVTTPD2QQ128,
+ IX86_BUILTIN_CVTTPD2UQQ256,
+ IX86_BUILTIN_CVTTPD2UQQ128,
+ IX86_BUILTIN_CVTPD2QQ256,
+ IX86_BUILTIN_CVTPD2QQ128,
+ IX86_BUILTIN_CVTPD2UQQ256,
+ IX86_BUILTIN_CVTPD2UQQ128,
+ IX86_BUILTIN_CVTPD2UDQ256_MASK,
+ IX86_BUILTIN_CVTPD2UDQ128_MASK,
+ IX86_BUILTIN_CVTTPS2QQ256,
+ IX86_BUILTIN_CVTTPS2QQ128,
+ IX86_BUILTIN_CVTTPS2UQQ256,
+ IX86_BUILTIN_CVTTPS2UQQ128,
+ IX86_BUILTIN_CVTTPS2DQ256_MASK,
+ IX86_BUILTIN_CVTTPS2DQ128_MASK,
+ IX86_BUILTIN_CVTTPS2UDQ256,
+ IX86_BUILTIN_CVTTPS2UDQ128,
+ IX86_BUILTIN_CVTTPD2DQ256_MASK,
+ IX86_BUILTIN_CVTTPD2DQ128_MASK,
+ IX86_BUILTIN_CVTTPD2UDQ256_MASK,
+ IX86_BUILTIN_CVTTPD2UDQ128_MASK,
+ IX86_BUILTIN_CVTPD2DQ256_MASK,
+ IX86_BUILTIN_CVTPD2DQ128_MASK,
+ IX86_BUILTIN_CVTDQ2PD256_MASK,
+ IX86_BUILTIN_CVTDQ2PD128_MASK,
+ IX86_BUILTIN_CVTUDQ2PD256_MASK,
+ IX86_BUILTIN_CVTUDQ2PD128_MASK,
+ IX86_BUILTIN_CVTDQ2PS256_MASK,
+ IX86_BUILTIN_CVTDQ2PS128_MASK,
+ IX86_BUILTIN_CVTUDQ2PS256_MASK,
+ IX86_BUILTIN_CVTUDQ2PS128_MASK,
+ IX86_BUILTIN_CVTPS2PD256_MASK,
+ IX86_BUILTIN_CVTPS2PD128_MASK,
+ IX86_BUILTIN_PBROADCASTB256_MASK,
+ IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTB128_MASK,
+ IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTW256_MASK,
+ IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTW128_MASK,
+ IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTD256_MASK,
+ IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTD128_MASK,
+ IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTQ256_MASK,
+ IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTQ256_MEM_MASK,
+ IX86_BUILTIN_PBROADCASTQ128_MASK,
+ IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTQ128_MEM_MASK,
+ IX86_BUILTIN_BROADCASTSS256,
+ IX86_BUILTIN_BROADCASTSS128,
+ IX86_BUILTIN_BROADCASTSD256,
+ IX86_BUILTIN_EXTRACTF64X2_256,
+ IX86_BUILTIN_EXTRACTI64X2_256,
+ IX86_BUILTIN_INSERTF32X4_256,
+ IX86_BUILTIN_INSERTI32X4_256,
+ IX86_BUILTIN_PMOVSXBW256_MASK,
+ IX86_BUILTIN_PMOVSXBW128_MASK,
+ IX86_BUILTIN_PMOVSXBD256_MASK,
+ IX86_BUILTIN_PMOVSXBD128_MASK,
+ IX86_BUILTIN_PMOVSXBQ256_MASK,
+ IX86_BUILTIN_PMOVSXBQ128_MASK,
+ IX86_BUILTIN_PMOVSXWD256_MASK,
+ IX86_BUILTIN_PMOVSXWD128_MASK,
+ IX86_BUILTIN_PMOVSXWQ256_MASK,
+ IX86_BUILTIN_PMOVSXWQ128_MASK,
+ IX86_BUILTIN_PMOVSXDQ256_MASK,
+ IX86_BUILTIN_PMOVSXDQ128_MASK,
+ IX86_BUILTIN_PMOVZXBW256_MASK,
+ IX86_BUILTIN_PMOVZXBW128_MASK,
+ IX86_BUILTIN_PMOVZXBD256_MASK,
+ IX86_BUILTIN_PMOVZXBD128_MASK,
+ IX86_BUILTIN_PMOVZXBQ256_MASK,
+ IX86_BUILTIN_PMOVZXBQ128_MASK,
+ IX86_BUILTIN_PMOVZXWD256_MASK,
+ IX86_BUILTIN_PMOVZXWD128_MASK,
+ IX86_BUILTIN_PMOVZXWQ256_MASK,
+ IX86_BUILTIN_PMOVZXWQ128_MASK,
+ IX86_BUILTIN_PMOVZXDQ256_MASK,
+ IX86_BUILTIN_PMOVZXDQ128_MASK,
+ IX86_BUILTIN_REDUCEPD256_MASK,
+ IX86_BUILTIN_REDUCEPD128_MASK,
+ IX86_BUILTIN_REDUCEPS256_MASK,
+ IX86_BUILTIN_REDUCEPS128_MASK,
+ IX86_BUILTIN_REDUCESD_MASK,
+ IX86_BUILTIN_REDUCESS_MASK,
+ IX86_BUILTIN_VPERMVARHI256_MASK,
+ IX86_BUILTIN_VPERMVARHI128_MASK,
+ IX86_BUILTIN_VPERMT2VARHI256,
+ IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
+ IX86_BUILTIN_VPERMT2VARHI128,
+ IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
+ IX86_BUILTIN_VPERMI2VARHI256,
+ IX86_BUILTIN_VPERMI2VARHI128,
+ IX86_BUILTIN_RCP14PD256,
+ IX86_BUILTIN_RCP14PD128,
+ IX86_BUILTIN_RCP14PS256,
+ IX86_BUILTIN_RCP14PS128,
+ IX86_BUILTIN_RSQRT14PD256_MASK,
+ IX86_BUILTIN_RSQRT14PD128_MASK,
+ IX86_BUILTIN_RSQRT14PS256_MASK,
+ IX86_BUILTIN_RSQRT14PS128_MASK,
+ IX86_BUILTIN_SQRTPD256_MASK,
+ IX86_BUILTIN_SQRTPD128_MASK,
+ IX86_BUILTIN_SQRTPS256_MASK,
+ IX86_BUILTIN_SQRTPS128_MASK,
+ IX86_BUILTIN_PADDB128_MASK,
+ IX86_BUILTIN_PADDW128_MASK,
+ IX86_BUILTIN_PADDD128_MASK,
+ IX86_BUILTIN_PADDQ128_MASK,
+ IX86_BUILTIN_PSUBB128_MASK,
+ IX86_BUILTIN_PSUBW128_MASK,
+ IX86_BUILTIN_PSUBD128_MASK,
+ IX86_BUILTIN_PSUBQ128_MASK,
+ IX86_BUILTIN_PADDSB128_MASK,
+ IX86_BUILTIN_PADDSW128_MASK,
+ IX86_BUILTIN_PSUBSB128_MASK,
+ IX86_BUILTIN_PSUBSW128_MASK,
+ IX86_BUILTIN_PADDUSB128_MASK,
+ IX86_BUILTIN_PADDUSW128_MASK,
+ IX86_BUILTIN_PSUBUSB128_MASK,
+ IX86_BUILTIN_PSUBUSW128_MASK,
+ IX86_BUILTIN_PADDB256_MASK,
+ IX86_BUILTIN_PADDW256_MASK,
+ IX86_BUILTIN_PADDD256_MASK,
+ IX86_BUILTIN_PADDQ256_MASK,
+ IX86_BUILTIN_PADDSB256_MASK,
+ IX86_BUILTIN_PADDSW256_MASK,
+ IX86_BUILTIN_PADDUSB256_MASK,
+ IX86_BUILTIN_PADDUSW256_MASK,
+ IX86_BUILTIN_PSUBB256_MASK,
+ IX86_BUILTIN_PSUBW256_MASK,
+ IX86_BUILTIN_PSUBD256_MASK,
+ IX86_BUILTIN_PSUBQ256_MASK,
+ IX86_BUILTIN_PSUBSB256_MASK,
+ IX86_BUILTIN_PSUBSW256_MASK,
+ IX86_BUILTIN_PSUBUSB256_MASK,
+ IX86_BUILTIN_PSUBUSW256_MASK,
+ IX86_BUILTIN_SHUF_F64x2_256,
+ IX86_BUILTIN_SHUF_I64x2_256,
+ IX86_BUILTIN_SHUF_I32x4_256,
+ IX86_BUILTIN_SHUF_F32x4_256,
+ IX86_BUILTIN_PMOVWB128,
+ IX86_BUILTIN_PMOVWB256,
+ IX86_BUILTIN_PMOVSWB128,
+ IX86_BUILTIN_PMOVSWB256,
+ IX86_BUILTIN_PMOVUSWB128,
+ IX86_BUILTIN_PMOVUSWB256,
+ IX86_BUILTIN_PMOVDB128,
+ IX86_BUILTIN_PMOVDB256,
+ IX86_BUILTIN_PMOVSDB128,
+ IX86_BUILTIN_PMOVSDB256,
+ IX86_BUILTIN_PMOVUSDB128,
+ IX86_BUILTIN_PMOVUSDB256,
+ IX86_BUILTIN_PMOVDW128,
+ IX86_BUILTIN_PMOVDW256,
+ IX86_BUILTIN_PMOVSDW128,
+ IX86_BUILTIN_PMOVSDW256,
+ IX86_BUILTIN_PMOVUSDW128,
+ IX86_BUILTIN_PMOVUSDW256,
+ IX86_BUILTIN_PMOVQB128,
+ IX86_BUILTIN_PMOVQB256,
+ IX86_BUILTIN_PMOVSQB128,
+ IX86_BUILTIN_PMOVSQB256,
+ IX86_BUILTIN_PMOVUSQB128,
+ IX86_BUILTIN_PMOVUSQB256,
+ IX86_BUILTIN_PMOVQW128,
+ IX86_BUILTIN_PMOVQW256,
+ IX86_BUILTIN_PMOVSQW128,
+ IX86_BUILTIN_PMOVSQW256,
+ IX86_BUILTIN_PMOVUSQW128,
+ IX86_BUILTIN_PMOVUSQW256,
+ IX86_BUILTIN_PMOVQD128,
+ IX86_BUILTIN_PMOVQD256,
+ IX86_BUILTIN_PMOVSQD128,
+ IX86_BUILTIN_PMOVSQD256,
+ IX86_BUILTIN_PMOVUSQD128,
+ IX86_BUILTIN_PMOVUSQD256,
+ IX86_BUILTIN_RANGEPD256,
+ IX86_BUILTIN_RANGEPD128,
+ IX86_BUILTIN_RANGEPS256,
+ IX86_BUILTIN_RANGEPS128,
+ IX86_BUILTIN_GETEXPPS256,
+ IX86_BUILTIN_GETEXPPD256,
+ IX86_BUILTIN_GETEXPPS128,
+ IX86_BUILTIN_GETEXPPD128,
+ IX86_BUILTIN_FIXUPIMMPD256,
+ IX86_BUILTIN_FIXUPIMMPD256_MASK,
+ IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
+ IX86_BUILTIN_FIXUPIMMPS256,
+ IX86_BUILTIN_FIXUPIMMPS256_MASK,
+ IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
+ IX86_BUILTIN_FIXUPIMMPD128,
+ IX86_BUILTIN_FIXUPIMMPD128_MASK,
+ IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
+ IX86_BUILTIN_FIXUPIMMPS128,
+ IX86_BUILTIN_FIXUPIMMPS128_MASK,
+ IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
+ IX86_BUILTIN_PABSQ256,
+ IX86_BUILTIN_PABSQ128,
+ IX86_BUILTIN_PABSD256_MASK,
+ IX86_BUILTIN_PABSD128_MASK,
+ IX86_BUILTIN_PMULHRSW256_MASK,
+ IX86_BUILTIN_PMULHRSW128_MASK,
+ IX86_BUILTIN_PMULHUW128_MASK,
+ IX86_BUILTIN_PMULHUW256_MASK,
+ IX86_BUILTIN_PMULHW256_MASK,
+ IX86_BUILTIN_PMULHW128_MASK,
+ IX86_BUILTIN_PMULLW256_MASK,
+ IX86_BUILTIN_PMULLW128_MASK,
+ IX86_BUILTIN_PMULLQ256,
+ IX86_BUILTIN_PMULLQ128,
+ IX86_BUILTIN_ANDPD256_MASK,
+ IX86_BUILTIN_ANDPD128_MASK,
+ IX86_BUILTIN_ANDPS256_MASK,
+ IX86_BUILTIN_ANDPS128_MASK,
+ IX86_BUILTIN_ANDNPD256_MASK,
+ IX86_BUILTIN_ANDNPD128_MASK,
+ IX86_BUILTIN_ANDNPS256_MASK,
+ IX86_BUILTIN_ANDNPS128_MASK,
+ IX86_BUILTIN_PSLLWI128_MASK,
+ IX86_BUILTIN_PSLLDI128_MASK,
+ IX86_BUILTIN_PSLLQI128_MASK,
+ IX86_BUILTIN_PSLLW128_MASK,
+ IX86_BUILTIN_PSLLD128_MASK,
+ IX86_BUILTIN_PSLLQ128_MASK,
+ IX86_BUILTIN_PSLLWI256_MASK ,
+ IX86_BUILTIN_PSLLW256_MASK,
+ IX86_BUILTIN_PSLLDI256_MASK,
+ IX86_BUILTIN_PSLLD256_MASK,
+ IX86_BUILTIN_PSLLQI256_MASK,
+ IX86_BUILTIN_PSLLQ256_MASK,
+ IX86_BUILTIN_PSRADI128_MASK,
+ IX86_BUILTIN_PSRAD128_MASK,
+ IX86_BUILTIN_PSRADI256_MASK,
+ IX86_BUILTIN_PSRAD256_MASK,
+ IX86_BUILTIN_PSRAQI128_MASK,
+ IX86_BUILTIN_PSRAQ128_MASK,
+ IX86_BUILTIN_PSRAQI256_MASK,
+ IX86_BUILTIN_PSRAQ256_MASK,
+ IX86_BUILTIN_PANDD256,
+ IX86_BUILTIN_PANDD128,
+ IX86_BUILTIN_PSRLDI128_MASK,
+ IX86_BUILTIN_PSRLD128_MASK,
+ IX86_BUILTIN_PSRLDI256_MASK,
+ IX86_BUILTIN_PSRLD256_MASK,
+ IX86_BUILTIN_PSRLQI128_MASK,
+ IX86_BUILTIN_PSRLQ128_MASK,
+ IX86_BUILTIN_PSRLQI256_MASK,
+ IX86_BUILTIN_PSRLQ256_MASK,
+ IX86_BUILTIN_PANDQ256,
+ IX86_BUILTIN_PANDQ128,
+ IX86_BUILTIN_PANDND256,
+ IX86_BUILTIN_PANDND128,
+ IX86_BUILTIN_PANDNQ256,
+ IX86_BUILTIN_PANDNQ128,
+ IX86_BUILTIN_PORD256,
+ IX86_BUILTIN_PORD128,
+ IX86_BUILTIN_PORQ256,
+ IX86_BUILTIN_PORQ128,
+ IX86_BUILTIN_PXORD256,
+ IX86_BUILTIN_PXORD128,
+ IX86_BUILTIN_PXORQ256,
+ IX86_BUILTIN_PXORQ128,
+ IX86_BUILTIN_PACKSSWB256_MASK,
+ IX86_BUILTIN_PACKSSWB128_MASK,
+ IX86_BUILTIN_PACKUSWB256_MASK,
+ IX86_BUILTIN_PACKUSWB128_MASK,
+ IX86_BUILTIN_RNDSCALEPS256,
+ IX86_BUILTIN_RNDSCALEPD256,
+ IX86_BUILTIN_RNDSCALEPS128,
+ IX86_BUILTIN_RNDSCALEPD128,
+ IX86_BUILTIN_VTERNLOGQ256_MASK,
+ IX86_BUILTIN_VTERNLOGQ256_MASKZ,
+ IX86_BUILTIN_VTERNLOGD256_MASK,
+ IX86_BUILTIN_VTERNLOGD256_MASKZ,
+ IX86_BUILTIN_VTERNLOGQ128_MASK,
+ IX86_BUILTIN_VTERNLOGQ128_MASKZ,
+ IX86_BUILTIN_VTERNLOGD128_MASK,
+ IX86_BUILTIN_VTERNLOGD128_MASKZ,
+ IX86_BUILTIN_SCALEFPD256,
+ IX86_BUILTIN_SCALEFPS256,
+ IX86_BUILTIN_SCALEFPD128,
+ IX86_BUILTIN_SCALEFPS128,
+ IX86_BUILTIN_VFMADDPD256_MASK,
+ IX86_BUILTIN_VFMADDPD256_MASK3,
+ IX86_BUILTIN_VFMADDPD256_MASKZ,
+ IX86_BUILTIN_VFMADDPD128_MASK,
+ IX86_BUILTIN_VFMADDPD128_MASK3,
+ IX86_BUILTIN_VFMADDPD128_MASKZ,
+ IX86_BUILTIN_VFMADDPS256_MASK,
+ IX86_BUILTIN_VFMADDPS256_MASK3,
+ IX86_BUILTIN_VFMADDPS256_MASKZ,
+ IX86_BUILTIN_VFMADDPS128_MASK,
+ IX86_BUILTIN_VFMADDPS128_MASK3,
+ IX86_BUILTIN_VFMADDPS128_MASKZ,
+ IX86_BUILTIN_VFMSUBPD256_MASK3,
+ IX86_BUILTIN_VFMSUBPD128_MASK3,
+ IX86_BUILTIN_VFMSUBPS256_MASK3,
+ IX86_BUILTIN_VFMSUBPS128_MASK3,
+ IX86_BUILTIN_VFNMADDPD256_MASK,
+ IX86_BUILTIN_VFNMADDPD128_MASK,
+ IX86_BUILTIN_VFNMADDPS256_MASK,
+ IX86_BUILTIN_VFNMADDPS128_MASK,
+ IX86_BUILTIN_VFNMSUBPD256_MASK,
+ IX86_BUILTIN_VFNMSUBPD256_MASK3,
+ IX86_BUILTIN_VFNMSUBPD128_MASK,
+ IX86_BUILTIN_VFNMSUBPD128_MASK3,
+ IX86_BUILTIN_VFNMSUBPS256_MASK,
+ IX86_BUILTIN_VFNMSUBPS256_MASK3,
+ IX86_BUILTIN_VFNMSUBPS128_MASK,
+ IX86_BUILTIN_VFNMSUBPS128_MASK3,
+ IX86_BUILTIN_VFMADDSUBPD256_MASK,
+ IX86_BUILTIN_VFMADDSUBPD256_MASK3,
+ IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
+ IX86_BUILTIN_VFMADDSUBPD128_MASK,
+ IX86_BUILTIN_VFMADDSUBPD128_MASK3,
+ IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
+ IX86_BUILTIN_VFMADDSUBPS256_MASK,
+ IX86_BUILTIN_VFMADDSUBPS256_MASK3,
+ IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
+ IX86_BUILTIN_VFMADDSUBPS128_MASK,
+ IX86_BUILTIN_VFMADDSUBPS128_MASK3,
+ IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
+ IX86_BUILTIN_VFMSUBADDPD256_MASK3,
+ IX86_BUILTIN_VFMSUBADDPD128_MASK3,
+ IX86_BUILTIN_VFMSUBADDPS256_MASK3,
+ IX86_BUILTIN_VFMSUBADDPS128_MASK3,
+ IX86_BUILTIN_INSERTF64X2_256,
+ IX86_BUILTIN_INSERTI64X2_256,
+ IX86_BUILTIN_PSRAVV16HI,
+ IX86_BUILTIN_PSRAVV8HI,
+ IX86_BUILTIN_PMADDUBSW256_MASK,
+ IX86_BUILTIN_PMADDUBSW128_MASK,
+ IX86_BUILTIN_PMADDWD256_MASK,
+ IX86_BUILTIN_PMADDWD128_MASK,
+ IX86_BUILTIN_PSRLVV16HI,
+ IX86_BUILTIN_PSRLVV8HI,
+ IX86_BUILTIN_CVTPS2DQ256_MASK,
+ IX86_BUILTIN_CVTPS2DQ128_MASK,
+ IX86_BUILTIN_CVTPS2UDQ256,
+ IX86_BUILTIN_CVTPS2UDQ128,
+ IX86_BUILTIN_CVTPS2QQ256,
+ IX86_BUILTIN_CVTPS2QQ128,
+ IX86_BUILTIN_CVTPS2UQQ256,
+ IX86_BUILTIN_CVTPS2UQQ128,
+ IX86_BUILTIN_GETMANTPS256,
+ IX86_BUILTIN_GETMANTPS128,
+ IX86_BUILTIN_GETMANTPD256,
+ IX86_BUILTIN_GETMANTPD128,
+ IX86_BUILTIN_MOVDDUP256_MASK,
+ IX86_BUILTIN_MOVDDUP128_MASK,
+ IX86_BUILTIN_MOVSHDUP256_MASK,
+ IX86_BUILTIN_MOVSHDUP128_MASK,
+ IX86_BUILTIN_MOVSLDUP256_MASK,
+ IX86_BUILTIN_MOVSLDUP128_MASK,
+ IX86_BUILTIN_CVTQQ2PS256,
+ IX86_BUILTIN_CVTQQ2PS128,
+ IX86_BUILTIN_CVTUQQ2PS256,
+ IX86_BUILTIN_CVTUQQ2PS128,
+ IX86_BUILTIN_CVTQQ2PD256,
+ IX86_BUILTIN_CVTQQ2PD128,
+ IX86_BUILTIN_CVTUQQ2PD256,
+ IX86_BUILTIN_CVTUQQ2PD128,
+ IX86_BUILTIN_VPERMT2VARQ256,
+ IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
+ IX86_BUILTIN_VPERMT2VARD256,
+ IX86_BUILTIN_VPERMT2VARD256_MASKZ,
+ IX86_BUILTIN_VPERMI2VARQ256,
+ IX86_BUILTIN_VPERMI2VARD256,
+ IX86_BUILTIN_VPERMT2VARPD256,
+ IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
+ IX86_BUILTIN_VPERMT2VARPS256,
+ IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
+ IX86_BUILTIN_VPERMI2VARPD256,
+ IX86_BUILTIN_VPERMI2VARPS256,
+ IX86_BUILTIN_VPERMT2VARQ128,
+ IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
+ IX86_BUILTIN_VPERMT2VARD128,
+ IX86_BUILTIN_VPERMT2VARD128_MASKZ,
+ IX86_BUILTIN_VPERMI2VARQ128,
+ IX86_BUILTIN_VPERMI2VARD128,
+ IX86_BUILTIN_VPERMT2VARPD128,
+ IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
+ IX86_BUILTIN_VPERMT2VARPS128,
+ IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
+ IX86_BUILTIN_VPERMI2VARPD128,
+ IX86_BUILTIN_VPERMI2VARPS128,
+ IX86_BUILTIN_PSHUFB256_MASK,
+ IX86_BUILTIN_PSHUFB128_MASK,
+ IX86_BUILTIN_PSHUFHW256_MASK,
+ IX86_BUILTIN_PSHUFHW128_MASK,
+ IX86_BUILTIN_PSHUFLW256_MASK,
+ IX86_BUILTIN_PSHUFLW128_MASK,
+ IX86_BUILTIN_PSHUFD256_MASK,
+ IX86_BUILTIN_PSHUFD128_MASK,
+ IX86_BUILTIN_SHUFPD256_MASK,
+ IX86_BUILTIN_SHUFPD128_MASK,
+ IX86_BUILTIN_SHUFPS256_MASK,
+ IX86_BUILTIN_SHUFPS128_MASK,
+ IX86_BUILTIN_PROLVQ256,
+ IX86_BUILTIN_PROLVQ128,
+ IX86_BUILTIN_PROLQ256,
+ IX86_BUILTIN_PROLQ128,
+ IX86_BUILTIN_PRORVQ256,
+ IX86_BUILTIN_PRORVQ128,
+ IX86_BUILTIN_PRORQ256,
+ IX86_BUILTIN_PRORQ128,
+ IX86_BUILTIN_PSRAVQ128,
+ IX86_BUILTIN_PSRAVQ256,
+ IX86_BUILTIN_PSLLVV4DI_MASK,
+ IX86_BUILTIN_PSLLVV2DI_MASK,
+ IX86_BUILTIN_PSLLVV8SI_MASK,
+ IX86_BUILTIN_PSLLVV4SI_MASK,
+ IX86_BUILTIN_PSRAVV8SI_MASK,
+ IX86_BUILTIN_PSRAVV4SI_MASK,
+ IX86_BUILTIN_PSRLVV4DI_MASK,
+ IX86_BUILTIN_PSRLVV2DI_MASK,
+ IX86_BUILTIN_PSRLVV8SI_MASK,
+ IX86_BUILTIN_PSRLVV4SI_MASK,
+ IX86_BUILTIN_PSRAWI256_MASK,
+ IX86_BUILTIN_PSRAW256_MASK,
+ IX86_BUILTIN_PSRAWI128_MASK,
+ IX86_BUILTIN_PSRAW128_MASK,
+ IX86_BUILTIN_PSRLWI256_MASK,
+ IX86_BUILTIN_PSRLW256_MASK,
+ IX86_BUILTIN_PSRLWI128_MASK,
+ IX86_BUILTIN_PSRLW128_MASK,
+ IX86_BUILTIN_PRORVD256,
+ IX86_BUILTIN_PROLVD256,
+ IX86_BUILTIN_PRORD256,
+ IX86_BUILTIN_PROLD256,
+ IX86_BUILTIN_PRORVD128,
+ IX86_BUILTIN_PROLVD128,
+ IX86_BUILTIN_PRORD128,
+ IX86_BUILTIN_PROLD128,
+ IX86_BUILTIN_FPCLASSPD256,
+ IX86_BUILTIN_FPCLASSPD128,
+ IX86_BUILTIN_FPCLASSSD,
+ IX86_BUILTIN_FPCLASSPS256,
+ IX86_BUILTIN_FPCLASSPS128,
+ IX86_BUILTIN_FPCLASSSS,
+ IX86_BUILTIN_CVTB2MASK128,
+ IX86_BUILTIN_CVTB2MASK256,
+ IX86_BUILTIN_CVTW2MASK128,
+ IX86_BUILTIN_CVTW2MASK256,
+ IX86_BUILTIN_CVTD2MASK128,
+ IX86_BUILTIN_CVTD2MASK256,
+ IX86_BUILTIN_CVTQ2MASK128,
+ IX86_BUILTIN_CVTQ2MASK256,
+ IX86_BUILTIN_CVTMASK2B128,
+ IX86_BUILTIN_CVTMASK2B256,
+ IX86_BUILTIN_CVTMASK2W128,
+ IX86_BUILTIN_CVTMASK2W256,
+ IX86_BUILTIN_CVTMASK2D128,
+ IX86_BUILTIN_CVTMASK2D256,
+ IX86_BUILTIN_CVTMASK2Q128,
+ IX86_BUILTIN_CVTMASK2Q256,
+ IX86_BUILTIN_PCMPEQB128_MASK,
+ IX86_BUILTIN_PCMPEQB256_MASK,
+ IX86_BUILTIN_PCMPEQW128_MASK,
+ IX86_BUILTIN_PCMPEQW256_MASK,
+ IX86_BUILTIN_PCMPEQD128_MASK,
+ IX86_BUILTIN_PCMPEQD256_MASK,
+ IX86_BUILTIN_PCMPEQQ128_MASK,
+ IX86_BUILTIN_PCMPEQQ256_MASK,
+ IX86_BUILTIN_PCMPGTB128_MASK,
+ IX86_BUILTIN_PCMPGTB256_MASK,
+ IX86_BUILTIN_PCMPGTW128_MASK,
+ IX86_BUILTIN_PCMPGTW256_MASK,
+ IX86_BUILTIN_PCMPGTD128_MASK,
+ IX86_BUILTIN_PCMPGTD256_MASK,
+ IX86_BUILTIN_PCMPGTQ128_MASK,
+ IX86_BUILTIN_PCMPGTQ256_MASK,
+ IX86_BUILTIN_PTESTMB128,
+ IX86_BUILTIN_PTESTMB256,
+ IX86_BUILTIN_PTESTMW128,
+ IX86_BUILTIN_PTESTMW256,
+ IX86_BUILTIN_PTESTMD128,
+ IX86_BUILTIN_PTESTMD256,
+ IX86_BUILTIN_PTESTMQ128,
+ IX86_BUILTIN_PTESTMQ256,
+ IX86_BUILTIN_PTESTNMB128,
+ IX86_BUILTIN_PTESTNMB256,
+ IX86_BUILTIN_PTESTNMW128,
+ IX86_BUILTIN_PTESTNMW256,
+ IX86_BUILTIN_PTESTNMD128,
+ IX86_BUILTIN_PTESTNMD256,
+ IX86_BUILTIN_PTESTNMQ128,
+ IX86_BUILTIN_PTESTNMQ256,
+ IX86_BUILTIN_PBROADCASTMB128,
+ IX86_BUILTIN_PBROADCASTMB256,
+ IX86_BUILTIN_PBROADCASTMW128,
+ IX86_BUILTIN_PBROADCASTMW256,
+ IX86_BUILTIN_COMPRESSPD256,
+ IX86_BUILTIN_COMPRESSPD128,
+ IX86_BUILTIN_COMPRESSPS256,
+ IX86_BUILTIN_COMPRESSPS128,
+ IX86_BUILTIN_PCOMPRESSQ256,
+ IX86_BUILTIN_PCOMPRESSQ128,
+ IX86_BUILTIN_PCOMPRESSD256,
+ IX86_BUILTIN_PCOMPRESSD128,
+ IX86_BUILTIN_EXPANDPD256,
+ IX86_BUILTIN_EXPANDPD128,
+ IX86_BUILTIN_EXPANDPS256,
+ IX86_BUILTIN_EXPANDPS128,
+ IX86_BUILTIN_PEXPANDQ256,
+ IX86_BUILTIN_PEXPANDQ128,
+ IX86_BUILTIN_PEXPANDD256,
+ IX86_BUILTIN_PEXPANDD128,
+ IX86_BUILTIN_EXPANDPD256Z,
+ IX86_BUILTIN_EXPANDPD128Z,
+ IX86_BUILTIN_EXPANDPS256Z,
+ IX86_BUILTIN_EXPANDPS128Z,
+ IX86_BUILTIN_PEXPANDQ256Z,
+ IX86_BUILTIN_PEXPANDQ128Z,
+ IX86_BUILTIN_PEXPANDD256Z,
+ IX86_BUILTIN_PEXPANDD128Z,
+ IX86_BUILTIN_PMAXSD256_MASK,
+ IX86_BUILTIN_PMINSD256_MASK,
+ IX86_BUILTIN_PMAXUD256_MASK,
+ IX86_BUILTIN_PMINUD256_MASK,
+ IX86_BUILTIN_PMAXSD128_MASK,
+ IX86_BUILTIN_PMINSD128_MASK,
+ IX86_BUILTIN_PMAXUD128_MASK,
+ IX86_BUILTIN_PMINUD128_MASK,
+ IX86_BUILTIN_PMAXSQ256_MASK,
+ IX86_BUILTIN_PMINSQ256_MASK,
+ IX86_BUILTIN_PMAXUQ256_MASK,
+ IX86_BUILTIN_PMINUQ256_MASK,
+ IX86_BUILTIN_PMAXSQ128_MASK,
+ IX86_BUILTIN_PMINSQ128_MASK,
+ IX86_BUILTIN_PMAXUQ128_MASK,
+ IX86_BUILTIN_PMINUQ128_MASK,
+ IX86_BUILTIN_PMINSB256_MASK,
+ IX86_BUILTIN_PMINUB256_MASK,
+ IX86_BUILTIN_PMAXSB256_MASK,
+ IX86_BUILTIN_PMAXUB256_MASK,
+ IX86_BUILTIN_PMINSB128_MASK,
+ IX86_BUILTIN_PMINUB128_MASK,
+ IX86_BUILTIN_PMAXSB128_MASK,
+ IX86_BUILTIN_PMAXUB128_MASK,
+ IX86_BUILTIN_PMINSW256_MASK,
+ IX86_BUILTIN_PMINUW256_MASK,
+ IX86_BUILTIN_PMAXSW256_MASK,
+ IX86_BUILTIN_PMAXUW256_MASK,
+ IX86_BUILTIN_PMINSW128_MASK,
+ IX86_BUILTIN_PMINUW128_MASK,
+ IX86_BUILTIN_PMAXSW128_MASK,
+ IX86_BUILTIN_PMAXUW128_MASK,
+ IX86_BUILTIN_VPCONFLICTQ256,
+ IX86_BUILTIN_VPCONFLICTD256,
+ IX86_BUILTIN_VPCLZCNTQ256,
+ IX86_BUILTIN_VPCLZCNTD256,
+ IX86_BUILTIN_UNPCKHPD256_MASK,
+ IX86_BUILTIN_UNPCKHPD128_MASK,
+ IX86_BUILTIN_UNPCKHPS256_MASK,
+ IX86_BUILTIN_UNPCKHPS128_MASK,
+ IX86_BUILTIN_UNPCKLPD256_MASK,
+ IX86_BUILTIN_UNPCKLPD128_MASK,
+ IX86_BUILTIN_UNPCKLPS256_MASK,
+ IX86_BUILTIN_VPCONFLICTQ128,
+ IX86_BUILTIN_VPCONFLICTD128,
+ IX86_BUILTIN_VPCLZCNTQ128,
+ IX86_BUILTIN_VPCLZCNTD128,
+ IX86_BUILTIN_UNPCKLPS128_MASK,
+ IX86_BUILTIN_ALIGND256,
+ IX86_BUILTIN_ALIGNQ256,
+ IX86_BUILTIN_ALIGND128,
+ IX86_BUILTIN_ALIGNQ128,
+ IX86_BUILTIN_CVTPS2PH256_MASK,
+ IX86_BUILTIN_CVTPS2PH_MASK,
+ IX86_BUILTIN_CVTPH2PS_MASK,
+ IX86_BUILTIN_CVTPH2PS256_MASK,
+ IX86_BUILTIN_PUNPCKHDQ128_MASK,
+ IX86_BUILTIN_PUNPCKHDQ256_MASK,
+ IX86_BUILTIN_PUNPCKHQDQ128_MASK,
+ IX86_BUILTIN_PUNPCKHQDQ256_MASK,
+ IX86_BUILTIN_PUNPCKLDQ128_MASK,
+ IX86_BUILTIN_PUNPCKLDQ256_MASK,
+ IX86_BUILTIN_PUNPCKLQDQ128_MASK,
+ IX86_BUILTIN_PUNPCKLQDQ256_MASK,
+ IX86_BUILTIN_PUNPCKHBW128_MASK,
+ IX86_BUILTIN_PUNPCKHBW256_MASK,
+ IX86_BUILTIN_PUNPCKHWD128_MASK,
+ IX86_BUILTIN_PUNPCKHWD256_MASK,
+ IX86_BUILTIN_PUNPCKLBW128_MASK,
+ IX86_BUILTIN_PUNPCKLBW256_MASK,
+ IX86_BUILTIN_PUNPCKLWD128_MASK,
+ IX86_BUILTIN_PUNPCKLWD256_MASK,
+ IX86_BUILTIN_PSLLVV16HI,
+ IX86_BUILTIN_PSLLVV8HI,
+ IX86_BUILTIN_PACKSSDW256_MASK,
+ IX86_BUILTIN_PACKSSDW128_MASK,
+ IX86_BUILTIN_PACKUSDW256_MASK,
+ IX86_BUILTIN_PACKUSDW128_MASK,
+ IX86_BUILTIN_PAVGB256_MASK,
+ IX86_BUILTIN_PAVGW256_MASK,
+ IX86_BUILTIN_PAVGB128_MASK,
+ IX86_BUILTIN_PAVGW128_MASK,
+ IX86_BUILTIN_VPERMVARSF256_MASK,
+ IX86_BUILTIN_VPERMVARDF256_MASK,
+ IX86_BUILTIN_VPERMDF256_MASK,
+ IX86_BUILTIN_PABSB256_MASK,
+ IX86_BUILTIN_PABSB128_MASK,
+ IX86_BUILTIN_PABSW256_MASK,
+ IX86_BUILTIN_PABSW128_MASK,
+ IX86_BUILTIN_VPERMILVARPD_MASK,
+ IX86_BUILTIN_VPERMILVARPS_MASK,
+ IX86_BUILTIN_VPERMILVARPD256_MASK,
+ IX86_BUILTIN_VPERMILVARPS256_MASK,
+ IX86_BUILTIN_VPERMILPD_MASK,
+ IX86_BUILTIN_VPERMILPS_MASK,
+ IX86_BUILTIN_VPERMILPD256_MASK,
+ IX86_BUILTIN_VPERMILPS256_MASK,
+ IX86_BUILTIN_BLENDMQ256,
+ IX86_BUILTIN_BLENDMD256,
+ IX86_BUILTIN_BLENDMPD256,
+ IX86_BUILTIN_BLENDMPS256,
+ IX86_BUILTIN_BLENDMQ128,
+ IX86_BUILTIN_BLENDMD128,
+ IX86_BUILTIN_BLENDMPD128,
+ IX86_BUILTIN_BLENDMPS128,
+ IX86_BUILTIN_BLENDMW256,
+ IX86_BUILTIN_BLENDMB256,
+ IX86_BUILTIN_BLENDMW128,
+ IX86_BUILTIN_BLENDMB128,
+ IX86_BUILTIN_PMULLD256_MASK,
+ IX86_BUILTIN_PMULLD128_MASK,
+ IX86_BUILTIN_PMULUDQ256_MASK,
+ IX86_BUILTIN_PMULDQ256_MASK,
+ IX86_BUILTIN_PMULDQ128_MASK,
+ IX86_BUILTIN_PMULUDQ128_MASK,
+ IX86_BUILTIN_CVTPD2PS256_MASK,
+ IX86_BUILTIN_CVTPD2PS_MASK,
+ IX86_BUILTIN_VPERMVARSI256_MASK,
+ IX86_BUILTIN_VPERMVARDI256_MASK,
+ IX86_BUILTIN_VPERMDI256_MASK,
+ IX86_BUILTIN_CMPQ256,
+ IX86_BUILTIN_CMPD256,
+ IX86_BUILTIN_UCMPQ256,
+ IX86_BUILTIN_UCMPD256,
+ IX86_BUILTIN_CMPB256,
+ IX86_BUILTIN_CMPW256,
+ IX86_BUILTIN_UCMPB256,
+ IX86_BUILTIN_UCMPW256,
+ IX86_BUILTIN_CMPPD256_MASK,
+ IX86_BUILTIN_CMPPS256_MASK,
+ IX86_BUILTIN_CMPQ128,
+ IX86_BUILTIN_CMPD128,
+ IX86_BUILTIN_UCMPQ128,
+ IX86_BUILTIN_UCMPD128,
+ IX86_BUILTIN_CMPB128,
+ IX86_BUILTIN_CMPW128,
+ IX86_BUILTIN_UCMPB128,
+ IX86_BUILTIN_UCMPW128,
+ IX86_BUILTIN_CMPPD128_MASK,
+ IX86_BUILTIN_CMPPS128_MASK,
+
+ IX86_BUILTIN_GATHER3SIV8SF,
+ IX86_BUILTIN_GATHER3SIV4SF,
+ IX86_BUILTIN_GATHER3SIV4DF,
+ IX86_BUILTIN_GATHER3SIV2DF,
+ IX86_BUILTIN_GATHER3DIV8SF,
+ IX86_BUILTIN_GATHER3DIV4SF,
+ IX86_BUILTIN_GATHER3DIV4DF,
+ IX86_BUILTIN_GATHER3DIV2DF,
+ IX86_BUILTIN_GATHER3SIV8SI,
+ IX86_BUILTIN_GATHER3SIV4SI,
+ IX86_BUILTIN_GATHER3SIV4DI,
+ IX86_BUILTIN_GATHER3SIV2DI,
+ IX86_BUILTIN_GATHER3DIV8SI,
+ IX86_BUILTIN_GATHER3DIV4SI,
+ IX86_BUILTIN_GATHER3DIV4DI,
+ IX86_BUILTIN_GATHER3DIV2DI,
+ IX86_BUILTIN_SCATTERSIV8SF,
+ IX86_BUILTIN_SCATTERSIV4SF,
+ IX86_BUILTIN_SCATTERSIV4DF,
+ IX86_BUILTIN_SCATTERSIV2DF,
+ IX86_BUILTIN_SCATTERDIV8SF,
+ IX86_BUILTIN_SCATTERDIV4SF,
+ IX86_BUILTIN_SCATTERDIV4DF,
+ IX86_BUILTIN_SCATTERDIV2DF,
+ IX86_BUILTIN_SCATTERSIV8SI,
+ IX86_BUILTIN_SCATTERSIV4SI,
+ IX86_BUILTIN_SCATTERSIV4DI,
+ IX86_BUILTIN_SCATTERSIV2DI,
+ IX86_BUILTIN_SCATTERDIV8SI,
+ IX86_BUILTIN_SCATTERDIV4SI,
+ IX86_BUILTIN_SCATTERDIV4DI,
+ IX86_BUILTIN_SCATTERDIV2DI,
+
+ /* AVX512DQ. */
+ IX86_BUILTIN_RANGESD128,
+ IX86_BUILTIN_RANGESS128,
+ IX86_BUILTIN_KUNPCKWD,
+ IX86_BUILTIN_KUNPCKDQ,
+ IX86_BUILTIN_BROADCASTF32x2_512,
+ IX86_BUILTIN_BROADCASTI32x2_512,
+ IX86_BUILTIN_BROADCASTF64X2_512,
+ IX86_BUILTIN_BROADCASTI64X2_512,
+ IX86_BUILTIN_BROADCASTF32X8_512,
+ IX86_BUILTIN_BROADCASTI32X8_512,
+ IX86_BUILTIN_EXTRACTF64X2_512,
+ IX86_BUILTIN_EXTRACTF32X8,
+ IX86_BUILTIN_EXTRACTI64X2_512,
+ IX86_BUILTIN_EXTRACTI32X8,
+ IX86_BUILTIN_REDUCEPD512_MASK,
+ IX86_BUILTIN_REDUCEPS512_MASK,
+ IX86_BUILTIN_PMULLQ512,
+ IX86_BUILTIN_XORPD512,
+ IX86_BUILTIN_XORPS512,
+ IX86_BUILTIN_ORPD512,
+ IX86_BUILTIN_ORPS512,
+ IX86_BUILTIN_ANDPD512,
+ IX86_BUILTIN_ANDPS512,
+ IX86_BUILTIN_ANDNPD512,
+ IX86_BUILTIN_ANDNPS512,
+ IX86_BUILTIN_INSERTF32X8,
+ IX86_BUILTIN_INSERTI32X8,
+ IX86_BUILTIN_INSERTF64X2_512,
+ IX86_BUILTIN_INSERTI64X2_512,
+ IX86_BUILTIN_FPCLASSPD512,
+ IX86_BUILTIN_FPCLASSPS512,
+ IX86_BUILTIN_CVTD2MASK512,
+ IX86_BUILTIN_CVTQ2MASK512,
+ IX86_BUILTIN_CVTMASK2D512,
+ IX86_BUILTIN_CVTMASK2Q512,
+ IX86_BUILTIN_CVTPD2QQ512,
+ IX86_BUILTIN_CVTPS2QQ512,
+ IX86_BUILTIN_CVTPD2UQQ512,
+ IX86_BUILTIN_CVTPS2UQQ512,
+ IX86_BUILTIN_CVTQQ2PS512,
+ IX86_BUILTIN_CVTUQQ2PS512,
+ IX86_BUILTIN_CVTQQ2PD512,
+ IX86_BUILTIN_CVTUQQ2PD512,
+ IX86_BUILTIN_CVTTPS2QQ512,
+ IX86_BUILTIN_CVTTPS2UQQ512,
+ IX86_BUILTIN_CVTTPD2QQ512,
+ IX86_BUILTIN_CVTTPD2UQQ512,
+ IX86_BUILTIN_RANGEPS512,
+ IX86_BUILTIN_RANGEPD512,
+
+ /* AVX512BW. */
+ IX86_BUILTIN_PACKUSDW512,
+ IX86_BUILTIN_PACKSSDW512,
+ IX86_BUILTIN_LOADDQUHI512_MASK,
+ IX86_BUILTIN_LOADDQUQI512_MASK,
+ IX86_BUILTIN_PSLLDQ512,
+ IX86_BUILTIN_PSRLDQ512,
+ IX86_BUILTIN_STOREDQUHI512_MASK,
+ IX86_BUILTIN_STOREDQUQI512_MASK,
+ IX86_BUILTIN_PALIGNR512,
+ IX86_BUILTIN_PALIGNR512_MASK,
+ IX86_BUILTIN_MOVDQUHI512_MASK,
+ IX86_BUILTIN_MOVDQUQI512_MASK,
+ IX86_BUILTIN_PSADBW512,
+ IX86_BUILTIN_DBPSADBW512,
+ IX86_BUILTIN_PBROADCASTB512,
+ IX86_BUILTIN_PBROADCASTB512_GPR,
+ IX86_BUILTIN_PBROADCASTW512,
+ IX86_BUILTIN_PBROADCASTW512_GPR,
+ IX86_BUILTIN_PMOVSXBW512_MASK,
+ IX86_BUILTIN_PMOVZXBW512_MASK,
+ IX86_BUILTIN_VPERMVARHI512_MASK,
+ IX86_BUILTIN_VPERMT2VARHI512,
+ IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
+ IX86_BUILTIN_VPERMI2VARHI512,
+ IX86_BUILTIN_PAVGB512,
+ IX86_BUILTIN_PAVGW512,
+ IX86_BUILTIN_PADDB512,
+ IX86_BUILTIN_PSUBB512,
+ IX86_BUILTIN_PSUBSB512,
+ IX86_BUILTIN_PADDSB512,
+ IX86_BUILTIN_PSUBUSB512,
+ IX86_BUILTIN_PADDUSB512,
+ IX86_BUILTIN_PSUBW512,
+ IX86_BUILTIN_PADDW512,
+ IX86_BUILTIN_PSUBSW512,
+ IX86_BUILTIN_PADDSW512,
+ IX86_BUILTIN_PSUBUSW512,
+ IX86_BUILTIN_PADDUSW512,
+ IX86_BUILTIN_PMAXUW512,
+ IX86_BUILTIN_PMAXSW512,
+ IX86_BUILTIN_PMINUW512,
+ IX86_BUILTIN_PMINSW512,
+ IX86_BUILTIN_PMAXUB512,
+ IX86_BUILTIN_PMAXSB512,
+ IX86_BUILTIN_PMINUB512,
+ IX86_BUILTIN_PMINSB512,
+ IX86_BUILTIN_PMOVWB512,
+ IX86_BUILTIN_PMOVSWB512,
+ IX86_BUILTIN_PMOVUSWB512,
+ IX86_BUILTIN_PMULHRSW512_MASK,
+ IX86_BUILTIN_PMULHUW512_MASK,
+ IX86_BUILTIN_PMULHW512_MASK,
+ IX86_BUILTIN_PMULLW512_MASK,
+ IX86_BUILTIN_PSLLWI512_MASK,
+ IX86_BUILTIN_PSLLW512_MASK,
+ IX86_BUILTIN_PACKSSWB512,
+ IX86_BUILTIN_PACKUSWB512,
+ IX86_BUILTIN_PSRAVV32HI,
+ IX86_BUILTIN_PMADDUBSW512_MASK,
+ IX86_BUILTIN_PMADDWD512_MASK,
+ IX86_BUILTIN_PSRLVV32HI,
+ IX86_BUILTIN_PUNPCKHBW512,
+ IX86_BUILTIN_PUNPCKHWD512,
+ IX86_BUILTIN_PUNPCKLBW512,
+ IX86_BUILTIN_PUNPCKLWD512,
+ IX86_BUILTIN_PSHUFB512,
+ IX86_BUILTIN_PSHUFHW512,
+ IX86_BUILTIN_PSHUFLW512,
+ IX86_BUILTIN_PSRAWI512,
+ IX86_BUILTIN_PSRAW512,
+ IX86_BUILTIN_PSRLWI512,
+ IX86_BUILTIN_PSRLW512,
+ IX86_BUILTIN_CVTB2MASK512,
+ IX86_BUILTIN_CVTW2MASK512,
+ IX86_BUILTIN_CVTMASK2B512,
+ IX86_BUILTIN_CVTMASK2W512,
+ IX86_BUILTIN_PCMPEQB512_MASK,
+ IX86_BUILTIN_PCMPEQW512_MASK,
+ IX86_BUILTIN_PCMPGTB512_MASK,
+ IX86_BUILTIN_PCMPGTW512_MASK,
+ IX86_BUILTIN_PTESTMB512,
+ IX86_BUILTIN_PTESTMW512,
+ IX86_BUILTIN_PTESTNMB512,
+ IX86_BUILTIN_PTESTNMW512,
+ IX86_BUILTIN_PSLLVV32HI,
+ IX86_BUILTIN_PABSB512,
+ IX86_BUILTIN_PABSW512,
+ IX86_BUILTIN_BLENDMW512,
+ IX86_BUILTIN_BLENDMB512,
+ IX86_BUILTIN_CMPB512,
+ IX86_BUILTIN_CMPW512,
+ IX86_BUILTIN_UCMPB512,
+ IX86_BUILTIN_UCMPW512,
+
/* Alternate 4 and 8 element gather/scatter for the vectorizer
where all operands are 32-byte or 64-byte wide respectively. */
IX86_BUILTIN_GATHERALTSIV4DF,
@@ -29330,6 +30323,108 @@ static const struct builtin_description bdesc_special_args[] =
{ OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
{ OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
{ OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
+
+ /* AVX512BW */
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
+
+ /* AVX512VL */
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
};
/* Builtins with variable number of arguments. */
@@ -30389,6 +31484,852 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
+
+ /* AVX512VL. */
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv4di_mask, "__builtin_ia32_pbroadcastq256_mem_mask", IX86_BUILTIN_PBROADCASTQ256_MEM_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv2di_mask, "__builtin_ia32_pbroadcastq128_mem_mask", IX86_BUILTIN_PBROADCASTQ128_MEM_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df, "__builtin_ia32_fixupimmpd256", IX86_BUILTIN_FIXUPIMMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf, "__builtin_ia32_fixupimmps256", IX86_BUILTIN_FIXUPIMMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df, "__builtin_ia32_fixupimmpd128", IX86_BUILTIN_FIXUPIMMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf, "__builtin_ia32_fixupimmps128", IX86_BUILTIN_FIXUPIMMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
+
+ /* AVX512DQ. */
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
+
+ /* AVX512BW. */
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
};
/* Builtins with rounding support. */
@@ -30526,6 +32467,24 @@ static const struct builtin_description bdesc_round_args[] =
{ OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
{ OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
{ OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
+
+ /* AVX512DQ. */
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
};
/* FMA4 and XOP. */
@@ -33803,6 +35762,28 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V4DI_FTYPE_V4SI:
case V4DI_FTYPE_V2DI:
case HI_FTYPE_HI:
+ case HI_FTYPE_V16QI:
+ case SI_FTYPE_V32QI:
+ case DI_FTYPE_V64QI:
+ case V16QI_FTYPE_HI:
+ case V32QI_FTYPE_SI:
+ case V64QI_FTYPE_DI:
+ case V8HI_FTYPE_QI:
+ case V16HI_FTYPE_HI:
+ case V32HI_FTYPE_SI:
+ case V4SI_FTYPE_QI:
+ case V8SI_FTYPE_QI:
+ case V4SI_FTYPE_HI:
+ case V8SI_FTYPE_HI:
+ case QI_FTYPE_V8HI:
+ case HI_FTYPE_V16HI:
+ case SI_FTYPE_V32HI:
+ case QI_FTYPE_V4SI:
+ case QI_FTYPE_V8SI:
+ case HI_FTYPE_V16SI:
+ case QI_FTYPE_V2DI:
+ case QI_FTYPE_V4DI:
+ case QI_FTYPE_V8DI:
case UINT_FTYPE_V2DF:
case UINT_FTYPE_V4SF:
case UINT64_FTYPE_V2DF:
@@ -33810,6 +35791,8 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V16QI_FTYPE_V8DI:
case V16HI_FTYPE_V16SI:
case V16SI_FTYPE_HI:
+ case V2DI_FTYPE_QI:
+ case V4DI_FTYPE_QI:
case V16SI_FTYPE_V16SI:
case V16SI_FTYPE_INT:
case V16SF_FTYPE_FLOAT:
@@ -33821,7 +35804,6 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V8HI_FTYPE_V8DI:
case V8UHI_FTYPE_V8UHI:
case V8SI_FTYPE_V8DI:
- case V8USI_FTYPE_V8USI:
case V8SF_FTYPE_V8DF:
case V8DI_FTYPE_QI:
case V8DI_FTYPE_INT64:
@@ -33902,6 +35884,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V4DI_FTYPE_V8SI_V8SI:
case V4UDI_FTYPE_V8USI_V8USI:
case QI_FTYPE_V8DI_V8DI:
+ case V8DI_FTYPE_V64QI_V64QI:
case HI_FTYPE_V16SI_V16SI:
if (comparison == UNKNOWN)
return ix86_expand_binop_builtin (icode, exp, target);
@@ -33941,6 +35924,8 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case UINT16_FTYPE_UINT16_INT:
case UINT8_FTYPE_UINT8_INT:
case HI_FTYPE_HI_HI:
+ case SI_FTYPE_SI_SI:
+ case DI_FTYPE_DI_DI:
case V16SI_FTYPE_V8DF_V8DF:
nargs = 2;
break;
@@ -33954,6 +35939,11 @@ ix86_expand_args_builtin (const struct builtin_description *d,
rmode = V2TImode;
nargs_constant = 1;
break;
+ case V8DI_FTYPE_V8DI_INT_CONVERT:
+ nargs = 2;
+ rmode = V4TImode;
+ nargs_constant = 1;
+ break;
case V8HI_FTYPE_V8HI_INT:
case V8HI_FTYPE_V8SF_INT:
case V16HI_FTYPE_V16SF_INT:
@@ -33979,6 +35969,8 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V2DI_FTYPE_V4DI_INT:
case V4DI_FTYPE_V8DI_INT:
case HI_FTYPE_HI_INT:
+ case QI_FTYPE_V4SF_INT:
+ case QI_FTYPE_V2DF_INT:
nargs = 2;
nargs_constant = 1;
break;
@@ -34003,20 +35995,118 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V16SI_FTYPE_V16HI_V16SI_HI:
case V16SI_FTYPE_V16QI_V16SI_HI:
case V16SI_FTYPE_V16SF_V16SI_HI:
+ case V8SF_FTYPE_V4SF_V8SF_QI:
+ case V4DF_FTYPE_V2DF_V4DF_QI:
+ case V8SI_FTYPE_V4SI_V8SI_QI:
+ case V8SI_FTYPE_SI_V8SI_QI:
+ case V4SI_FTYPE_V4SI_V4SI_QI:
+ case V4SI_FTYPE_SI_V4SI_QI:
+ case V4DI_FTYPE_V2DI_V4DI_QI:
+ case V4DI_FTYPE_DI_V4DI_QI:
+ case V2DI_FTYPE_V2DI_V2DI_QI:
+ case V2DI_FTYPE_DI_V2DI_QI:
+ case V64QI_FTYPE_V64QI_V64QI_DI:
+ case V64QI_FTYPE_V16QI_V64QI_DI:
+ case V64QI_FTYPE_QI_V64QI_DI:
+ case V32QI_FTYPE_V32QI_V32QI_SI:
+ case V32QI_FTYPE_V16QI_V32QI_SI:
+ case V32QI_FTYPE_QI_V32QI_SI:
+ case V16QI_FTYPE_V16QI_V16QI_HI:
+ case V16QI_FTYPE_QI_V16QI_HI:
+ case V32HI_FTYPE_V8HI_V32HI_SI:
+ case V32HI_FTYPE_HI_V32HI_SI:
+ case V16HI_FTYPE_V8HI_V16HI_HI:
+ case V16HI_FTYPE_HI_V16HI_HI:
+ case V8HI_FTYPE_V8HI_V8HI_QI:
+ case V8HI_FTYPE_HI_V8HI_QI:
+ case V8SF_FTYPE_V8HI_V8SF_QI:
+ case V4SF_FTYPE_V8HI_V4SF_QI:
+ case V8SI_FTYPE_V8SF_V8SI_QI:
+ case V4SI_FTYPE_V4SF_V4SI_QI:
+ case V8DI_FTYPE_V8SF_V8DI_QI:
+ case V4DI_FTYPE_V4SF_V4DI_QI:
+ case V2DI_FTYPE_V4SF_V2DI_QI:
+ case V8SF_FTYPE_V8DI_V8SF_QI:
+ case V4SF_FTYPE_V4DI_V4SF_QI:
+ case V4SF_FTYPE_V2DI_V4SF_QI:
+ case V8DF_FTYPE_V8DI_V8DF_QI:
+ case V4DF_FTYPE_V4DI_V4DF_QI:
+ case V2DF_FTYPE_V2DI_V2DF_QI:
+ case V16QI_FTYPE_V8HI_V16QI_QI:
+ case V16QI_FTYPE_V16HI_V16QI_HI:
+ case V16QI_FTYPE_V4SI_V16QI_QI:
+ case V16QI_FTYPE_V8SI_V16QI_QI:
+ case V8HI_FTYPE_V4SI_V8HI_QI:
+ case V8HI_FTYPE_V8SI_V8HI_QI:
+ case V16QI_FTYPE_V2DI_V16QI_QI:
+ case V16QI_FTYPE_V4DI_V16QI_QI:
+ case V8HI_FTYPE_V2DI_V8HI_QI:
+ case V8HI_FTYPE_V4DI_V8HI_QI:
+ case V4SI_FTYPE_V2DI_V4SI_QI:
+ case V4SI_FTYPE_V4DI_V4SI_QI:
+ case V32QI_FTYPE_V32HI_V32QI_SI:
+ case HI_FTYPE_V16QI_V16QI_HI:
+ case SI_FTYPE_V32QI_V32QI_SI:
+ case DI_FTYPE_V64QI_V64QI_DI:
+ case QI_FTYPE_V8HI_V8HI_QI:
+ case HI_FTYPE_V16HI_V16HI_HI:
+ case SI_FTYPE_V32HI_V32HI_SI:
+ case QI_FTYPE_V4SI_V4SI_QI:
+ case QI_FTYPE_V8SI_V8SI_QI:
+ case QI_FTYPE_V2DI_V2DI_QI:
+ case QI_FTYPE_V4DI_V4DI_QI:
+ case V4SF_FTYPE_V2DF_V4SF_QI:
+ case V4SF_FTYPE_V4DF_V4SF_QI:
+ nargs = 3;
case V16SI_FTYPE_V16SI_V16SI_HI:
case V16SI_FTYPE_V16SI_V16SI_V16SI:
case V16SI_FTYPE_V4SI_V16SI_HI:
case V2DI_FTYPE_V2DI_V2DI_V2DI:
+ case V2DI_FTYPE_V4SI_V2DI_QI:
+ case V2DI_FTYPE_V8HI_V2DI_QI:
+ case V2DI_FTYPE_V16QI_V2DI_QI:
+ case V4DI_FTYPE_V4DI_V4DI_QI:
+ case V4DI_FTYPE_V4SI_V4DI_QI:
+ case V4DI_FTYPE_V8HI_V4DI_QI:
+ case V4DI_FTYPE_V16QI_V4DI_QI:
+ case V8DI_FTYPE_V8DF_V8DI_QI:
+ case V4DI_FTYPE_V4DF_V4DI_QI:
+ case V2DI_FTYPE_V2DF_V2DI_QI:
+ case V4SI_FTYPE_V4DF_V4SI_QI:
+ case V4SI_FTYPE_V2DF_V4SI_QI:
+ case V4SI_FTYPE_V8HI_V4SI_QI:
+ case V4SI_FTYPE_V16QI_V4SI_QI:
+ case V8SI_FTYPE_V8SI_V8SI_V8SI:
case V4DI_FTYPE_V4DI_V4DI_V4DI:
case V8DF_FTYPE_V2DF_V8DF_QI:
case V8DF_FTYPE_V4DF_V8DF_QI:
case V8DF_FTYPE_V8DF_V8DF_QI:
case V8DF_FTYPE_V8DF_V8DF_V8DF:
+ case V8SF_FTYPE_V8SF_V8SF_QI:
+ case V8SF_FTYPE_V8SI_V8SF_QI:
+ case V4DF_FTYPE_V4DF_V4DF_QI:
+ case V4SF_FTYPE_V4SF_V4SF_QI:
+ case V2DF_FTYPE_V2DF_V2DF_QI:
+ case V2DF_FTYPE_V4SF_V2DF_QI:
+ case V2DF_FTYPE_V4SI_V2DF_QI:
+ case V4SF_FTYPE_V4SI_V4SF_QI:
+ case V4DF_FTYPE_V4SF_V4DF_QI:
+ case V4DF_FTYPE_V4SI_V4DF_QI:
+ case V8SI_FTYPE_V8SI_V8SI_QI:
+ case V8SI_FTYPE_V8HI_V8SI_QI:
+ case V8SI_FTYPE_V16QI_V8SI_QI:
case V8DF_FTYPE_V8DF_V8DI_V8DF:
case V8DF_FTYPE_V8DI_V8DF_V8DF:
case V8DF_FTYPE_V8SF_V8DF_QI:
case V8DF_FTYPE_V8SI_V8DF_QI:
case V8DI_FTYPE_DI_V8DI_QI:
+ case V16SF_FTYPE_V8SF_V16SF_HI:
+ case V16SI_FTYPE_V8SI_V16SI_HI:
+ case V16HI_FTYPE_V16HI_V16HI_HI:
+ case V8HI_FTYPE_V16QI_V8HI_QI:
+ case V16HI_FTYPE_V16QI_V16HI_HI:
+ case V32HI_FTYPE_V32HI_V32HI_SI:
+ case V32HI_FTYPE_V32QI_V32HI_SI:
case V8DI_FTYPE_V16QI_V8DI_QI:
case V8DI_FTYPE_V2DI_V8DI_QI:
case V8DI_FTYPE_V4DI_V8DI_QI:
@@ -34078,13 +36168,80 @@ ix86_expand_args_builtin (const struct builtin_description *d,
nargs = 3;
nargs_constant = 2;
break;
+ case V8DI_FTYPE_V8DI_V8DI_INT_CONVERT:
+ nargs = 3;
+ rmode = V8DImode;
+ nargs_constant = 1;
+ break;
+ case V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT:
+ nargs = 5;
+ rmode = V8DImode;
+ mask_pos = 2;
+ nargs_constant = 1;
+ break;
+ case QI_FTYPE_V8DF_INT_QI:
+ case QI_FTYPE_V4DF_INT_QI:
+ case QI_FTYPE_V2DF_INT_QI:
+ case HI_FTYPE_V16SF_INT_HI:
+ case QI_FTYPE_V8SF_INT_QI:
+ case QI_FTYPE_V4SF_INT_QI:
+ nargs = 3;
+ mask_pos = 1;
+ nargs_constant = 1;
+ break;
+ case V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT:
+ nargs = 5;
+ rmode = V4DImode;
+ mask_pos = 2;
+ nargs_constant = 1;
+ break;
+ case V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT:
+ nargs = 5;
+ rmode = V2DImode;
+ mask_pos = 2;
+ nargs_constant = 1;
+ break;
+ case V32QI_FTYPE_V32QI_V32QI_V32QI_SI:
+ case V32HI_FTYPE_V32HI_V32HI_V32HI_SI:
+ case V32HI_FTYPE_V64QI_V64QI_V32HI_SI:
+ case V16SI_FTYPE_V32HI_V32HI_V16SI_HI:
+ case V64QI_FTYPE_V64QI_V64QI_V64QI_DI:
+ case V32HI_FTYPE_V32HI_V8HI_V32HI_SI:
+ case V16HI_FTYPE_V16HI_V8HI_V16HI_HI:
+ case V8SI_FTYPE_V8SI_V4SI_V8SI_QI:
+ case V4DI_FTYPE_V4DI_V2DI_V4DI_QI:
+ case V64QI_FTYPE_V32HI_V32HI_V64QI_DI:
+ case V32QI_FTYPE_V16HI_V16HI_V32QI_SI:
+ case V16QI_FTYPE_V8HI_V8HI_V16QI_HI:
+ case V32HI_FTYPE_V16SI_V16SI_V32HI_SI:
+ case V16HI_FTYPE_V8SI_V8SI_V16HI_HI:
+ case V8HI_FTYPE_V4SI_V4SI_V8HI_QI:
+ case V4DF_FTYPE_V4DF_V4DI_V4DF_QI:
+ case V8SF_FTYPE_V8SF_V8SI_V8SF_QI:
+ case V4SF_FTYPE_V4SF_V4SI_V4SF_QI:
+ case V2DF_FTYPE_V2DF_V2DI_V2DF_QI:
+ case V2DI_FTYPE_V4SI_V4SI_V2DI_QI:
+ case V4DI_FTYPE_V8SI_V8SI_V4DI_QI:
+ case V4DF_FTYPE_V4DI_V4DF_V4DF_QI:
+ case V8SF_FTYPE_V8SI_V8SF_V8SF_QI:
+ case V2DF_FTYPE_V2DI_V2DF_V2DF_QI:
+ case V4SF_FTYPE_V4SI_V4SF_V4SF_QI:
case V16SF_FTYPE_V16SF_V16SF_V16SF_HI:
case V16SF_FTYPE_V16SF_V16SI_V16SF_HI:
case V16SF_FTYPE_V16SI_V16SF_V16SF_HI:
case V16SI_FTYPE_V16SI_V16SI_V16SI_HI:
case V16SI_FTYPE_V16SI_V4SI_V16SI_HI:
+ case V8HI_FTYPE_V8HI_V8HI_V8HI_QI:
+ case V8SI_FTYPE_V8SI_V8SI_V8SI_QI:
+ case V4SI_FTYPE_V4SI_V4SI_V4SI_QI:
+ case V8SF_FTYPE_V8SF_V8SF_V8SF_QI:
+ case V16QI_FTYPE_V16QI_V16QI_V16QI_HI:
+ case V16HI_FTYPE_V16HI_V16HI_V16HI_HI:
+ case V2DI_FTYPE_V2DI_V2DI_V2DI_QI:
case V2DF_FTYPE_V2DF_V2DF_V2DF_QI:
case V2DF_FTYPE_V2DF_V4SF_V2DF_QI:
+ case V4DI_FTYPE_V4DI_V4DI_V4DI_QI:
+ case V4DF_FTYPE_V4DF_V4DF_V4DF_QI:
case V4SF_FTYPE_V4SF_V2DF_V4SF_QI:
case V4SF_FTYPE_V4SF_V4SF_V4SF_QI:
case V8DF_FTYPE_V8DF_V8DF_V8DF_QI:
@@ -34094,6 +36251,10 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V8DI_FTYPE_V8DI_SI_V8DI_V8DI:
case V8DI_FTYPE_V8DI_V2DI_V8DI_QI:
case V8DI_FTYPE_V8DI_V8DI_V8DI_QI:
+ case V8HI_FTYPE_V16QI_V16QI_V8HI_QI:
+ case V16HI_FTYPE_V32QI_V32QI_V16HI_HI:
+ case V8SI_FTYPE_V16HI_V16HI_V8SI_QI:
+ case V4SI_FTYPE_V8HI_V8HI_V4SI_QI:
nargs = 4;
break;
case V2DF_FTYPE_V2DF_V2DF_V2DI_INT:
@@ -34104,8 +36265,20 @@ ix86_expand_args_builtin (const struct builtin_description *d,
nargs = 4;
nargs_constant = 1;
break;
+ case QI_FTYPE_V4DI_V4DI_INT_QI:
+ case QI_FTYPE_V8SI_V8SI_INT_QI:
+ case QI_FTYPE_V4DF_V4DF_INT_QI:
+ case QI_FTYPE_V8SF_V8SF_INT_QI:
+ case QI_FTYPE_V2DI_V2DI_INT_QI:
+ case QI_FTYPE_V4SI_V4SI_INT_QI:
case QI_FTYPE_V2DF_V2DF_INT_QI:
case QI_FTYPE_V4SF_V4SF_INT_QI:
+ case DI_FTYPE_V64QI_V64QI_INT_DI:
+ case SI_FTYPE_V32QI_V32QI_INT_SI:
+ case HI_FTYPE_V16QI_V16QI_INT_HI:
+ case SI_FTYPE_V32HI_V32HI_INT_SI:
+ case HI_FTYPE_V16HI_V16HI_INT_HI:
+ case QI_FTYPE_V8HI_V8HI_INT_QI:
nargs = 4;
mask_pos = 1;
nargs_constant = 1;
@@ -34126,6 +36299,27 @@ ix86_expand_args_builtin (const struct builtin_description *d,
nargs = 4;
nargs_constant = 1;
break;
+ case V8SF_FTYPE_V8SF_INT_V8SF_QI:
+ case V4SF_FTYPE_V4SF_INT_V4SF_QI:
+ case V2DF_FTYPE_V4DF_INT_V2DF_QI:
+ case V2DI_FTYPE_V4DI_INT_V2DI_QI:
+ case V8SF_FTYPE_V16SF_INT_V8SF_QI:
+ case V8SI_FTYPE_V16SI_INT_V8SI_QI:
+ case V2DF_FTYPE_V8DF_INT_V2DF_QI:
+ case V2DI_FTYPE_V8DI_INT_V2DI_QI:
+ case V4SF_FTYPE_V8SF_INT_V4SF_QI:
+ case V4SI_FTYPE_V8SI_INT_V4SI_QI:
+ case V8HI_FTYPE_V8SF_INT_V8HI_QI:
+ case V8HI_FTYPE_V4SF_INT_V8HI_QI:
+ case V32HI_FTYPE_V32HI_INT_V32HI_SI:
+ case V16HI_FTYPE_V16HI_INT_V16HI_HI:
+ case V8HI_FTYPE_V8HI_INT_V8HI_QI:
+ case V4DI_FTYPE_V4DI_INT_V4DI_QI:
+ case V2DI_FTYPE_V2DI_INT_V2DI_QI:
+ case V8SI_FTYPE_V8SI_INT_V8SI_QI:
+ case V4SI_FTYPE_V4SI_INT_V4SI_QI:
+ case V4DF_FTYPE_V4DF_INT_V4DF_QI:
+ case V2DF_FTYPE_V2DF_INT_V2DF_QI:
case V8DF_FTYPE_V8DF_INT_V8DF_QI:
case V16SF_FTYPE_V16SF_INT_V16SF_HI:
case V16HI_FTYPE_V16SF_INT_V16HI_HI:
@@ -34149,6 +36343,23 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI:
case V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI:
case V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI:
+ case V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI:
+ case V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI:
+ case V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI:
+ case V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI:
+ case V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI:
+ case V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI:
+ case V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI:
+ case V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI:
+ case V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI:
+ case V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI:
+ case V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI:
+ case V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI:
+ case V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI:
+ case V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI:
+ case V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI:
+ case V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI:
+ case V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI:
nargs = 5;
mask_pos = 2;
nargs_constant = 1;
@@ -34158,6 +36369,13 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI:
case V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI:
case V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI:
+ case V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI:
+ case V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI:
+ case V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI:
+ case V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI:
+ case V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI:
+ case V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI:
+ nargs = 5;
nargs = 5;
mask_pos = 1;
nargs_constant = 1;
@@ -34606,7 +36824,11 @@ ix86_expand_round_builtin (const struct builtin_description *d,
case V8SF_FTYPE_V8DF_V8SF_QI_INT:
case V8DF_FTYPE_V8DF_V8DF_QI_INT:
case V8SI_FTYPE_V8DF_V8SI_QI_INT:
+ case V8DI_FTYPE_V8DF_V8DI_QI_INT:
+ case V8SF_FTYPE_V8DI_V8SF_QI_INT:
+ case V8DF_FTYPE_V8DI_V8DF_QI_INT:
case V16SF_FTYPE_V16SF_V16SF_HI_INT:
+ case V8DI_FTYPE_V8SF_V8DI_QI_INT:
case V16SF_FTYPE_V16SI_V16SF_HI_INT:
case V16SI_FTYPE_V16SF_V16SI_HI_INT:
case V8DF_FTYPE_V8SF_V8DF_QI_INT:
@@ -34643,6 +36865,8 @@ ix86_expand_round_builtin (const struct builtin_description *d,
nargs_constant = 3;
nargs = 5;
break;
+ case V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT:
+ case V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT:
case V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI_INT:
case V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI_INT:
nargs = 6;
@@ -34905,7 +37129,11 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
case VOID_FTYPE_PV8DF_V8DF_QI:
case VOID_FTYPE_PV16SF_V16SF_HI:
case VOID_FTYPE_PV8DI_V8DI_QI:
+ case VOID_FTYPE_PV4DI_V4DI_QI:
+ case VOID_FTYPE_PV2DI_V2DI_QI:
case VOID_FTYPE_PV16SI_V16SI_HI:
+ case VOID_FTYPE_PV8SI_V8SI_QI:
+ case VOID_FTYPE_PV4SI_V4SI_QI:
switch (icode)
{
/* These builtins and instructions require the memory
@@ -34943,17 +37171,51 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
case VOID_FTYPE_PV16HI_V16SI_HI:
case VOID_FTYPE_PV16QI_V8DI_QI:
case VOID_FTYPE_PV16QI_V16SI_HI:
+ case VOID_FTYPE_PV4SI_V4DI_QI:
+ case VOID_FTYPE_PV4SI_V2DI_QI:
+ case VOID_FTYPE_PV8HI_V4DI_QI:
+ case VOID_FTYPE_PV8HI_V2DI_QI:
+ case VOID_FTYPE_PV8HI_V8SI_QI:
+ case VOID_FTYPE_PV8HI_V4SI_QI:
+ case VOID_FTYPE_PV16QI_V4DI_QI:
+ case VOID_FTYPE_PV16QI_V2DI_QI:
+ case VOID_FTYPE_PV16QI_V8SI_QI:
+ case VOID_FTYPE_PV16QI_V4SI_QI:
+ case VOID_FTYPE_PV8HI_V8HI_QI:
+ case VOID_FTYPE_PV16HI_V16HI_HI:
+ case VOID_FTYPE_PV32HI_V32HI_SI:
+ case VOID_FTYPE_PV16QI_V16QI_HI:
+ case VOID_FTYPE_PV32QI_V32QI_SI:
+ case VOID_FTYPE_PV64QI_V64QI_DI:
+ case VOID_FTYPE_PV4DF_V4DF_QI:
+ case VOID_FTYPE_PV2DF_V2DF_QI:
+ case VOID_FTYPE_PV8SF_V8SF_QI:
+ case VOID_FTYPE_PV4SF_V4SF_QI:
nargs = 2;
klass = store;
/* Reserve memory operand for target. */
memory = ARRAY_SIZE (args);
break;
+ case V4SF_FTYPE_PCV4SF_V4SF_QI:
+ case V8SF_FTYPE_PCV8SF_V8SF_QI:
case V16SF_FTYPE_PCV16SF_V16SF_HI:
+ case V4SI_FTYPE_PCV4SI_V4SI_QI:
+ case V8SI_FTYPE_PCV8SI_V8SI_QI:
case V16SI_FTYPE_PCV16SI_V16SI_HI:
+ case V2DF_FTYPE_PCV2DF_V2DF_QI:
+ case V4DF_FTYPE_PCV4DF_V4DF_QI:
case V8DF_FTYPE_PCV8DF_V8DF_QI:
+ case V2DI_FTYPE_PCV2DI_V2DI_QI:
+ case V4DI_FTYPE_PCV4DI_V4DI_QI:
case V8DI_FTYPE_PCV8DI_V8DI_QI:
case V2DF_FTYPE_PCDOUBLE_V2DF_QI:
case V4SF_FTYPE_PCFLOAT_V4SF_QI:
+ case V8HI_FTYPE_PCV8HI_V8HI_QI:
+ case V16HI_FTYPE_PCV16HI_V16HI_HI:
+ case V32HI_FTYPE_PCV32HI_V32HI_SI:
+ case V16QI_FTYPE_PCV16QI_V16QI_HI:
+ case V32QI_FTYPE_PCV32QI_V32QI_SI:
+ case V64QI_FTYPE_PCV64QI_V64QI_DI:
nargs = 3;
klass = load;
memory = 0;
diff --git a/gcc/tree-core.h b/gcc/tree-core.h
index b69312b..a639487 100644
--- a/gcc/tree-core.h
+++ b/gcc/tree-core.h
@@ -1539,7 +1539,7 @@ struct GTY(()) tree_function_decl {
DECL_FUNCTION_CODE. Otherwise unused.
??? The bitfield needs to be able to hold all target function
codes as well. */
- ENUM_BITFIELD(built_in_function) function_code : 11;
+ ENUM_BITFIELD(built_in_function) function_code : 12;
ENUM_BITFIELD(built_in_class) built_in_class : 2;
unsigned static_ctor_flag : 1;
@@ -1563,7 +1563,7 @@ struct GTY(()) tree_function_decl {
unsigned has_debug_args_flag : 1;
unsigned tm_clone_flag : 1;
unsigned versioned_function : 1;
- /* No bits left. */
+ /* 31 bits left. */
};
struct GTY(()) tree_translation_unit_decl {
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH i386 AVX512] [81/n] Add new built-ins.
2014-10-20 13:50 [PATCH i386 AVX512] [81/n] Add new built-ins Kirill Yukhin
@ 2014-10-20 13:56 ` Jakub Jelinek
2014-10-21 9:19 ` Richard Biener
2014-10-21 14:09 ` Kirill Yukhin
2014-10-23 12:58 ` [PATCH i386 AVX512] [81.2/n] " Kirill Yukhin
1 sibling, 2 replies; 16+ messages in thread
From: Jakub Jelinek @ 2014-10-20 13:56 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Uros Bizjak, Richard Henderson, GCC Patches
On Mon, Oct 20, 2014 at 05:41:25PM +0400, Kirill Yukhin wrote:
> Hello,
> This patch adds (almost) all built-ins needed by
> AVX-512VL,BW,DQ intrinsics.
>
> Main questionable hunk is:
>
> diff --git a/gcc/tree-core.h b/gcc/tree-core.h
> index b69312b..a639487 100644
> --- a/gcc/tree-core.h
> +++ b/gcc/tree-core.h
> @@ -1539,7 +1539,7 @@ struct GTY(()) tree_function_decl {
> DECL_FUNCTION_CODE. Otherwise unused.
> ??? The bitfield needs to be able to hold all target function
> codes as well. */
> - ENUM_BITFIELD(built_in_function) function_code : 11;
> + ENUM_BITFIELD(built_in_function) function_code : 12;
> ENUM_BITFIELD(built_in_class) built_in_class : 2;
>
> unsigned static_ctor_flag : 1;
Well, decl_with_vis has 15 unused bits, so instead of growing
FUNCTION_DECL significantly, might be better to move one of the
flags to decl_with_vis and just document that it applies to FUNCTION_DECLs
only. Or move some flag to cgraph if possible.
But seeing e.g.
IX86_BUILTIN_FIXUPIMMPD256, IX86_BUILTIN_FIXUPIMMPD256_MASK,
IX86_BUILTIN_FIXUPIMMPD256_MASKZ
etc. I wonder if you really need that many builtins, weren't we adding
for avx512f just single builtin instead of 3 different ones, always
providing mask argument and depending on whether it is all ones, etc.
figuring out what kind of masking should be performed?
Jakub
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH i386 AVX512] [81/n] Add new built-ins.
2014-10-20 13:56 ` Jakub Jelinek
@ 2014-10-21 9:19 ` Richard Biener
2014-10-21 14:19 ` Kirill Yukhin
2014-10-21 14:09 ` Kirill Yukhin
1 sibling, 1 reply; 16+ messages in thread
From: Richard Biener @ 2014-10-21 9:19 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: Kirill Yukhin, Uros Bizjak, Richard Henderson, GCC Patches
On Mon, Oct 20, 2014 at 3:50 PM, Jakub Jelinek <jakub@redhat.com> wrote:
> On Mon, Oct 20, 2014 at 05:41:25PM +0400, Kirill Yukhin wrote:
>> Hello,
>> This patch adds (almost) all built-ins needed by
>> AVX-512VL,BW,DQ intrinsics.
>>
>> Main questionable hunk is:
>>
>> diff --git a/gcc/tree-core.h b/gcc/tree-core.h
>> index b69312b..a639487 100644
>> --- a/gcc/tree-core.h
>> +++ b/gcc/tree-core.h
>> @@ -1539,7 +1539,7 @@ struct GTY(()) tree_function_decl {
>> DECL_FUNCTION_CODE. Otherwise unused.
>> ??? The bitfield needs to be able to hold all target function
>> codes as well. */
>> - ENUM_BITFIELD(built_in_function) function_code : 11;
>> + ENUM_BITFIELD(built_in_function) function_code : 12;
>> ENUM_BITFIELD(built_in_class) built_in_class : 2;
>>
>> unsigned static_ctor_flag : 1;
>
> Well, decl_with_vis has 15 unused bits, so instead of growing
> FUNCTION_DECL significantly, might be better to move one of the
> flags to decl_with_vis and just document that it applies to FUNCTION_DECLs
> only. Or move some flag to cgraph if possible.
>
> But seeing e.g.
> IX86_BUILTIN_FIXUPIMMPD256, IX86_BUILTIN_FIXUPIMMPD256_MASK,
> IX86_BUILTIN_FIXUPIMMPD256_MASKZ
> etc. I wonder if you really need that many builtins, weren't we adding
> for avx512f just single builtin instead of 3 different ones, always
> providing mask argument and depending on whether it is all ones, etc.
> figuring out what kind of masking should be performed?
If only we had no lang-specific flags in tree_base we could use
the same place as we use for internal function code ...
But yes, not using that many builtins in the first place is preferred
for example by making them type-generic and/or variadic.
Richard.
> Jakub
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH i386 AVX512] [81/n] Add new built-ins.
2014-10-20 13:56 ` Jakub Jelinek
2014-10-21 9:19 ` Richard Biener
@ 2014-10-21 14:09 ` Kirill Yukhin
2014-10-21 14:21 ` Jakub Jelinek
2014-10-21 14:24 ` [PATCH i386 AVX512] [81/n] Add new built-ins Richard Biener
1 sibling, 2 replies; 16+ messages in thread
From: Kirill Yukhin @ 2014-10-21 14:09 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: Uros Bizjak, Richard Henderson, GCC Patches
Hello,
On 20 Oct 15:50, Jakub Jelinek wrote:
> On Mon, Oct 20, 2014 at 05:41:25PM +0400, Kirill Yukhin wrote:
> > Hello,
> > This patch adds (almost) all built-ins needed by
> > AVX-512VL,BW,DQ intrinsics.
> >
> > Main questionable hunk is:
> >
> > diff --git a/gcc/tree-core.h b/gcc/tree-core.h
> > index b69312b..a639487 100644
> > --- a/gcc/tree-core.h
> > +++ b/gcc/tree-core.h
> > @@ -1539,7 +1539,7 @@ struct GTY(()) tree_function_decl {
> > DECL_FUNCTION_CODE. Otherwise unused.
> > ??? The bitfield needs to be able to hold all target function
> > codes as well. */
> > - ENUM_BITFIELD(built_in_function) function_code : 11;
> > + ENUM_BITFIELD(built_in_function) function_code : 12;
> > ENUM_BITFIELD(built_in_class) built_in_class : 2;
> >
> > unsigned static_ctor_flag : 1;
>
> Well, decl_with_vis has 15 unused bits, so instead of growing
> FUNCTION_DECL significantly, might be better to move one of the
> flags to decl_with_vis and just document that it applies to FUNCTION_DECLs
> only. Or move some flag to cgraph if possible.
That was exactly what I was thinking about. Updated patch in the
bottom w/ moved `regdecl_flag' field.
> But seeing e.g.
> IX86_BUILTIN_FIXUPIMMPD256, IX86_BUILTIN_FIXUPIMMPD256_MASK,
> IX86_BUILTIN_FIXUPIMMPD256_MASKZ
FIXUPIMM w/o masking is really redundant. Fixed.
> etc. I wonder if you really need that many builtins, weren't we adding
> for avx512f just single builtin instead of 3 different ones, always
> providing mask argument and depending on whether it is all ones, etc.
> figuring out what kind of masking should be performed?
In 3 operands insns w/
destructive source we already have one operand w/ constraint `0'.
As we don't support 2+ constraint `0' in single pattern, we have to
use `match_dup' workaround, because of that we have two versions:
one w/ `match_dup' for normal masking and one w/ constraint `0' for
zero- and non-masking (generated by `subst'). Those two built-ins
are for such cases.
For non-destructive source we have one built-in.
Is it ok for trunk (w/ appropriate ChangeLog change)?
Bootstrapped. Regtesting in progress.
--
Thanks, K
AVX-512. 81/n. Add new builtins.
diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def
index 9161287..8315c5e 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -56,6 +56,7 @@ DEF_PRIMITIVE_TYPE (UHI, unsigned_intHI_type_node)
DEF_PRIMITIVE_TYPE (USI, unsigned_intSI_type_node)
DEF_PRIMITIVE_TYPE (UDI, long_long_unsigned_type_node)
# ??? Some of the types below should use the mode types above.
+DEF_PRIMITIVE_TYPE (SHORT, short_integer_type_node)
DEF_PRIMITIVE_TYPE (USHORT, short_unsigned_type_node)
DEF_PRIMITIVE_TYPE (INT, integer_type_node)
DEF_PRIMITIVE_TYPE (UINT, unsigned_type_node)
@@ -107,7 +108,14 @@ DEF_VECTOR_TYPE (V16SF, FLOAT)
DEF_VECTOR_TYPE (V8DF, DOUBLE)
DEF_VECTOR_TYPE (V8DI, DI)
DEF_VECTOR_TYPE (V16SI, SI)
+DEF_VECTOR_TYPE (V32HI, HI)
DEF_VECTOR_TYPE (V64QI, QI)
+DEF_VECTOR_TYPE (V12QI, QI)
+DEF_VECTOR_TYPE (V14QI, QI)
+DEF_VECTOR_TYPE (V32SI, SI)
+DEF_VECTOR_TYPE (V8UDI, UDI, V8DI)
+DEF_VECTOR_TYPE (V16USI, USI, V16SI)
+DEF_VECTOR_TYPE (V32UHI, UHI, V32HI)
DEF_POINTER_TYPE (PCCHAR, CHAR, CONST)
DEF_POINTER_TYPE (PCDOUBLE, DOUBLE, CONST)
@@ -119,6 +127,7 @@ DEF_POINTER_TYPE (PCVOID, VOID, CONST)
DEF_POINTER_TYPE (PVOID, VOID)
DEF_POINTER_TYPE (PDOUBLE, DOUBLE)
DEF_POINTER_TYPE (PFLOAT, FLOAT)
+DEF_POINTER_TYPE (PSHORT, SHORT)
DEF_POINTER_TYPE (PUSHORT, USHORT)
DEF_POINTER_TYPE (PINT, INT)
DEF_POINTER_TYPE (PLONGLONG, LONGLONG)
@@ -142,6 +151,9 @@ DEF_POINTER_TYPE (PV16QI, V16QI)
DEF_POINTER_TYPE (PV16HI, V16HI)
DEF_POINTER_TYPE (PV16SI, V16SI)
DEF_POINTER_TYPE (PV16SF, V16SF)
+DEF_POINTER_TYPE (PV32QI, V32QI)
+DEF_POINTER_TYPE (PV32HI, V32HI)
+DEF_POINTER_TYPE (PV64QI, V64QI)
DEF_POINTER_TYPE (PCV2SI, V2SI, CONST)
DEF_POINTER_TYPE (PCV2DF, V2DF, CONST)
@@ -155,9 +167,15 @@ DEF_POINTER_TYPE (PCV16SF, V16SF, CONST)
DEF_POINTER_TYPE (PCV2DI, V2DI, CONST)
DEF_POINTER_TYPE (PCV4SI, V4SI, CONST)
DEF_POINTER_TYPE (PCV4DI, V4DI, CONST)
+DEF_POINTER_TYPE (PCV8HI, V8HI, CONST)
DEF_POINTER_TYPE (PCV8SI, V8SI, CONST)
DEF_POINTER_TYPE (PCV8DI, V8DI, CONST)
+DEF_POINTER_TYPE (PCV16QI, V16QI, CONST)
+DEF_POINTER_TYPE (PCV16HI, V16HI, CONST)
DEF_POINTER_TYPE (PCV16SI, V16SI, CONST)
+DEF_POINTER_TYPE (PCV32QI, V32QI, CONST)
+DEF_POINTER_TYPE (PCV32HI, V32HI, CONST)
+DEF_POINTER_TYPE (PCV64QI, V64QI, CONST)
DEF_FUNCTION_TYPE (FLOAT128)
DEF_FUNCTION_TYPE (UINT64)
@@ -217,12 +235,15 @@ DEF_FUNCTION_TYPE (V8DF, V8DF)
DEF_FUNCTION_TYPE (V4HI, V4HI)
DEF_FUNCTION_TYPE (V4SF, PCFLOAT)
DEF_FUNCTION_TYPE (V4SF, V2DF)
+DEF_FUNCTION_TYPE (V4SF, V2DF, V4SF, QI)
DEF_FUNCTION_TYPE (V4SF, V4DF)
+DEF_FUNCTION_TYPE (V4SF, V4DF, V4SF, QI)
DEF_FUNCTION_TYPE (V4SF, V4SF)
DEF_FUNCTION_TYPE (V4SF, PCV4SF)
DEF_FUNCTION_TYPE (V4SF, V4SI)
DEF_FUNCTION_TYPE (V4SF, V8SF)
DEF_FUNCTION_TYPE (V4SF, V8HI)
+DEF_FUNCTION_TYPE (V4SF, V8HI, V4SF, QI)
DEF_FUNCTION_TYPE (V4SI, V16QI)
DEF_FUNCTION_TYPE (V4SI, V2DF)
DEF_FUNCTION_TYPE (V4SI, V4DF)
@@ -241,6 +262,7 @@ DEF_FUNCTION_TYPE (V8SF, V4SF)
DEF_FUNCTION_TYPE (V8SF, V8SF)
DEF_FUNCTION_TYPE (V8SF, V8SI)
DEF_FUNCTION_TYPE (V8SF, V8HI)
+DEF_FUNCTION_TYPE (V8SF, V8HI, V8SF, QI)
DEF_FUNCTION_TYPE (V16SF, V16SF)
DEF_FUNCTION_TYPE (V8SI, V8DI)
DEF_FUNCTION_TYPE (V8SI, V4SI)
@@ -251,6 +273,9 @@ DEF_FUNCTION_TYPE (V32QI, V32QI)
DEF_FUNCTION_TYPE (V32QI, V16QI)
DEF_FUNCTION_TYPE (V16HI, V16SI)
DEF_FUNCTION_TYPE (V16HI, V16HI)
+DEF_FUNCTION_TYPE (V16SF, V16HI)
+DEF_FUNCTION_TYPE (V16SF, V16HI, V16SF, HI)
+DEF_FUNCTION_TYPE (V16SF, V16SI)
DEF_FUNCTION_TYPE (V16HI, V8HI)
DEF_FUNCTION_TYPE (V8SI, V8SI)
DEF_FUNCTION_TYPE (VOID, PCVOID)
@@ -266,8 +291,10 @@ DEF_FUNCTION_TYPE (V4DI, V16QI)
DEF_FUNCTION_TYPE (V8SI, V8HI)
DEF_FUNCTION_TYPE (V4DI, V8HI)
DEF_FUNCTION_TYPE (V4DI, V4SI)
+DEF_FUNCTION_TYPE (V4DI, V4DI)
DEF_FUNCTION_TYPE (V4DI, PV4DI)
DEF_FUNCTION_TYPE (V4DI, V2DI)
+DEF_FUNCTION_TYPE (V16SI, V16SF)
DEF_FUNCTION_TYPE (V16SF, FLOAT)
DEF_FUNCTION_TYPE (V16SI, INT)
DEF_FUNCTION_TYPE (V8DF, DOUBLE)
@@ -290,10 +317,38 @@ DEF_FUNCTION_TYPE (V8DI, V8DI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, QI)
DEF_FUNCTION_TYPE (V16SI, PV4SI)
DEF_FUNCTION_TYPE (V16SF, PV4SF)
+DEF_FUNCTION_TYPE (V8DI, PV2DI)
+DEF_FUNCTION_TYPE (V8DF, PV2DF)
+DEF_FUNCTION_TYPE (V4DI, PV2DI)
+DEF_FUNCTION_TYPE (V4DF, PV2DF)
+DEF_FUNCTION_TYPE (V16SI, PV2SI)
+DEF_FUNCTION_TYPE (V16SF, PV2SF)
DEF_FUNCTION_TYPE (V8DI, PV4DI)
DEF_FUNCTION_TYPE (V8DF, PV4DF)
+DEF_FUNCTION_TYPE (V8SF, FLOAT)
+DEF_FUNCTION_TYPE (V4SF, FLOAT)
+DEF_FUNCTION_TYPE (V4DF, DOUBLE)
+DEF_FUNCTION_TYPE (V8SF, PV4SF)
+DEF_FUNCTION_TYPE (V8SI, PV4SI)
+DEF_FUNCTION_TYPE (V4SI, PV2SI)
+DEF_FUNCTION_TYPE (V8SF, PV2SF)
+DEF_FUNCTION_TYPE (V8SI, PV2SI)
+DEF_FUNCTION_TYPE (V16SF, PV8SF)
+DEF_FUNCTION_TYPE (V16SI, PV8SI)
+DEF_FUNCTION_TYPE (V8DI, V8SF)
+DEF_FUNCTION_TYPE (V4DI, V4SF)
+DEF_FUNCTION_TYPE (V2DI, V4SF)
+DEF_FUNCTION_TYPE (V64QI, QI)
+DEF_FUNCTION_TYPE (V32HI, HI)
DEF_FUNCTION_TYPE (V8UHI, V8UHI)
+DEF_FUNCTION_TYPE (V16UHI, V16UHI)
+DEF_FUNCTION_TYPE (V32UHI, V32UHI)
+DEF_FUNCTION_TYPE (V2UDI, V2UDI)
+DEF_FUNCTION_TYPE (V4UDI, V4UDI)
+DEF_FUNCTION_TYPE (V8UDI, V8UDI)
+DEF_FUNCTION_TYPE (V4USI, V4USI)
DEF_FUNCTION_TYPE (V8USI, V8USI)
+DEF_FUNCTION_TYPE (V16USI, V16USI)
DEF_FUNCTION_TYPE (V8DI, PV8DI)
DEF_FUNCTION_TYPE (DI, V2DI, INT)
@@ -336,9 +391,13 @@ DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V4SF)
DEF_FUNCTION_TYPE (V2DF, V4DF, INT)
+DEF_FUNCTION_TYPE (V2DF, V4DF, INT, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V8DF, INT)
+DEF_FUNCTION_TYPE (V2DF, V8DF, INT, V2DF, QI)
DEF_FUNCTION_TYPE (V2DI, V16QI, V16QI)
DEF_FUNCTION_TYPE (V2DI, V2DF, V2DF)
DEF_FUNCTION_TYPE (V2DI, V2DI, INT)
+DEF_FUNCTION_TYPE (V2DI, V2DI, INT, V2DI, QI)
DEF_FUNCTION_TYPE (V2DI, V2DI, SI)
DEF_FUNCTION_TYPE (V2DI, V2DI, V16QI)
DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI)
@@ -353,6 +412,7 @@ DEF_FUNCTION_TYPE (V2SI, V2SI, V2SI)
DEF_FUNCTION_TYPE (V2SI, V4HI, V4HI)
DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DI)
DEF_FUNCTION_TYPE (V4DF, V4DF, INT)
+DEF_FUNCTION_TYPE (V8DF, V8DF, INT)
DEF_FUNCTION_TYPE (V4DF, V8DF, INT)
DEF_FUNCTION_TYPE (V4DF, V8DF, INT, V4DF, QI)
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF)
@@ -377,25 +437,36 @@ DEF_FUNCTION_TYPE (V4SF, V4SF, V2SI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SI)
DEF_FUNCTION_TYPE (V4SF, V8SF, INT)
+DEF_FUNCTION_TYPE (V4SF, V8SF, INT, V4SF, QI)
DEF_FUNCTION_TYPE (V4SI, V2DF, V2DF)
+DEF_FUNCTION_TYPE (V4SI, V2DF, V4SI, QI)
DEF_FUNCTION_TYPE (V4SI, V4SF, V4SF)
DEF_FUNCTION_TYPE (V4SI, V4SI, INT)
+DEF_FUNCTION_TYPE (V4SI, V4SI, INT, V4SI, QI)
DEF_FUNCTION_TYPE (V4SI, V4SI, SI)
DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI)
DEF_FUNCTION_TYPE (V4SI, V8HI, V8HI)
+DEF_FUNCTION_TYPE (V4SI, V8HI, V8HI, V4SI, QI)
DEF_FUNCTION_TYPE (V4SI, V8SI, INT)
+DEF_FUNCTION_TYPE (V4SI, V8SI, INT, V4SI, QI)
DEF_FUNCTION_TYPE (V4SI, PCV4SI, V4SI)
DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI)
+DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI, V8HI, QI)
DEF_FUNCTION_TYPE (V8HI, V4SI, V4SI)
DEF_FUNCTION_TYPE (V8HI, V8HI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DI, INT)
DEF_FUNCTION_TYPE (V8HI, V8HI, SI)
DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI)
DEF_FUNCTION_TYPE (V8HI, V8SF, INT)
+DEF_FUNCTION_TYPE (V8HI, V8SF, INT, V8HI, QI)
DEF_FUNCTION_TYPE (V8HI, V4SF, INT)
+DEF_FUNCTION_TYPE (V8HI, V4SF, INT, V8HI, QI)
DEF_FUNCTION_TYPE (V8QI, V4HI, V4HI)
DEF_FUNCTION_TYPE (V8QI, V8QI, V8QI)
DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SI)
DEF_FUNCTION_TYPE (V8SF, V8SF, INT)
+DEF_FUNCTION_TYPE (V8SF, V16SF, INT)
+DEF_FUNCTION_TYPE (V8SF, V16SF, INT, V8SF, QI)
DEF_FUNCTION_TYPE (V16SF, V16SF, INT)
DEF_FUNCTION_TYPE (V4SF, V16SF, INT)
DEF_FUNCTION_TYPE (V4SF, V16SF, INT, V4SF, QI)
@@ -404,29 +475,46 @@ DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SI)
DEF_FUNCTION_TYPE (V32QI, V16HI, V16HI)
+DEF_FUNCTION_TYPE (V64QI, V32HI, V32HI)
DEF_FUNCTION_TYPE (V16HI, V8SI, V8SI)
+DEF_FUNCTION_TYPE (V32HI, V16SI, V16SI)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V2DF, INT)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V2DF, INT, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V4DF, INT, V8DF, QI)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, INT, V8DF, QI)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, INT, V8DF, QI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, INT, V8DF, QI)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DI, INT)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DI, INT, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DI, INT, QI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DI, INT, QI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, INT, V16SF, HI)
+DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, INT, V16SF, HI, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, INT, V16SF, HI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V4SI, INT, V16SI, HI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SI, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SI, INT, HI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SI, INT, HI, INT)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SI, INT, QI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SI, INT, QI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SI, INT, QI, INT)
-DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT, QI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT, QI, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V4SF, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V4SF, INT, V16SF, HI)
+DEF_FUNCTION_TYPE (V16SF, V16SF, V8SF, INT, V16SF, HI)
DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI)
DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI)
+DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI)
+DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI, V16HI, HI)
+DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI, V32HI, SI)
DEF_FUNCTION_TYPE (V16HI, V16HI, V8HI)
DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, INT)
DEF_FUNCTION_TYPE (V16HI, V16HI, INT)
DEF_FUNCTION_TYPE (V16HI, V16SF, INT)
DEF_FUNCTION_TYPE (V16HI, V16SF, INT, V16HI, HI)
@@ -438,13 +526,20 @@ DEF_FUNCTION_TYPE (V8SI, V4DF, V4DF)
DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V4SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V4SI, INT)
+DEF_FUNCTION_TYPE (V16SI, V16SI, V8SI, INT, V16SI, HI)
DEF_FUNCTION_TYPE (V4SI, V16SI, INT)
DEF_FUNCTION_TYPE (V4SI, V16SI, INT, V4SI, QI)
DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, INT, V16SI, HI)
DEF_FUNCTION_TYPE (V8SI, V16HI, V16HI)
+DEF_FUNCTION_TYPE (V16SI, V32HI, V32HI)
+DEF_FUNCTION_TYPE (V8SI, V16HI, V16HI, V8SI, QI)
+DEF_FUNCTION_TYPE (V16SI, V32HI, V32HI, V16SI, HI)
DEF_FUNCTION_TYPE (V8SI, V8SI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SI, INT, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V16SI, INT)
+DEF_FUNCTION_TYPE (V8SI, V16SI, INT, V8SI, QI)
DEF_FUNCTION_TYPE (V8SI, V8SI, SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, INT)
@@ -455,9 +550,17 @@ DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI)
DEF_FUNCTION_TYPE (V16SI, V8DF, V8DF)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, INT, V8DI, QI)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, INT, V8DI, DI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT, V4DI, SI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT, V2DI, HI)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V4DI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI, INT, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V4DI, INT, V8DI, QI)
DEF_FUNCTION_TYPE (V4DI, V8SI, V8SI)
DEF_FUNCTION_TYPE (V4UDI, V8USI, V8USI)
+DEF_FUNCTION_TYPE (V8DI, V16SI, V16SI)
+DEF_FUNCTION_TYPE (V8DI, V64QI, V64QI)
DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI)
DEF_FUNCTION_TYPE (V4DI, PCV4DI, V4DI)
@@ -466,8 +569,12 @@ DEF_FUNCTION_TYPE (V4DI, V8DI, INT, V4DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8DI, INT, V8DI, QI)
DEF_FUNCTION_TYPE (V4DI, V4DI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, INT, V4DI, QI)
DEF_FUNCTION_TYPE (V2DI, V4DI, INT)
DEF_FUNCTION_TYPE (VOID, PVOID, INT64)
+DEF_FUNCTION_TYPE (V2DI, V4DI, INT, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V8DI, INT)
+DEF_FUNCTION_TYPE (V2DI, V8DI, INT, V2DI, QI)
DEF_FUNCTION_TYPE (VOID, PCHAR, V16QI)
DEF_FUNCTION_TYPE (VOID, PCHAR, V32QI)
DEF_FUNCTION_TYPE (VOID, PDOUBLE, V2DF)
@@ -489,9 +596,72 @@ DEF_FUNCTION_TYPE (VOID, UNSIGNED, UNSIGNED)
DEF_FUNCTION_TYPE (VOID, PV8DI, V8DI)
# Instructions returning mask
+DEF_FUNCTION_TYPE (QI, QI)
DEF_FUNCTION_TYPE (HI, HI)
+DEF_FUNCTION_TYPE (SI, SI)
+DEF_FUNCTION_TYPE (DI, DI)
+DEF_FUNCTION_TYPE (HI, V16QI)
+DEF_FUNCTION_TYPE (SI, V32QI)
+DEF_FUNCTION_TYPE (DI, V64QI)
+DEF_FUNCTION_TYPE (QI, V8HI)
+DEF_FUNCTION_TYPE (HI, V16HI)
+DEF_FUNCTION_TYPE (SI, V32HI)
+DEF_FUNCTION_TYPE (QI, V4SI)
+DEF_FUNCTION_TYPE (QI, V8SI)
+DEF_FUNCTION_TYPE (HI, V16SI)
+DEF_FUNCTION_TYPE (QI, V2DI)
+DEF_FUNCTION_TYPE (QI, V4DI)
+DEF_FUNCTION_TYPE (QI, V8DI)
+DEF_FUNCTION_TYPE (V16QI, HI)
+DEF_FUNCTION_TYPE (V32QI, SI)
+DEF_FUNCTION_TYPE (V64QI, DI)
+DEF_FUNCTION_TYPE (V8HI, QI)
+DEF_FUNCTION_TYPE (V16HI, HI)
+DEF_FUNCTION_TYPE (V32HI, SI)
+DEF_FUNCTION_TYPE (V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, HI)
+DEF_FUNCTION_TYPE (V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, HI)
+DEF_FUNCTION_TYPE (V2DI, QI)
+DEF_FUNCTION_TYPE (V4DI, QI)
+DEF_FUNCTION_TYPE (QI, QI, QI)
DEF_FUNCTION_TYPE (HI, HI, HI)
+DEF_FUNCTION_TYPE (SI, SI, SI)
+DEF_FUNCTION_TYPE (DI, DI, DI)
+DEF_FUNCTION_TYPE (QI, QI, INT)
DEF_FUNCTION_TYPE (HI, HI, INT)
+DEF_FUNCTION_TYPE (SI, SI, INT)
+DEF_FUNCTION_TYPE (DI, DI, INT)
+DEF_FUNCTION_TYPE (HI, V16QI, V16QI)
+DEF_FUNCTION_TYPE (HI, V16QI, V16QI, HI)
+DEF_FUNCTION_TYPE (HI, V16QI, V16QI, INT, HI)
+DEF_FUNCTION_TYPE (SI, V32QI, V32QI)
+DEF_FUNCTION_TYPE (SI, V32QI, V32QI, SI)
+DEF_FUNCTION_TYPE (SI, V32QI, V32QI, INT, SI)
+DEF_FUNCTION_TYPE (DI, V64QI, V64QI)
+DEF_FUNCTION_TYPE (DI, V64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (DI, V64QI, V64QI, INT, DI)
+DEF_FUNCTION_TYPE (QI, V8HI, V8HI)
+DEF_FUNCTION_TYPE (QI, V8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (QI, V8HI, V8HI, INT, QI)
+DEF_FUNCTION_TYPE (HI, V16HI, V16HI)
+DEF_FUNCTION_TYPE (HI, V16HI, V16HI, HI)
+DEF_FUNCTION_TYPE (HI, V16HI, V16HI, INT, HI)
+DEF_FUNCTION_TYPE (SI, V32HI, V32HI)
+DEF_FUNCTION_TYPE (SI, V32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (SI, V32HI, V32HI, INT, SI)
+DEF_FUNCTION_TYPE (QI, V4SI, V4SI)
+DEF_FUNCTION_TYPE (QI, V4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (QI, V4SI, V4SI, INT, QI)
+DEF_FUNCTION_TYPE (QI, V8SI, V8SI)
+DEF_FUNCTION_TYPE (QI, V8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (QI, V8SI, V8SI, INT, QI)
+DEF_FUNCTION_TYPE (QI, V2DI, V2DI)
+DEF_FUNCTION_TYPE (QI, V2DI, V2DI, QI)
+DEF_FUNCTION_TYPE (QI, V2DI, V2DI, INT, QI)
+DEF_FUNCTION_TYPE (QI, V4DI, V4DI)
+DEF_FUNCTION_TYPE (QI, V4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (QI, V4DI, V4DI, INT, QI)
DEF_FUNCTION_TYPE (QI, V8DI, V8DI)
DEF_FUNCTION_TYPE (QI, V8DI, V8DI, QI)
DEF_FUNCTION_TYPE (HI, V16SI, V16SI)
@@ -518,6 +688,7 @@ DEF_FUNCTION_TYPE (V8DI, QI)
DEF_FUNCTION_TYPE (INT, V16QI, V16QI, INT)
DEF_FUNCTION_TYPE (UCHAR, UINT, UINT, UINT)
DEF_FUNCTION_TYPE (UCHAR, UINT64, UINT, UINT)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, V32HI)
DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, V16HI)
DEF_FUNCTION_TYPE (V16QI, V16QI, QI, INT)
DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, INT)
@@ -525,7 +696,10 @@ DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, V16QI)
DEF_FUNCTION_TYPE (V1DI, V1DI, V1DI, INT)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI, INT)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DF)
+DEF_FUNCTION_TYPE (V2DF, V2DI, V2DF, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DI, V2DF, QI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT)
DEF_FUNCTION_TYPE (V2DI, V2DI, DI, INT)
DEF_FUNCTION_TYPE (V2DI, V2DI, UINT, UINT)
@@ -533,9 +707,11 @@ DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT)
DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI)
DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, V32QI)
DEF_FUNCTION_TYPE (V4DF, V4DF, V2DF, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V2DF, INT, V4DF, QI)
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, INT)
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DF)
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, INT)
DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V4DI)
DEF_FUNCTION_TYPE (V4HI, V4HI, HI, INT)
DEF_FUNCTION_TYPE (V4SF, V4SF, FLOAT, INT)
@@ -544,6 +720,10 @@ DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, INT, INT)
DEF_FUNCTION_TYPE (V4SF, V4SF, V2DF, INT)
DEF_FUNCTION_TYPE (V2DF, V2DF, V4SF, INT)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF)
+DEF_FUNCTION_TYPE (V4SF, V4SI, V4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SI, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V2DF, V4SF, QI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SI, INT)
DEF_FUNCTION_TYPE (V4SI, V4SI, SI, INT)
DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, INT)
@@ -554,76 +734,263 @@ DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, INT)
DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, V4SI)
DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, V8HI)
DEF_FUNCTION_TYPE (V8SF, V8SF, V4SF, INT)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V4SF, INT, V8SF, QI)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, INT)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SF)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DF)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SF)
DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI, INT, V8SI, QI)
DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, INT)
DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI)
DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT)
DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI, INT, V4DI, QI)
# Instructions with masking
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V4SF, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V4SI, V2DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4SF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4SI, V4DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8SF, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8SI, V8DF, QI)
+DEF_FUNCTION_TYPE (V2DI, V4SI, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V8HI, V2DI, QI)
+DEF_FUNCTION_TYPE (V8DI, V8DF, V8DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DF, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DF, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT, V2DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT, V4DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8SI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8HI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, V16QI, V8DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V16QI, V2DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V16QI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4SI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V8HI, V4DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, V8DF)
DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DI, V8DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DI, V4DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DF, QI)
+DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, V16QI, HI)
+DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, V16HI, HI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI, HI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DF, QI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V4SF, V2DF, QI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, V32QI, SI)
+DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SI, V4SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SI, V8SF, QI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, HI)
DEF_FUNCTION_TYPE (V16SF, V16SI, V16SF, HI)
+DEF_FUNCTION_TYPE (V4SI, V16QI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V8HI, V4SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V8HI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V16QI, V8SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, INT, V4SI, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SI, V8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, INT, V8SI, QI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SF, HI)
DEF_FUNCTION_TYPE (V16SF, V16SI, V16SF, V16SF)
DEF_FUNCTION_TYPE (V16SF, V16SI, V16SF, V16SF, HI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SI, V16SF, HI)
-DEF_FUNCTION_TYPE (V4SF, V4SF, V2DF, V4SF, QI)
-DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V16SF, V8SF, V16SF, HI)
DEF_FUNCTION_TYPE (V16SF, V4SF, V16SF, HI)
DEF_FUNCTION_TYPE (V8DF, V4DF, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V2DF, V8DF, QI)
+DEF_FUNCTION_TYPE (V16SI, V8SI, V16SI, HI)
DEF_FUNCTION_TYPE (V16SI, V4SI, V16SI, HI)
DEF_FUNCTION_TYPE (V16SI, SI, V16SI, HI)
DEF_FUNCTION_TYPE (V16SI, V16HI, V16SI, HI)
DEF_FUNCTION_TYPE (V16SI, V16QI, V16SI, HI)
DEF_FUNCTION_TYPE (V8SI, V8DF, V8SI, QI)
DEF_FUNCTION_TYPE (V8DI, V4DI, V8DI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4DF, V4SI, QI)
DEF_FUNCTION_TYPE (V8DI, V2DI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, DI, V8DI, QI)
+DEF_FUNCTION_TYPE (V8DI, PCCHAR, V8DI, QI)
+DEF_FUNCTION_TYPE (V8SF, PCFLOAT, V8SF, QI)
+DEF_FUNCTION_TYPE (V4SF, PCFLOAT, V4SF, QI)
+DEF_FUNCTION_TYPE (V4DF, PCDOUBLE, V4DF, QI)
+DEF_FUNCTION_TYPE (V2DF, PCDOUBLE, V2DF, QI)
+DEF_FUNCTION_TYPE (V8SI, PCCHAR, V8SI, QI)
+DEF_FUNCTION_TYPE (V4SI, PCCHAR, V4SI, QI)
+DEF_FUNCTION_TYPE (V4DI, PCCHAR, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, PCCHAR, V2DI, QI)
+DEF_FUNCTION_TYPE (V16QI, V16SI, V16QI, HI)
+DEF_FUNCTION_TYPE (V16QI, V8DI, V16QI, QI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI, INT)
+DEF_FUNCTION_TYPE (V32HI, V32QI, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI, INT)
+DEF_FUNCTION_TYPE (V16HI, V16QI, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V16QI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI, INT)
+DEF_FUNCTION_TYPE (V8SF, V4SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V4DF, V2DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V8SI, V4SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, SI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4DI, V2DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, DI, V2DI, QI)
+DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V64QI, V16QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V64QI, QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, SI)
+DEF_FUNCTION_TYPE (V32QI, V16QI, V32QI, SI)
+DEF_FUNCTION_TYPE (V32QI, QI, V32QI, SI)
+DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, HI)
+DEF_FUNCTION_TYPE (V16QI, QI, V16QI, HI)
+DEF_FUNCTION_TYPE (V32HI, V8HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V32HI, HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V8HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V16HI, HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8HI, HI, V8HI, QI)
+DEF_FUNCTION_TYPE (V64QI, PCV64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V32HI, PCV32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V32QI, PCV32QI, V32QI, SI)
DEF_FUNCTION_TYPE (V16SF, PCV16SF, V16SF, HI)
+DEF_FUNCTION_TYPE (V16SF, PCV8SF, V16SF, HI)
DEF_FUNCTION_TYPE (V8DF, PCV8DF, V8DF, QI)
DEF_FUNCTION_TYPE (V16SI, PCV16SI, V16SI, HI)
+DEF_FUNCTION_TYPE (V16SI, PCV8SI, V16SI, HI)
+DEF_FUNCTION_TYPE (V16HI, PCV16HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V16QI, PCV16QI, V16QI, HI)
+DEF_FUNCTION_TYPE (V8DF, PCV2DF, V8DF, QI)
+DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SF, PCV4SF, V8SF, QI)
DEF_FUNCTION_TYPE (V8DI, PCV8DI, V8DI, QI)
-DEF_FUNCTION_TYPE (V2DF, PCDOUBLE, V2DF, QI)
-DEF_FUNCTION_TYPE (V4SF, PCFLOAT, V4SF, QI)
-DEF_FUNCTION_TYPE (V16QI, V16SI, V16QI, HI)
+DEF_FUNCTION_TYPE (V8DI, PCV2DI, V8DI, QI)
+DEF_FUNCTION_TYPE (V8SI, PCV8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, PCV4SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8HI, PCV8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (V4DF, PCV2DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4SF, PCV4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V4DI, PCV4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, PCV2DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4SI, PCV4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (V2DF, PCV2DF, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DI, PCV2DI, V2DI, QI)
DEF_FUNCTION_TYPE (V16HI, V16SI, V16HI, HI)
DEF_FUNCTION_TYPE (V8SI, V8DI, V8SI, QI)
DEF_FUNCTION_TYPE (V8HI, V8DI, V8HI, QI)
-DEF_FUNCTION_TYPE (V16QI, V8DI, V16QI, QI)
+DEF_FUNCTION_TYPE (V16QI, V8HI, V16QI, QI)
+DEF_FUNCTION_TYPE (V16QI, V16HI, V16QI, HI)
+DEF_FUNCTION_TYPE (V16QI, V4SI, V16QI, QI)
+DEF_FUNCTION_TYPE (V16QI, V8SI, V16QI, QI)
+DEF_FUNCTION_TYPE (V8HI, V4SI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8HI, V8SI, V8HI, QI)
+DEF_FUNCTION_TYPE (V16QI, V2DI, V16QI, QI)
+DEF_FUNCTION_TYPE (V16QI, V4DI, V16QI, QI)
+DEF_FUNCTION_TYPE (V8HI, V2DI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8HI, V4DI, V8HI, QI)
+DEF_FUNCTION_TYPE (V4SI, V2DI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4DI, V4SI, QI)
+DEF_FUNCTION_TYPE (V32QI, V32HI, V32QI, SI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, INT, V2DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, INT, V4DF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, INT, V4SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, INT, V8SF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, INT, V4DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT, V2DF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, INT, V8SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, INT, V4SF, QI)
DEF_FUNCTION_TYPE (VOID, PV8DF, V8DF, QI)
DEF_FUNCTION_TYPE (VOID, PV8SI, V8DI, QI)
DEF_FUNCTION_TYPE (VOID, PV8HI, V8DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V4DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V2DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4SI, V4DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4SI, V2DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V8SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V4SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4DF, V4DF, QI)
+DEF_FUNCTION_TYPE (VOID, PV2DF, V2DF, QI)
DEF_FUNCTION_TYPE (VOID, PV16SF, V16SF, HI)
+DEF_FUNCTION_TYPE (VOID, PV8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (VOID, PV4SF, V4SF, QI)
DEF_FUNCTION_TYPE (VOID, PV8DI, V8DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV2DI, V2DI, QI)
DEF_FUNCTION_TYPE (VOID, PV16SI, V16SI, HI)
DEF_FUNCTION_TYPE (VOID, PV16HI, V16SI, HI)
DEF_FUNCTION_TYPE (VOID, PV16QI, V16SI, HI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V8SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V4SI, QI)
DEF_FUNCTION_TYPE (VOID, PV16QI, V8DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V4DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V2DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (VOID, PV16HI, V16HI, HI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (VOID, PV64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (VOID, PV32QI, V32QI, SI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V16QI, HI)
DEF_FUNCTION_TYPE (VOID, PDOUBLE, V2DF, QI)
DEF_FUNCTION_TYPE (VOID, PFLOAT, V4SF, QI)
DEF_FUNCTION_TYPE (V16SI, V16SF, V16SI, HI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI, INT, QI)
+DEF_FUNCTION_TYPE (V8SI, V8SF, V8SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SF, V4SI, QI)
+DEF_FUNCTION_TYPE (V8DI, V8SF, V8DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4SF, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V4SF, V2DI, QI)
+DEF_FUNCTION_TYPE (V8SF, V8DI, V8SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4DI, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V2DI, V4SF, QI)
+DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DI, V4DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V2DI, V2DF, QI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, INT, V32HI, SI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V8HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V16HI, INT, V16HI, HI)
+DEF_FUNCTION_TYPE (V16HI, V16HI, V8HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V8HI, INT, V8HI, QI)
+DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI, INT, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI, INT, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI, INT, V8HI, QI)
+DEF_FUNCTION_TYPE (V64QI, V32HI, V32HI, V64QI, DI)
+DEF_FUNCTION_TYPE (V32QI, V16HI, V16HI, V32QI, SI)
+DEF_FUNCTION_TYPE (V16QI, V8HI, V8HI, V16QI, HI)
+DEF_FUNCTION_TYPE (V32HI, V16SI, V16SI, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V8SI, V8SI, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V4SI, V4SI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8DI, V16SI, V16SI, V8DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V8SI, V8SI, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V4SI, V4SI, V2DI, QI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI, INT, HI)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI, INT, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V4DI, INT, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI, INT, QI)
DEF_FUNCTION_TYPE (VOID, PCVOID, UNSIGNED, UNSIGNED)
DEF_FUNCTION_TYPE (VOID, PV2DF, V2DI, V2DF)
@@ -648,11 +1015,30 @@ DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DI)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DI, V2DF)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI, V4DF)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DI, V8DF)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SI, V4SF)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI, V8SF)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SI, V16SF)
-DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, INT, V4SF, QI)
-DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT, V2DF, QI)
-DEF_FUNCTION_TYPE (V8DI, V16SI, V16SI, V8DI, QI)
+
+DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI, V4DI, QI)
+
+DEF_FUNCTION_TYPE (QI, V8DF, INT)
+DEF_FUNCTION_TYPE (QI, V4DF, INT)
+DEF_FUNCTION_TYPE (QI, V4DF, V4DF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V2DF, INT)
+DEF_FUNCTION_TYPE (HI, V16SF, INT)
+DEF_FUNCTION_TYPE (QI, V8SF, INT)
+DEF_FUNCTION_TYPE (QI, V8SF, V8SF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V4SF, INT)
+DEF_FUNCTION_TYPE (QI, V8DF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V4DF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V2DF, INT, QI)
+DEF_FUNCTION_TYPE (HI, V16SF, INT, HI)
+DEF_FUNCTION_TYPE (QI, V8SF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V4SF, INT, QI)
DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, UINT, UINT)
DEF_FUNCTION_TYPE (V4HI, HI, HI, HI, HI)
@@ -688,6 +1074,10 @@ DEF_FUNCTION_TYPE (V8SI, V8DF, V8SI, QI, INT)
DEF_FUNCTION_TYPE (V8SF, V8DF, V8SF, QI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, QI, INT)
DEF_FUNCTION_TYPE (V8DF, V8SF, V8DF, QI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DF, V8DI, QI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8SF, V8DI, QI, INT)
+DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, QI, INT)
+DEF_FUNCTION_TYPE (V8SF, V8DI, V8SF, QI, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SF, HI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DF, QI, INT)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF, QI, INT)
@@ -736,16 +1126,53 @@ DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V8SI, QI, INT)
DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V16SI, QI, INT)
DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V8DI, QI, INT)
DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V8DI, QI, INT)
+DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V8SI, QI, INT)
+DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE, V2DI, QI, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V8SF, V8SF, PCFLOAT, V8SI, QI, INT)
+DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V2DI, QI, INT)
+DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V8SF, V8SF, PCFLOAT, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V2DI, V2DI, PCINT64, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V8SI, QI, INT)
+DEF_FUNCTION_TYPE (V2DI, V2DI, PCINT64, V2DI, QI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V8SI, QI, INT)
+DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V2DI, QI, INT)
+DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V4DI, QI, INT)
+
DEF_FUNCTION_TYPE (VOID, PFLOAT, HI, V16SI, V16SF, INT)
+DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V8SI, V8SF, INT)
+DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V4SI, V4SF, INT)
DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V8SI, V8DF, INT)
+DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4SI, V4DF, INT)
+DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4SI, V2DF, INT)
DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V8DI, V8SF, INT)
+DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V4DI, V4SF, INT)
+DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V2DI, V4SF, INT)
DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V8DI, V8DF, INT)
+DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4DI, V4DF, INT)
+DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V2DI, V2DF, INT)
DEF_FUNCTION_TYPE (VOID, PINT, HI, V16SI, V16SI, INT)
+DEF_FUNCTION_TYPE (VOID, PINT, QI, V8SI, V8SI, INT)
+DEF_FUNCTION_TYPE (VOID, PINT, QI, V4SI, V4SI, INT)
DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V8SI, V8DI, INT)
+DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4SI, V4DI, INT)
+DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4SI, V2DI, INT)
DEF_FUNCTION_TYPE (VOID, PINT, QI, V8DI, V8SI, INT)
+DEF_FUNCTION_TYPE (VOID, PINT, QI, V4DI, V4SI, INT)
+DEF_FUNCTION_TYPE (VOID, PINT, QI, V2DI, V4SI, INT)
DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V8DI, V8DI, INT)
DEF_FUNCTION_TYPE (VOID, QI, V8SI, PCINT64, INT, INT)
+DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4DI, V4DI, INT)
+DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V2DI, V2DI, INT)
DEF_FUNCTION_TYPE (VOID, HI, V16SI, PCINT, INT, INT)
DEF_FUNCTION_TYPE (VOID, QI, V8DI, PCINT64, INT, INT)
DEF_FUNCTION_TYPE (VOID, QI, V8DI, PCINT, INT, INT)
@@ -793,8 +1220,13 @@ DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_V2DI, COUNT)
DEF_FUNCTION_TYPE_ALIAS (V2DF_FTYPE_V2DF_V2DF, SWAP)
DEF_FUNCTION_TYPE_ALIAS (V4SF_FTYPE_V4SF_V4SF, SWAP)
+DEF_FUNCTION_TYPE_ALIAS (V8DI_FTYPE_V8DI_INT, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_INT, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V2DI_FTYPE_V2DI_INT, CONVERT)
+DEF_FUNCTION_TYPE_ALIAS (V8DI_FTYPE_V8DI_V8DI_INT, CONVERT)
+DEF_FUNCTION_TYPE_ALIAS (V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI, CONVERT)
+DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI, CONVERT)
+DEF_FUNCTION_TYPE_ALIAS (V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_V4DI_INT, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V2DI_FTYPE_V2DI_V2DI_INT, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V1DI_FTYPE_V1DI_V1DI_INT, CONVERT)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 33b21f4..87992b0 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -28635,6 +28635,995 @@ enum ix86_builtins
IX86_BUILTIN_KXOR16,
IX86_BUILTIN_KMOV16,
+ /* AVX512VL. */
+ IX86_BUILTIN_PMOVUSQD256_MEM,
+ IX86_BUILTIN_PMOVUSQD128_MEM,
+ IX86_BUILTIN_PMOVSQD256_MEM,
+ IX86_BUILTIN_PMOVSQD128_MEM,
+ IX86_BUILTIN_PMOVQD256_MEM,
+ IX86_BUILTIN_PMOVQD128_MEM,
+ IX86_BUILTIN_PMOVUSQW256_MEM,
+ IX86_BUILTIN_PMOVUSQW128_MEM,
+ IX86_BUILTIN_PMOVSQW256_MEM,
+ IX86_BUILTIN_PMOVSQW128_MEM,
+ IX86_BUILTIN_PMOVQW256_MEM,
+ IX86_BUILTIN_PMOVQW128_MEM,
+ IX86_BUILTIN_PMOVUSQB256_MEM,
+ IX86_BUILTIN_PMOVUSQB128_MEM,
+ IX86_BUILTIN_PMOVSQB256_MEM,
+ IX86_BUILTIN_PMOVSQB128_MEM,
+ IX86_BUILTIN_PMOVQB256_MEM,
+ IX86_BUILTIN_PMOVQB128_MEM,
+ IX86_BUILTIN_PMOVUSDW256_MEM,
+ IX86_BUILTIN_PMOVUSDW128_MEM,
+ IX86_BUILTIN_PMOVSDW256_MEM,
+ IX86_BUILTIN_PMOVSDW128_MEM,
+ IX86_BUILTIN_PMOVDW256_MEM,
+ IX86_BUILTIN_PMOVDW128_MEM,
+ IX86_BUILTIN_PMOVUSDB256_MEM,
+ IX86_BUILTIN_PMOVUSDB128_MEM,
+ IX86_BUILTIN_PMOVSDB256_MEM,
+ IX86_BUILTIN_PMOVSDB128_MEM,
+ IX86_BUILTIN_PMOVDB256_MEM,
+ IX86_BUILTIN_PMOVDB128_MEM,
+ IX86_BUILTIN_MOVDQA64LOAD256_MASK,
+ IX86_BUILTIN_MOVDQA64LOAD128_MASK,
+ IX86_BUILTIN_MOVDQA32LOAD256_MASK,
+ IX86_BUILTIN_MOVDQA32LOAD128_MASK,
+ IX86_BUILTIN_MOVDQA64STORE256_MASK,
+ IX86_BUILTIN_MOVDQA64STORE128_MASK,
+ IX86_BUILTIN_MOVDQA32STORE256_MASK,
+ IX86_BUILTIN_MOVDQA32STORE128_MASK,
+ IX86_BUILTIN_LOADAPD256_MASK,
+ IX86_BUILTIN_LOADAPD128_MASK,
+ IX86_BUILTIN_LOADAPS256_MASK,
+ IX86_BUILTIN_LOADAPS128_MASK,
+ IX86_BUILTIN_STOREAPD256_MASK,
+ IX86_BUILTIN_STOREAPD128_MASK,
+ IX86_BUILTIN_STOREAPS256_MASK,
+ IX86_BUILTIN_STOREAPS128_MASK,
+ IX86_BUILTIN_LOADUPD256_MASK,
+ IX86_BUILTIN_LOADUPD128_MASK,
+ IX86_BUILTIN_LOADUPS256_MASK,
+ IX86_BUILTIN_LOADUPS128_MASK,
+ IX86_BUILTIN_STOREUPD256_MASK,
+ IX86_BUILTIN_STOREUPD128_MASK,
+ IX86_BUILTIN_STOREUPS256_MASK,
+ IX86_BUILTIN_STOREUPS128_MASK,
+ IX86_BUILTIN_LOADDQUDI256_MASK,
+ IX86_BUILTIN_LOADDQUDI128_MASK,
+ IX86_BUILTIN_LOADDQUSI256_MASK,
+ IX86_BUILTIN_LOADDQUSI128_MASK,
+ IX86_BUILTIN_LOADDQUHI256_MASK,
+ IX86_BUILTIN_LOADDQUHI128_MASK,
+ IX86_BUILTIN_LOADDQUQI256_MASK,
+ IX86_BUILTIN_LOADDQUQI128_MASK,
+ IX86_BUILTIN_STOREDQUDI256_MASK,
+ IX86_BUILTIN_STOREDQUDI128_MASK,
+ IX86_BUILTIN_STOREDQUSI256_MASK,
+ IX86_BUILTIN_STOREDQUSI128_MASK,
+ IX86_BUILTIN_STOREDQUHI256_MASK,
+ IX86_BUILTIN_STOREDQUHI128_MASK,
+ IX86_BUILTIN_STOREDQUQI256_MASK,
+ IX86_BUILTIN_STOREDQUQI128_MASK,
+ IX86_BUILTIN_COMPRESSPDSTORE256,
+ IX86_BUILTIN_COMPRESSPDSTORE128,
+ IX86_BUILTIN_COMPRESSPSSTORE256,
+ IX86_BUILTIN_COMPRESSPSSTORE128,
+ IX86_BUILTIN_PCOMPRESSQSTORE256,
+ IX86_BUILTIN_PCOMPRESSQSTORE128,
+ IX86_BUILTIN_PCOMPRESSDSTORE256,
+ IX86_BUILTIN_PCOMPRESSDSTORE128,
+ IX86_BUILTIN_EXPANDPDLOAD256,
+ IX86_BUILTIN_EXPANDPDLOAD128,
+ IX86_BUILTIN_EXPANDPSLOAD256,
+ IX86_BUILTIN_EXPANDPSLOAD128,
+ IX86_BUILTIN_PEXPANDQLOAD256,
+ IX86_BUILTIN_PEXPANDQLOAD128,
+ IX86_BUILTIN_PEXPANDDLOAD256,
+ IX86_BUILTIN_PEXPANDDLOAD128,
+ IX86_BUILTIN_EXPANDPDLOAD256Z,
+ IX86_BUILTIN_EXPANDPDLOAD128Z,
+ IX86_BUILTIN_EXPANDPSLOAD256Z,
+ IX86_BUILTIN_EXPANDPSLOAD128Z,
+ IX86_BUILTIN_PEXPANDQLOAD256Z,
+ IX86_BUILTIN_PEXPANDQLOAD128Z,
+ IX86_BUILTIN_PEXPANDDLOAD256Z,
+ IX86_BUILTIN_PEXPANDDLOAD128Z,
+ IX86_BUILTIN_PALIGNR256_MASK,
+ IX86_BUILTIN_PALIGNR128_MASK,
+ IX86_BUILTIN_MOVDQA64_256_MASK,
+ IX86_BUILTIN_MOVDQA64_128_MASK,
+ IX86_BUILTIN_MOVDQA32_256_MASK,
+ IX86_BUILTIN_MOVDQA32_128_MASK,
+ IX86_BUILTIN_MOVAPD256_MASK,
+ IX86_BUILTIN_MOVAPD128_MASK,
+ IX86_BUILTIN_MOVAPS256_MASK,
+ IX86_BUILTIN_MOVAPS128_MASK,
+ IX86_BUILTIN_MOVDQUHI256_MASK,
+ IX86_BUILTIN_MOVDQUHI128_MASK,
+ IX86_BUILTIN_MOVDQUQI256_MASK,
+ IX86_BUILTIN_MOVDQUQI128_MASK,
+ IX86_BUILTIN_MINPS128_MASK,
+ IX86_BUILTIN_MAXPS128_MASK,
+ IX86_BUILTIN_MINPD128_MASK,
+ IX86_BUILTIN_MAXPD128_MASK,
+ IX86_BUILTIN_MAXPD256_MASK,
+ IX86_BUILTIN_MAXPS256_MASK,
+ IX86_BUILTIN_MINPD256_MASK,
+ IX86_BUILTIN_MINPS256_MASK,
+ IX86_BUILTIN_MULPS128_MASK,
+ IX86_BUILTIN_DIVPS128_MASK,
+ IX86_BUILTIN_MULPD128_MASK,
+ IX86_BUILTIN_DIVPD128_MASK,
+ IX86_BUILTIN_DIVPD256_MASK,
+ IX86_BUILTIN_DIVPS256_MASK,
+ IX86_BUILTIN_MULPD256_MASK,
+ IX86_BUILTIN_MULPS256_MASK,
+ IX86_BUILTIN_ADDPD128_MASK,
+ IX86_BUILTIN_ADDPD256_MASK,
+ IX86_BUILTIN_ADDPS128_MASK,
+ IX86_BUILTIN_ADDPS256_MASK,
+ IX86_BUILTIN_SUBPD128_MASK,
+ IX86_BUILTIN_SUBPD256_MASK,
+ IX86_BUILTIN_SUBPS128_MASK,
+ IX86_BUILTIN_SUBPS256_MASK,
+ IX86_BUILTIN_XORPD256_MASK,
+ IX86_BUILTIN_XORPD128_MASK,
+ IX86_BUILTIN_XORPS256_MASK,
+ IX86_BUILTIN_XORPS128_MASK,
+ IX86_BUILTIN_ORPD256_MASK,
+ IX86_BUILTIN_ORPD128_MASK,
+ IX86_BUILTIN_ORPS256_MASK,
+ IX86_BUILTIN_ORPS128_MASK,
+ IX86_BUILTIN_BROADCASTF32x2_256,
+ IX86_BUILTIN_BROADCASTI32x2_256,
+ IX86_BUILTIN_BROADCASTI32x2_128,
+ IX86_BUILTIN_BROADCASTF64X2_256,
+ IX86_BUILTIN_BROADCASTI64X2_256,
+ IX86_BUILTIN_BROADCASTF32X4_256,
+ IX86_BUILTIN_BROADCASTI32X4_256,
+ IX86_BUILTIN_EXTRACTF32X4_256,
+ IX86_BUILTIN_EXTRACTI32X4_256,
+ IX86_BUILTIN_DBPSADBW256,
+ IX86_BUILTIN_DBPSADBW128,
+ IX86_BUILTIN_CVTTPD2QQ256,
+ IX86_BUILTIN_CVTTPD2QQ128,
+ IX86_BUILTIN_CVTTPD2UQQ256,
+ IX86_BUILTIN_CVTTPD2UQQ128,
+ IX86_BUILTIN_CVTPD2QQ256,
+ IX86_BUILTIN_CVTPD2QQ128,
+ IX86_BUILTIN_CVTPD2UQQ256,
+ IX86_BUILTIN_CVTPD2UQQ128,
+ IX86_BUILTIN_CVTPD2UDQ256_MASK,
+ IX86_BUILTIN_CVTPD2UDQ128_MASK,
+ IX86_BUILTIN_CVTTPS2QQ256,
+ IX86_BUILTIN_CVTTPS2QQ128,
+ IX86_BUILTIN_CVTTPS2UQQ256,
+ IX86_BUILTIN_CVTTPS2UQQ128,
+ IX86_BUILTIN_CVTTPS2DQ256_MASK,
+ IX86_BUILTIN_CVTTPS2DQ128_MASK,
+ IX86_BUILTIN_CVTTPS2UDQ256,
+ IX86_BUILTIN_CVTTPS2UDQ128,
+ IX86_BUILTIN_CVTTPD2DQ256_MASK,
+ IX86_BUILTIN_CVTTPD2DQ128_MASK,
+ IX86_BUILTIN_CVTTPD2UDQ256_MASK,
+ IX86_BUILTIN_CVTTPD2UDQ128_MASK,
+ IX86_BUILTIN_CVTPD2DQ256_MASK,
+ IX86_BUILTIN_CVTPD2DQ128_MASK,
+ IX86_BUILTIN_CVTDQ2PD256_MASK,
+ IX86_BUILTIN_CVTDQ2PD128_MASK,
+ IX86_BUILTIN_CVTUDQ2PD256_MASK,
+ IX86_BUILTIN_CVTUDQ2PD128_MASK,
+ IX86_BUILTIN_CVTDQ2PS256_MASK,
+ IX86_BUILTIN_CVTDQ2PS128_MASK,
+ IX86_BUILTIN_CVTUDQ2PS256_MASK,
+ IX86_BUILTIN_CVTUDQ2PS128_MASK,
+ IX86_BUILTIN_CVTPS2PD256_MASK,
+ IX86_BUILTIN_CVTPS2PD128_MASK,
+ IX86_BUILTIN_PBROADCASTB256_MASK,
+ IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTB128_MASK,
+ IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTW256_MASK,
+ IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTW128_MASK,
+ IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTD256_MASK,
+ IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTD128_MASK,
+ IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTQ256_MASK,
+ IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTQ256_MEM_MASK,
+ IX86_BUILTIN_PBROADCASTQ128_MASK,
+ IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTQ128_MEM_MASK,
+ IX86_BUILTIN_BROADCASTSS256,
+ IX86_BUILTIN_BROADCASTSS128,
+ IX86_BUILTIN_BROADCASTSD256,
+ IX86_BUILTIN_EXTRACTF64X2_256,
+ IX86_BUILTIN_EXTRACTI64X2_256,
+ IX86_BUILTIN_INSERTF32X4_256,
+ IX86_BUILTIN_INSERTI32X4_256,
+ IX86_BUILTIN_PMOVSXBW256_MASK,
+ IX86_BUILTIN_PMOVSXBW128_MASK,
+ IX86_BUILTIN_PMOVSXBD256_MASK,
+ IX86_BUILTIN_PMOVSXBD128_MASK,
+ IX86_BUILTIN_PMOVSXBQ256_MASK,
+ IX86_BUILTIN_PMOVSXBQ128_MASK,
+ IX86_BUILTIN_PMOVSXWD256_MASK,
+ IX86_BUILTIN_PMOVSXWD128_MASK,
+ IX86_BUILTIN_PMOVSXWQ256_MASK,
+ IX86_BUILTIN_PMOVSXWQ128_MASK,
+ IX86_BUILTIN_PMOVSXDQ256_MASK,
+ IX86_BUILTIN_PMOVSXDQ128_MASK,
+ IX86_BUILTIN_PMOVZXBW256_MASK,
+ IX86_BUILTIN_PMOVZXBW128_MASK,
+ IX86_BUILTIN_PMOVZXBD256_MASK,
+ IX86_BUILTIN_PMOVZXBD128_MASK,
+ IX86_BUILTIN_PMOVZXBQ256_MASK,
+ IX86_BUILTIN_PMOVZXBQ128_MASK,
+ IX86_BUILTIN_PMOVZXWD256_MASK,
+ IX86_BUILTIN_PMOVZXWD128_MASK,
+ IX86_BUILTIN_PMOVZXWQ256_MASK,
+ IX86_BUILTIN_PMOVZXWQ128_MASK,
+ IX86_BUILTIN_PMOVZXDQ256_MASK,
+ IX86_BUILTIN_PMOVZXDQ128_MASK,
+ IX86_BUILTIN_REDUCEPD256_MASK,
+ IX86_BUILTIN_REDUCEPD128_MASK,
+ IX86_BUILTIN_REDUCEPS256_MASK,
+ IX86_BUILTIN_REDUCEPS128_MASK,
+ IX86_BUILTIN_REDUCESD_MASK,
+ IX86_BUILTIN_REDUCESS_MASK,
+ IX86_BUILTIN_VPERMVARHI256_MASK,
+ IX86_BUILTIN_VPERMVARHI128_MASK,
+ IX86_BUILTIN_VPERMT2VARHI256,
+ IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
+ IX86_BUILTIN_VPERMT2VARHI128,
+ IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
+ IX86_BUILTIN_VPERMI2VARHI256,
+ IX86_BUILTIN_VPERMI2VARHI128,
+ IX86_BUILTIN_RCP14PD256,
+ IX86_BUILTIN_RCP14PD128,
+ IX86_BUILTIN_RCP14PS256,
+ IX86_BUILTIN_RCP14PS128,
+ IX86_BUILTIN_RSQRT14PD256_MASK,
+ IX86_BUILTIN_RSQRT14PD128_MASK,
+ IX86_BUILTIN_RSQRT14PS256_MASK,
+ IX86_BUILTIN_RSQRT14PS128_MASK,
+ IX86_BUILTIN_SQRTPD256_MASK,
+ IX86_BUILTIN_SQRTPD128_MASK,
+ IX86_BUILTIN_SQRTPS256_MASK,
+ IX86_BUILTIN_SQRTPS128_MASK,
+ IX86_BUILTIN_PADDB128_MASK,
+ IX86_BUILTIN_PADDW128_MASK,
+ IX86_BUILTIN_PADDD128_MASK,
+ IX86_BUILTIN_PADDQ128_MASK,
+ IX86_BUILTIN_PSUBB128_MASK,
+ IX86_BUILTIN_PSUBW128_MASK,
+ IX86_BUILTIN_PSUBD128_MASK,
+ IX86_BUILTIN_PSUBQ128_MASK,
+ IX86_BUILTIN_PADDSB128_MASK,
+ IX86_BUILTIN_PADDSW128_MASK,
+ IX86_BUILTIN_PSUBSB128_MASK,
+ IX86_BUILTIN_PSUBSW128_MASK,
+ IX86_BUILTIN_PADDUSB128_MASK,
+ IX86_BUILTIN_PADDUSW128_MASK,
+ IX86_BUILTIN_PSUBUSB128_MASK,
+ IX86_BUILTIN_PSUBUSW128_MASK,
+ IX86_BUILTIN_PADDB256_MASK,
+ IX86_BUILTIN_PADDW256_MASK,
+ IX86_BUILTIN_PADDD256_MASK,
+ IX86_BUILTIN_PADDQ256_MASK,
+ IX86_BUILTIN_PADDSB256_MASK,
+ IX86_BUILTIN_PADDSW256_MASK,
+ IX86_BUILTIN_PADDUSB256_MASK,
+ IX86_BUILTIN_PADDUSW256_MASK,
+ IX86_BUILTIN_PSUBB256_MASK,
+ IX86_BUILTIN_PSUBW256_MASK,
+ IX86_BUILTIN_PSUBD256_MASK,
+ IX86_BUILTIN_PSUBQ256_MASK,
+ IX86_BUILTIN_PSUBSB256_MASK,
+ IX86_BUILTIN_PSUBSW256_MASK,
+ IX86_BUILTIN_PSUBUSB256_MASK,
+ IX86_BUILTIN_PSUBUSW256_MASK,
+ IX86_BUILTIN_SHUF_F64x2_256,
+ IX86_BUILTIN_SHUF_I64x2_256,
+ IX86_BUILTIN_SHUF_I32x4_256,
+ IX86_BUILTIN_SHUF_F32x4_256,
+ IX86_BUILTIN_PMOVWB128,
+ IX86_BUILTIN_PMOVWB256,
+ IX86_BUILTIN_PMOVSWB128,
+ IX86_BUILTIN_PMOVSWB256,
+ IX86_BUILTIN_PMOVUSWB128,
+ IX86_BUILTIN_PMOVUSWB256,
+ IX86_BUILTIN_PMOVDB128,
+ IX86_BUILTIN_PMOVDB256,
+ IX86_BUILTIN_PMOVSDB128,
+ IX86_BUILTIN_PMOVSDB256,
+ IX86_BUILTIN_PMOVUSDB128,
+ IX86_BUILTIN_PMOVUSDB256,
+ IX86_BUILTIN_PMOVDW128,
+ IX86_BUILTIN_PMOVDW256,
+ IX86_BUILTIN_PMOVSDW128,
+ IX86_BUILTIN_PMOVSDW256,
+ IX86_BUILTIN_PMOVUSDW128,
+ IX86_BUILTIN_PMOVUSDW256,
+ IX86_BUILTIN_PMOVQB128,
+ IX86_BUILTIN_PMOVQB256,
+ IX86_BUILTIN_PMOVSQB128,
+ IX86_BUILTIN_PMOVSQB256,
+ IX86_BUILTIN_PMOVUSQB128,
+ IX86_BUILTIN_PMOVUSQB256,
+ IX86_BUILTIN_PMOVQW128,
+ IX86_BUILTIN_PMOVQW256,
+ IX86_BUILTIN_PMOVSQW128,
+ IX86_BUILTIN_PMOVSQW256,
+ IX86_BUILTIN_PMOVUSQW128,
+ IX86_BUILTIN_PMOVUSQW256,
+ IX86_BUILTIN_PMOVQD128,
+ IX86_BUILTIN_PMOVQD256,
+ IX86_BUILTIN_PMOVSQD128,
+ IX86_BUILTIN_PMOVSQD256,
+ IX86_BUILTIN_PMOVUSQD128,
+ IX86_BUILTIN_PMOVUSQD256,
+ IX86_BUILTIN_RANGEPD256,
+ IX86_BUILTIN_RANGEPD128,
+ IX86_BUILTIN_RANGEPS256,
+ IX86_BUILTIN_RANGEPS128,
+ IX86_BUILTIN_GETEXPPS256,
+ IX86_BUILTIN_GETEXPPD256,
+ IX86_BUILTIN_GETEXPPS128,
+ IX86_BUILTIN_GETEXPPD128,
+ IX86_BUILTIN_FIXUPIMMPD256_MASK,
+ IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
+ IX86_BUILTIN_FIXUPIMMPS256_MASK,
+ IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
+ IX86_BUILTIN_FIXUPIMMPD128_MASK,
+ IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
+ IX86_BUILTIN_FIXUPIMMPS128_MASK,
+ IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
+ IX86_BUILTIN_PABSQ256,
+ IX86_BUILTIN_PABSQ128,
+ IX86_BUILTIN_PABSD256_MASK,
+ IX86_BUILTIN_PABSD128_MASK,
+ IX86_BUILTIN_PMULHRSW256_MASK,
+ IX86_BUILTIN_PMULHRSW128_MASK,
+ IX86_BUILTIN_PMULHUW128_MASK,
+ IX86_BUILTIN_PMULHUW256_MASK,
+ IX86_BUILTIN_PMULHW256_MASK,
+ IX86_BUILTIN_PMULHW128_MASK,
+ IX86_BUILTIN_PMULLW256_MASK,
+ IX86_BUILTIN_PMULLW128_MASK,
+ IX86_BUILTIN_PMULLQ256,
+ IX86_BUILTIN_PMULLQ128,
+ IX86_BUILTIN_ANDPD256_MASK,
+ IX86_BUILTIN_ANDPD128_MASK,
+ IX86_BUILTIN_ANDPS256_MASK,
+ IX86_BUILTIN_ANDPS128_MASK,
+ IX86_BUILTIN_ANDNPD256_MASK,
+ IX86_BUILTIN_ANDNPD128_MASK,
+ IX86_BUILTIN_ANDNPS256_MASK,
+ IX86_BUILTIN_ANDNPS128_MASK,
+ IX86_BUILTIN_PSLLWI128_MASK,
+ IX86_BUILTIN_PSLLDI128_MASK,
+ IX86_BUILTIN_PSLLQI128_MASK,
+ IX86_BUILTIN_PSLLW128_MASK,
+ IX86_BUILTIN_PSLLD128_MASK,
+ IX86_BUILTIN_PSLLQ128_MASK,
+ IX86_BUILTIN_PSLLWI256_MASK ,
+ IX86_BUILTIN_PSLLW256_MASK,
+ IX86_BUILTIN_PSLLDI256_MASK,
+ IX86_BUILTIN_PSLLD256_MASK,
+ IX86_BUILTIN_PSLLQI256_MASK,
+ IX86_BUILTIN_PSLLQ256_MASK,
+ IX86_BUILTIN_PSRADI128_MASK,
+ IX86_BUILTIN_PSRAD128_MASK,
+ IX86_BUILTIN_PSRADI256_MASK,
+ IX86_BUILTIN_PSRAD256_MASK,
+ IX86_BUILTIN_PSRAQI128_MASK,
+ IX86_BUILTIN_PSRAQ128_MASK,
+ IX86_BUILTIN_PSRAQI256_MASK,
+ IX86_BUILTIN_PSRAQ256_MASK,
+ IX86_BUILTIN_PANDD256,
+ IX86_BUILTIN_PANDD128,
+ IX86_BUILTIN_PSRLDI128_MASK,
+ IX86_BUILTIN_PSRLD128_MASK,
+ IX86_BUILTIN_PSRLDI256_MASK,
+ IX86_BUILTIN_PSRLD256_MASK,
+ IX86_BUILTIN_PSRLQI128_MASK,
+ IX86_BUILTIN_PSRLQ128_MASK,
+ IX86_BUILTIN_PSRLQI256_MASK,
+ IX86_BUILTIN_PSRLQ256_MASK,
+ IX86_BUILTIN_PANDQ256,
+ IX86_BUILTIN_PANDQ128,
+ IX86_BUILTIN_PANDND256,
+ IX86_BUILTIN_PANDND128,
+ IX86_BUILTIN_PANDNQ256,
+ IX86_BUILTIN_PANDNQ128,
+ IX86_BUILTIN_PORD256,
+ IX86_BUILTIN_PORD128,
+ IX86_BUILTIN_PORQ256,
+ IX86_BUILTIN_PORQ128,
+ IX86_BUILTIN_PXORD256,
+ IX86_BUILTIN_PXORD128,
+ IX86_BUILTIN_PXORQ256,
+ IX86_BUILTIN_PXORQ128,
+ IX86_BUILTIN_PACKSSWB256_MASK,
+ IX86_BUILTIN_PACKSSWB128_MASK,
+ IX86_BUILTIN_PACKUSWB256_MASK,
+ IX86_BUILTIN_PACKUSWB128_MASK,
+ IX86_BUILTIN_RNDSCALEPS256,
+ IX86_BUILTIN_RNDSCALEPD256,
+ IX86_BUILTIN_RNDSCALEPS128,
+ IX86_BUILTIN_RNDSCALEPD128,
+ IX86_BUILTIN_VTERNLOGQ256_MASK,
+ IX86_BUILTIN_VTERNLOGQ256_MASKZ,
+ IX86_BUILTIN_VTERNLOGD256_MASK,
+ IX86_BUILTIN_VTERNLOGD256_MASKZ,
+ IX86_BUILTIN_VTERNLOGQ128_MASK,
+ IX86_BUILTIN_VTERNLOGQ128_MASKZ,
+ IX86_BUILTIN_VTERNLOGD128_MASK,
+ IX86_BUILTIN_VTERNLOGD128_MASKZ,
+ IX86_BUILTIN_SCALEFPD256,
+ IX86_BUILTIN_SCALEFPS256,
+ IX86_BUILTIN_SCALEFPD128,
+ IX86_BUILTIN_SCALEFPS128,
+ IX86_BUILTIN_VFMADDPD256_MASK,
+ IX86_BUILTIN_VFMADDPD256_MASK3,
+ IX86_BUILTIN_VFMADDPD256_MASKZ,
+ IX86_BUILTIN_VFMADDPD128_MASK,
+ IX86_BUILTIN_VFMADDPD128_MASK3,
+ IX86_BUILTIN_VFMADDPD128_MASKZ,
+ IX86_BUILTIN_VFMADDPS256_MASK,
+ IX86_BUILTIN_VFMADDPS256_MASK3,
+ IX86_BUILTIN_VFMADDPS256_MASKZ,
+ IX86_BUILTIN_VFMADDPS128_MASK,
+ IX86_BUILTIN_VFMADDPS128_MASK3,
+ IX86_BUILTIN_VFMADDPS128_MASKZ,
+ IX86_BUILTIN_VFMSUBPD256_MASK3,
+ IX86_BUILTIN_VFMSUBPD128_MASK3,
+ IX86_BUILTIN_VFMSUBPS256_MASK3,
+ IX86_BUILTIN_VFMSUBPS128_MASK3,
+ IX86_BUILTIN_VFNMADDPD256_MASK,
+ IX86_BUILTIN_VFNMADDPD128_MASK,
+ IX86_BUILTIN_VFNMADDPS256_MASK,
+ IX86_BUILTIN_VFNMADDPS128_MASK,
+ IX86_BUILTIN_VFNMSUBPD256_MASK,
+ IX86_BUILTIN_VFNMSUBPD256_MASK3,
+ IX86_BUILTIN_VFNMSUBPD128_MASK,
+ IX86_BUILTIN_VFNMSUBPD128_MASK3,
+ IX86_BUILTIN_VFNMSUBPS256_MASK,
+ IX86_BUILTIN_VFNMSUBPS256_MASK3,
+ IX86_BUILTIN_VFNMSUBPS128_MASK,
+ IX86_BUILTIN_VFNMSUBPS128_MASK3,
+ IX86_BUILTIN_VFMADDSUBPD256_MASK,
+ IX86_BUILTIN_VFMADDSUBPD256_MASK3,
+ IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
+ IX86_BUILTIN_VFMADDSUBPD128_MASK,
+ IX86_BUILTIN_VFMADDSUBPD128_MASK3,
+ IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
+ IX86_BUILTIN_VFMADDSUBPS256_MASK,
+ IX86_BUILTIN_VFMADDSUBPS256_MASK3,
+ IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
+ IX86_BUILTIN_VFMADDSUBPS128_MASK,
+ IX86_BUILTIN_VFMADDSUBPS128_MASK3,
+ IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
+ IX86_BUILTIN_VFMSUBADDPD256_MASK3,
+ IX86_BUILTIN_VFMSUBADDPD128_MASK3,
+ IX86_BUILTIN_VFMSUBADDPS256_MASK3,
+ IX86_BUILTIN_VFMSUBADDPS128_MASK3,
+ IX86_BUILTIN_INSERTF64X2_256,
+ IX86_BUILTIN_INSERTI64X2_256,
+ IX86_BUILTIN_PSRAVV16HI,
+ IX86_BUILTIN_PSRAVV8HI,
+ IX86_BUILTIN_PMADDUBSW256_MASK,
+ IX86_BUILTIN_PMADDUBSW128_MASK,
+ IX86_BUILTIN_PMADDWD256_MASK,
+ IX86_BUILTIN_PMADDWD128_MASK,
+ IX86_BUILTIN_PSRLVV16HI,
+ IX86_BUILTIN_PSRLVV8HI,
+ IX86_BUILTIN_CVTPS2DQ256_MASK,
+ IX86_BUILTIN_CVTPS2DQ128_MASK,
+ IX86_BUILTIN_CVTPS2UDQ256,
+ IX86_BUILTIN_CVTPS2UDQ128,
+ IX86_BUILTIN_CVTPS2QQ256,
+ IX86_BUILTIN_CVTPS2QQ128,
+ IX86_BUILTIN_CVTPS2UQQ256,
+ IX86_BUILTIN_CVTPS2UQQ128,
+ IX86_BUILTIN_GETMANTPS256,
+ IX86_BUILTIN_GETMANTPS128,
+ IX86_BUILTIN_GETMANTPD256,
+ IX86_BUILTIN_GETMANTPD128,
+ IX86_BUILTIN_MOVDDUP256_MASK,
+ IX86_BUILTIN_MOVDDUP128_MASK,
+ IX86_BUILTIN_MOVSHDUP256_MASK,
+ IX86_BUILTIN_MOVSHDUP128_MASK,
+ IX86_BUILTIN_MOVSLDUP256_MASK,
+ IX86_BUILTIN_MOVSLDUP128_MASK,
+ IX86_BUILTIN_CVTQQ2PS256,
+ IX86_BUILTIN_CVTQQ2PS128,
+ IX86_BUILTIN_CVTUQQ2PS256,
+ IX86_BUILTIN_CVTUQQ2PS128,
+ IX86_BUILTIN_CVTQQ2PD256,
+ IX86_BUILTIN_CVTQQ2PD128,
+ IX86_BUILTIN_CVTUQQ2PD256,
+ IX86_BUILTIN_CVTUQQ2PD128,
+ IX86_BUILTIN_VPERMT2VARQ256,
+ IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
+ IX86_BUILTIN_VPERMT2VARD256,
+ IX86_BUILTIN_VPERMT2VARD256_MASKZ,
+ IX86_BUILTIN_VPERMI2VARQ256,
+ IX86_BUILTIN_VPERMI2VARD256,
+ IX86_BUILTIN_VPERMT2VARPD256,
+ IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
+ IX86_BUILTIN_VPERMT2VARPS256,
+ IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
+ IX86_BUILTIN_VPERMI2VARPD256,
+ IX86_BUILTIN_VPERMI2VARPS256,
+ IX86_BUILTIN_VPERMT2VARQ128,
+ IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
+ IX86_BUILTIN_VPERMT2VARD128,
+ IX86_BUILTIN_VPERMT2VARD128_MASKZ,
+ IX86_BUILTIN_VPERMI2VARQ128,
+ IX86_BUILTIN_VPERMI2VARD128,
+ IX86_BUILTIN_VPERMT2VARPD128,
+ IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
+ IX86_BUILTIN_VPERMT2VARPS128,
+ IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
+ IX86_BUILTIN_VPERMI2VARPD128,
+ IX86_BUILTIN_VPERMI2VARPS128,
+ IX86_BUILTIN_PSHUFB256_MASK,
+ IX86_BUILTIN_PSHUFB128_MASK,
+ IX86_BUILTIN_PSHUFHW256_MASK,
+ IX86_BUILTIN_PSHUFHW128_MASK,
+ IX86_BUILTIN_PSHUFLW256_MASK,
+ IX86_BUILTIN_PSHUFLW128_MASK,
+ IX86_BUILTIN_PSHUFD256_MASK,
+ IX86_BUILTIN_PSHUFD128_MASK,
+ IX86_BUILTIN_SHUFPD256_MASK,
+ IX86_BUILTIN_SHUFPD128_MASK,
+ IX86_BUILTIN_SHUFPS256_MASK,
+ IX86_BUILTIN_SHUFPS128_MASK,
+ IX86_BUILTIN_PROLVQ256,
+ IX86_BUILTIN_PROLVQ128,
+ IX86_BUILTIN_PROLQ256,
+ IX86_BUILTIN_PROLQ128,
+ IX86_BUILTIN_PRORVQ256,
+ IX86_BUILTIN_PRORVQ128,
+ IX86_BUILTIN_PRORQ256,
+ IX86_BUILTIN_PRORQ128,
+ IX86_BUILTIN_PSRAVQ128,
+ IX86_BUILTIN_PSRAVQ256,
+ IX86_BUILTIN_PSLLVV4DI_MASK,
+ IX86_BUILTIN_PSLLVV2DI_MASK,
+ IX86_BUILTIN_PSLLVV8SI_MASK,
+ IX86_BUILTIN_PSLLVV4SI_MASK,
+ IX86_BUILTIN_PSRAVV8SI_MASK,
+ IX86_BUILTIN_PSRAVV4SI_MASK,
+ IX86_BUILTIN_PSRLVV4DI_MASK,
+ IX86_BUILTIN_PSRLVV2DI_MASK,
+ IX86_BUILTIN_PSRLVV8SI_MASK,
+ IX86_BUILTIN_PSRLVV4SI_MASK,
+ IX86_BUILTIN_PSRAWI256_MASK,
+ IX86_BUILTIN_PSRAW256_MASK,
+ IX86_BUILTIN_PSRAWI128_MASK,
+ IX86_BUILTIN_PSRAW128_MASK,
+ IX86_BUILTIN_PSRLWI256_MASK,
+ IX86_BUILTIN_PSRLW256_MASK,
+ IX86_BUILTIN_PSRLWI128_MASK,
+ IX86_BUILTIN_PSRLW128_MASK,
+ IX86_BUILTIN_PRORVD256,
+ IX86_BUILTIN_PROLVD256,
+ IX86_BUILTIN_PRORD256,
+ IX86_BUILTIN_PROLD256,
+ IX86_BUILTIN_PRORVD128,
+ IX86_BUILTIN_PROLVD128,
+ IX86_BUILTIN_PRORD128,
+ IX86_BUILTIN_PROLD128,
+ IX86_BUILTIN_FPCLASSPD256,
+ IX86_BUILTIN_FPCLASSPD128,
+ IX86_BUILTIN_FPCLASSSD,
+ IX86_BUILTIN_FPCLASSPS256,
+ IX86_BUILTIN_FPCLASSPS128,
+ IX86_BUILTIN_FPCLASSSS,
+ IX86_BUILTIN_CVTB2MASK128,
+ IX86_BUILTIN_CVTB2MASK256,
+ IX86_BUILTIN_CVTW2MASK128,
+ IX86_BUILTIN_CVTW2MASK256,
+ IX86_BUILTIN_CVTD2MASK128,
+ IX86_BUILTIN_CVTD2MASK256,
+ IX86_BUILTIN_CVTQ2MASK128,
+ IX86_BUILTIN_CVTQ2MASK256,
+ IX86_BUILTIN_CVTMASK2B128,
+ IX86_BUILTIN_CVTMASK2B256,
+ IX86_BUILTIN_CVTMASK2W128,
+ IX86_BUILTIN_CVTMASK2W256,
+ IX86_BUILTIN_CVTMASK2D128,
+ IX86_BUILTIN_CVTMASK2D256,
+ IX86_BUILTIN_CVTMASK2Q128,
+ IX86_BUILTIN_CVTMASK2Q256,
+ IX86_BUILTIN_PCMPEQB128_MASK,
+ IX86_BUILTIN_PCMPEQB256_MASK,
+ IX86_BUILTIN_PCMPEQW128_MASK,
+ IX86_BUILTIN_PCMPEQW256_MASK,
+ IX86_BUILTIN_PCMPEQD128_MASK,
+ IX86_BUILTIN_PCMPEQD256_MASK,
+ IX86_BUILTIN_PCMPEQQ128_MASK,
+ IX86_BUILTIN_PCMPEQQ256_MASK,
+ IX86_BUILTIN_PCMPGTB128_MASK,
+ IX86_BUILTIN_PCMPGTB256_MASK,
+ IX86_BUILTIN_PCMPGTW128_MASK,
+ IX86_BUILTIN_PCMPGTW256_MASK,
+ IX86_BUILTIN_PCMPGTD128_MASK,
+ IX86_BUILTIN_PCMPGTD256_MASK,
+ IX86_BUILTIN_PCMPGTQ128_MASK,
+ IX86_BUILTIN_PCMPGTQ256_MASK,
+ IX86_BUILTIN_PTESTMB128,
+ IX86_BUILTIN_PTESTMB256,
+ IX86_BUILTIN_PTESTMW128,
+ IX86_BUILTIN_PTESTMW256,
+ IX86_BUILTIN_PTESTMD128,
+ IX86_BUILTIN_PTESTMD256,
+ IX86_BUILTIN_PTESTMQ128,
+ IX86_BUILTIN_PTESTMQ256,
+ IX86_BUILTIN_PTESTNMB128,
+ IX86_BUILTIN_PTESTNMB256,
+ IX86_BUILTIN_PTESTNMW128,
+ IX86_BUILTIN_PTESTNMW256,
+ IX86_BUILTIN_PTESTNMD128,
+ IX86_BUILTIN_PTESTNMD256,
+ IX86_BUILTIN_PTESTNMQ128,
+ IX86_BUILTIN_PTESTNMQ256,
+ IX86_BUILTIN_PBROADCASTMB128,
+ IX86_BUILTIN_PBROADCASTMB256,
+ IX86_BUILTIN_PBROADCASTMW128,
+ IX86_BUILTIN_PBROADCASTMW256,
+ IX86_BUILTIN_COMPRESSPD256,
+ IX86_BUILTIN_COMPRESSPD128,
+ IX86_BUILTIN_COMPRESSPS256,
+ IX86_BUILTIN_COMPRESSPS128,
+ IX86_BUILTIN_PCOMPRESSQ256,
+ IX86_BUILTIN_PCOMPRESSQ128,
+ IX86_BUILTIN_PCOMPRESSD256,
+ IX86_BUILTIN_PCOMPRESSD128,
+ IX86_BUILTIN_EXPANDPD256,
+ IX86_BUILTIN_EXPANDPD128,
+ IX86_BUILTIN_EXPANDPS256,
+ IX86_BUILTIN_EXPANDPS128,
+ IX86_BUILTIN_PEXPANDQ256,
+ IX86_BUILTIN_PEXPANDQ128,
+ IX86_BUILTIN_PEXPANDD256,
+ IX86_BUILTIN_PEXPANDD128,
+ IX86_BUILTIN_EXPANDPD256Z,
+ IX86_BUILTIN_EXPANDPD128Z,
+ IX86_BUILTIN_EXPANDPS256Z,
+ IX86_BUILTIN_EXPANDPS128Z,
+ IX86_BUILTIN_PEXPANDQ256Z,
+ IX86_BUILTIN_PEXPANDQ128Z,
+ IX86_BUILTIN_PEXPANDD256Z,
+ IX86_BUILTIN_PEXPANDD128Z,
+ IX86_BUILTIN_PMAXSD256_MASK,
+ IX86_BUILTIN_PMINSD256_MASK,
+ IX86_BUILTIN_PMAXUD256_MASK,
+ IX86_BUILTIN_PMINUD256_MASK,
+ IX86_BUILTIN_PMAXSD128_MASK,
+ IX86_BUILTIN_PMINSD128_MASK,
+ IX86_BUILTIN_PMAXUD128_MASK,
+ IX86_BUILTIN_PMINUD128_MASK,
+ IX86_BUILTIN_PMAXSQ256_MASK,
+ IX86_BUILTIN_PMINSQ256_MASK,
+ IX86_BUILTIN_PMAXUQ256_MASK,
+ IX86_BUILTIN_PMINUQ256_MASK,
+ IX86_BUILTIN_PMAXSQ128_MASK,
+ IX86_BUILTIN_PMINSQ128_MASK,
+ IX86_BUILTIN_PMAXUQ128_MASK,
+ IX86_BUILTIN_PMINUQ128_MASK,
+ IX86_BUILTIN_PMINSB256_MASK,
+ IX86_BUILTIN_PMINUB256_MASK,
+ IX86_BUILTIN_PMAXSB256_MASK,
+ IX86_BUILTIN_PMAXUB256_MASK,
+ IX86_BUILTIN_PMINSB128_MASK,
+ IX86_BUILTIN_PMINUB128_MASK,
+ IX86_BUILTIN_PMAXSB128_MASK,
+ IX86_BUILTIN_PMAXUB128_MASK,
+ IX86_BUILTIN_PMINSW256_MASK,
+ IX86_BUILTIN_PMINUW256_MASK,
+ IX86_BUILTIN_PMAXSW256_MASK,
+ IX86_BUILTIN_PMAXUW256_MASK,
+ IX86_BUILTIN_PMINSW128_MASK,
+ IX86_BUILTIN_PMINUW128_MASK,
+ IX86_BUILTIN_PMAXSW128_MASK,
+ IX86_BUILTIN_PMAXUW128_MASK,
+ IX86_BUILTIN_VPCONFLICTQ256,
+ IX86_BUILTIN_VPCONFLICTD256,
+ IX86_BUILTIN_VPCLZCNTQ256,
+ IX86_BUILTIN_VPCLZCNTD256,
+ IX86_BUILTIN_UNPCKHPD256_MASK,
+ IX86_BUILTIN_UNPCKHPD128_MASK,
+ IX86_BUILTIN_UNPCKHPS256_MASK,
+ IX86_BUILTIN_UNPCKHPS128_MASK,
+ IX86_BUILTIN_UNPCKLPD256_MASK,
+ IX86_BUILTIN_UNPCKLPD128_MASK,
+ IX86_BUILTIN_UNPCKLPS256_MASK,
+ IX86_BUILTIN_VPCONFLICTQ128,
+ IX86_BUILTIN_VPCONFLICTD128,
+ IX86_BUILTIN_VPCLZCNTQ128,
+ IX86_BUILTIN_VPCLZCNTD128,
+ IX86_BUILTIN_UNPCKLPS128_MASK,
+ IX86_BUILTIN_ALIGND256,
+ IX86_BUILTIN_ALIGNQ256,
+ IX86_BUILTIN_ALIGND128,
+ IX86_BUILTIN_ALIGNQ128,
+ IX86_BUILTIN_CVTPS2PH256_MASK,
+ IX86_BUILTIN_CVTPS2PH_MASK,
+ IX86_BUILTIN_CVTPH2PS_MASK,
+ IX86_BUILTIN_CVTPH2PS256_MASK,
+ IX86_BUILTIN_PUNPCKHDQ128_MASK,
+ IX86_BUILTIN_PUNPCKHDQ256_MASK,
+ IX86_BUILTIN_PUNPCKHQDQ128_MASK,
+ IX86_BUILTIN_PUNPCKHQDQ256_MASK,
+ IX86_BUILTIN_PUNPCKLDQ128_MASK,
+ IX86_BUILTIN_PUNPCKLDQ256_MASK,
+ IX86_BUILTIN_PUNPCKLQDQ128_MASK,
+ IX86_BUILTIN_PUNPCKLQDQ256_MASK,
+ IX86_BUILTIN_PUNPCKHBW128_MASK,
+ IX86_BUILTIN_PUNPCKHBW256_MASK,
+ IX86_BUILTIN_PUNPCKHWD128_MASK,
+ IX86_BUILTIN_PUNPCKHWD256_MASK,
+ IX86_BUILTIN_PUNPCKLBW128_MASK,
+ IX86_BUILTIN_PUNPCKLBW256_MASK,
+ IX86_BUILTIN_PUNPCKLWD128_MASK,
+ IX86_BUILTIN_PUNPCKLWD256_MASK,
+ IX86_BUILTIN_PSLLVV16HI,
+ IX86_BUILTIN_PSLLVV8HI,
+ IX86_BUILTIN_PACKSSDW256_MASK,
+ IX86_BUILTIN_PACKSSDW128_MASK,
+ IX86_BUILTIN_PACKUSDW256_MASK,
+ IX86_BUILTIN_PACKUSDW128_MASK,
+ IX86_BUILTIN_PAVGB256_MASK,
+ IX86_BUILTIN_PAVGW256_MASK,
+ IX86_BUILTIN_PAVGB128_MASK,
+ IX86_BUILTIN_PAVGW128_MASK,
+ IX86_BUILTIN_VPERMVARSF256_MASK,
+ IX86_BUILTIN_VPERMVARDF256_MASK,
+ IX86_BUILTIN_VPERMDF256_MASK,
+ IX86_BUILTIN_PABSB256_MASK,
+ IX86_BUILTIN_PABSB128_MASK,
+ IX86_BUILTIN_PABSW256_MASK,
+ IX86_BUILTIN_PABSW128_MASK,
+ IX86_BUILTIN_VPERMILVARPD_MASK,
+ IX86_BUILTIN_VPERMILVARPS_MASK,
+ IX86_BUILTIN_VPERMILVARPD256_MASK,
+ IX86_BUILTIN_VPERMILVARPS256_MASK,
+ IX86_BUILTIN_VPERMILPD_MASK,
+ IX86_BUILTIN_VPERMILPS_MASK,
+ IX86_BUILTIN_VPERMILPD256_MASK,
+ IX86_BUILTIN_VPERMILPS256_MASK,
+ IX86_BUILTIN_BLENDMQ256,
+ IX86_BUILTIN_BLENDMD256,
+ IX86_BUILTIN_BLENDMPD256,
+ IX86_BUILTIN_BLENDMPS256,
+ IX86_BUILTIN_BLENDMQ128,
+ IX86_BUILTIN_BLENDMD128,
+ IX86_BUILTIN_BLENDMPD128,
+ IX86_BUILTIN_BLENDMPS128,
+ IX86_BUILTIN_BLENDMW256,
+ IX86_BUILTIN_BLENDMB256,
+ IX86_BUILTIN_BLENDMW128,
+ IX86_BUILTIN_BLENDMB128,
+ IX86_BUILTIN_PMULLD256_MASK,
+ IX86_BUILTIN_PMULLD128_MASK,
+ IX86_BUILTIN_PMULUDQ256_MASK,
+ IX86_BUILTIN_PMULDQ256_MASK,
+ IX86_BUILTIN_PMULDQ128_MASK,
+ IX86_BUILTIN_PMULUDQ128_MASK,
+ IX86_BUILTIN_CVTPD2PS256_MASK,
+ IX86_BUILTIN_CVTPD2PS_MASK,
+ IX86_BUILTIN_VPERMVARSI256_MASK,
+ IX86_BUILTIN_VPERMVARDI256_MASK,
+ IX86_BUILTIN_VPERMDI256_MASK,
+ IX86_BUILTIN_CMPQ256,
+ IX86_BUILTIN_CMPD256,
+ IX86_BUILTIN_UCMPQ256,
+ IX86_BUILTIN_UCMPD256,
+ IX86_BUILTIN_CMPB256,
+ IX86_BUILTIN_CMPW256,
+ IX86_BUILTIN_UCMPB256,
+ IX86_BUILTIN_UCMPW256,
+ IX86_BUILTIN_CMPPD256_MASK,
+ IX86_BUILTIN_CMPPS256_MASK,
+ IX86_BUILTIN_CMPQ128,
+ IX86_BUILTIN_CMPD128,
+ IX86_BUILTIN_UCMPQ128,
+ IX86_BUILTIN_UCMPD128,
+ IX86_BUILTIN_CMPB128,
+ IX86_BUILTIN_CMPW128,
+ IX86_BUILTIN_UCMPB128,
+ IX86_BUILTIN_UCMPW128,
+ IX86_BUILTIN_CMPPD128_MASK,
+ IX86_BUILTIN_CMPPS128_MASK,
+
+ IX86_BUILTIN_GATHER3SIV8SF,
+ IX86_BUILTIN_GATHER3SIV4SF,
+ IX86_BUILTIN_GATHER3SIV4DF,
+ IX86_BUILTIN_GATHER3SIV2DF,
+ IX86_BUILTIN_GATHER3DIV8SF,
+ IX86_BUILTIN_GATHER3DIV4SF,
+ IX86_BUILTIN_GATHER3DIV4DF,
+ IX86_BUILTIN_GATHER3DIV2DF,
+ IX86_BUILTIN_GATHER3SIV8SI,
+ IX86_BUILTIN_GATHER3SIV4SI,
+ IX86_BUILTIN_GATHER3SIV4DI,
+ IX86_BUILTIN_GATHER3SIV2DI,
+ IX86_BUILTIN_GATHER3DIV8SI,
+ IX86_BUILTIN_GATHER3DIV4SI,
+ IX86_BUILTIN_GATHER3DIV4DI,
+ IX86_BUILTIN_GATHER3DIV2DI,
+ IX86_BUILTIN_SCATTERSIV8SF,
+ IX86_BUILTIN_SCATTERSIV4SF,
+ IX86_BUILTIN_SCATTERSIV4DF,
+ IX86_BUILTIN_SCATTERSIV2DF,
+ IX86_BUILTIN_SCATTERDIV8SF,
+ IX86_BUILTIN_SCATTERDIV4SF,
+ IX86_BUILTIN_SCATTERDIV4DF,
+ IX86_BUILTIN_SCATTERDIV2DF,
+ IX86_BUILTIN_SCATTERSIV8SI,
+ IX86_BUILTIN_SCATTERSIV4SI,
+ IX86_BUILTIN_SCATTERSIV4DI,
+ IX86_BUILTIN_SCATTERSIV2DI,
+ IX86_BUILTIN_SCATTERDIV8SI,
+ IX86_BUILTIN_SCATTERDIV4SI,
+ IX86_BUILTIN_SCATTERDIV4DI,
+ IX86_BUILTIN_SCATTERDIV2DI,
+
+ /* AVX512DQ. */
+ IX86_BUILTIN_RANGESD128,
+ IX86_BUILTIN_RANGESS128,
+ IX86_BUILTIN_KUNPCKWD,
+ IX86_BUILTIN_KUNPCKDQ,
+ IX86_BUILTIN_BROADCASTF32x2_512,
+ IX86_BUILTIN_BROADCASTI32x2_512,
+ IX86_BUILTIN_BROADCASTF64X2_512,
+ IX86_BUILTIN_BROADCASTI64X2_512,
+ IX86_BUILTIN_BROADCASTF32X8_512,
+ IX86_BUILTIN_BROADCASTI32X8_512,
+ IX86_BUILTIN_EXTRACTF64X2_512,
+ IX86_BUILTIN_EXTRACTF32X8,
+ IX86_BUILTIN_EXTRACTI64X2_512,
+ IX86_BUILTIN_EXTRACTI32X8,
+ IX86_BUILTIN_REDUCEPD512_MASK,
+ IX86_BUILTIN_REDUCEPS512_MASK,
+ IX86_BUILTIN_PMULLQ512,
+ IX86_BUILTIN_XORPD512,
+ IX86_BUILTIN_XORPS512,
+ IX86_BUILTIN_ORPD512,
+ IX86_BUILTIN_ORPS512,
+ IX86_BUILTIN_ANDPD512,
+ IX86_BUILTIN_ANDPS512,
+ IX86_BUILTIN_ANDNPD512,
+ IX86_BUILTIN_ANDNPS512,
+ IX86_BUILTIN_INSERTF32X8,
+ IX86_BUILTIN_INSERTI32X8,
+ IX86_BUILTIN_INSERTF64X2_512,
+ IX86_BUILTIN_INSERTI64X2_512,
+ IX86_BUILTIN_FPCLASSPD512,
+ IX86_BUILTIN_FPCLASSPS512,
+ IX86_BUILTIN_CVTD2MASK512,
+ IX86_BUILTIN_CVTQ2MASK512,
+ IX86_BUILTIN_CVTMASK2D512,
+ IX86_BUILTIN_CVTMASK2Q512,
+ IX86_BUILTIN_CVTPD2QQ512,
+ IX86_BUILTIN_CVTPS2QQ512,
+ IX86_BUILTIN_CVTPD2UQQ512,
+ IX86_BUILTIN_CVTPS2UQQ512,
+ IX86_BUILTIN_CVTQQ2PS512,
+ IX86_BUILTIN_CVTUQQ2PS512,
+ IX86_BUILTIN_CVTQQ2PD512,
+ IX86_BUILTIN_CVTUQQ2PD512,
+ IX86_BUILTIN_CVTTPS2QQ512,
+ IX86_BUILTIN_CVTTPS2UQQ512,
+ IX86_BUILTIN_CVTTPD2QQ512,
+ IX86_BUILTIN_CVTTPD2UQQ512,
+ IX86_BUILTIN_RANGEPS512,
+ IX86_BUILTIN_RANGEPD512,
+
+ /* AVX512BW. */
+ IX86_BUILTIN_PACKUSDW512,
+ IX86_BUILTIN_PACKSSDW512,
+ IX86_BUILTIN_LOADDQUHI512_MASK,
+ IX86_BUILTIN_LOADDQUQI512_MASK,
+ IX86_BUILTIN_PSLLDQ512,
+ IX86_BUILTIN_PSRLDQ512,
+ IX86_BUILTIN_STOREDQUHI512_MASK,
+ IX86_BUILTIN_STOREDQUQI512_MASK,
+ IX86_BUILTIN_PALIGNR512,
+ IX86_BUILTIN_PALIGNR512_MASK,
+ IX86_BUILTIN_MOVDQUHI512_MASK,
+ IX86_BUILTIN_MOVDQUQI512_MASK,
+ IX86_BUILTIN_PSADBW512,
+ IX86_BUILTIN_DBPSADBW512,
+ IX86_BUILTIN_PBROADCASTB512,
+ IX86_BUILTIN_PBROADCASTB512_GPR,
+ IX86_BUILTIN_PBROADCASTW512,
+ IX86_BUILTIN_PBROADCASTW512_GPR,
+ IX86_BUILTIN_PMOVSXBW512_MASK,
+ IX86_BUILTIN_PMOVZXBW512_MASK,
+ IX86_BUILTIN_VPERMVARHI512_MASK,
+ IX86_BUILTIN_VPERMT2VARHI512,
+ IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
+ IX86_BUILTIN_VPERMI2VARHI512,
+ IX86_BUILTIN_PAVGB512,
+ IX86_BUILTIN_PAVGW512,
+ IX86_BUILTIN_PADDB512,
+ IX86_BUILTIN_PSUBB512,
+ IX86_BUILTIN_PSUBSB512,
+ IX86_BUILTIN_PADDSB512,
+ IX86_BUILTIN_PSUBUSB512,
+ IX86_BUILTIN_PADDUSB512,
+ IX86_BUILTIN_PSUBW512,
+ IX86_BUILTIN_PADDW512,
+ IX86_BUILTIN_PSUBSW512,
+ IX86_BUILTIN_PADDSW512,
+ IX86_BUILTIN_PSUBUSW512,
+ IX86_BUILTIN_PADDUSW512,
+ IX86_BUILTIN_PMAXUW512,
+ IX86_BUILTIN_PMAXSW512,
+ IX86_BUILTIN_PMINUW512,
+ IX86_BUILTIN_PMINSW512,
+ IX86_BUILTIN_PMAXUB512,
+ IX86_BUILTIN_PMAXSB512,
+ IX86_BUILTIN_PMINUB512,
+ IX86_BUILTIN_PMINSB512,
+ IX86_BUILTIN_PMOVWB512,
+ IX86_BUILTIN_PMOVSWB512,
+ IX86_BUILTIN_PMOVUSWB512,
+ IX86_BUILTIN_PMULHRSW512_MASK,
+ IX86_BUILTIN_PMULHUW512_MASK,
+ IX86_BUILTIN_PMULHW512_MASK,
+ IX86_BUILTIN_PMULLW512_MASK,
+ IX86_BUILTIN_PSLLWI512_MASK,
+ IX86_BUILTIN_PSLLW512_MASK,
+ IX86_BUILTIN_PACKSSWB512,
+ IX86_BUILTIN_PACKUSWB512,
+ IX86_BUILTIN_PSRAVV32HI,
+ IX86_BUILTIN_PMADDUBSW512_MASK,
+ IX86_BUILTIN_PMADDWD512_MASK,
+ IX86_BUILTIN_PSRLVV32HI,
+ IX86_BUILTIN_PUNPCKHBW512,
+ IX86_BUILTIN_PUNPCKHWD512,
+ IX86_BUILTIN_PUNPCKLBW512,
+ IX86_BUILTIN_PUNPCKLWD512,
+ IX86_BUILTIN_PSHUFB512,
+ IX86_BUILTIN_PSHUFHW512,
+ IX86_BUILTIN_PSHUFLW512,
+ IX86_BUILTIN_PSRAWI512,
+ IX86_BUILTIN_PSRAW512,
+ IX86_BUILTIN_PSRLWI512,
+ IX86_BUILTIN_PSRLW512,
+ IX86_BUILTIN_CVTB2MASK512,
+ IX86_BUILTIN_CVTW2MASK512,
+ IX86_BUILTIN_CVTMASK2B512,
+ IX86_BUILTIN_CVTMASK2W512,
+ IX86_BUILTIN_PCMPEQB512_MASK,
+ IX86_BUILTIN_PCMPEQW512_MASK,
+ IX86_BUILTIN_PCMPGTB512_MASK,
+ IX86_BUILTIN_PCMPGTW512_MASK,
+ IX86_BUILTIN_PTESTMB512,
+ IX86_BUILTIN_PTESTMW512,
+ IX86_BUILTIN_PTESTNMB512,
+ IX86_BUILTIN_PTESTNMW512,
+ IX86_BUILTIN_PSLLVV32HI,
+ IX86_BUILTIN_PABSB512,
+ IX86_BUILTIN_PABSW512,
+ IX86_BUILTIN_BLENDMW512,
+ IX86_BUILTIN_BLENDMB512,
+ IX86_BUILTIN_CMPB512,
+ IX86_BUILTIN_CMPW512,
+ IX86_BUILTIN_UCMPB512,
+ IX86_BUILTIN_UCMPW512,
+
/* Alternate 4 and 8 element gather/scatter for the vectorizer
where all operands are 32-byte or 64-byte wide respectively. */
IX86_BUILTIN_GATHERALTSIV4DF,
@@ -29330,6 +30319,108 @@ static const struct builtin_description bdesc_special_args[] =
{ OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
{ OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
{ OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
+
+ /* AVX512BW */
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
+
+ /* AVX512VL */
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
};
/* Builtins with variable number of arguments. */
@@ -30389,6 +31480,848 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
+
+ /* AVX512VL. */
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv4di_mask, "__builtin_ia32_pbroadcastq256_mem_mask", IX86_BUILTIN_PBROADCASTQ256_MEM_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv2di_mask, "__builtin_ia32_pbroadcastq128_mem_mask", IX86_BUILTIN_PBROADCASTQ128_MEM_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
+
+ /* AVX512DQ. */
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
+
+ /* AVX512BW. */
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
};
/* Builtins with rounding support. */
@@ -30526,6 +32459,24 @@ static const struct builtin_description bdesc_round_args[] =
{ OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
{ OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
{ OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
+
+ /* AVX512DQ. */
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
};
/* FMA4 and XOP. */
@@ -33803,6 +35754,28 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V4DI_FTYPE_V4SI:
case V4DI_FTYPE_V2DI:
case HI_FTYPE_HI:
+ case HI_FTYPE_V16QI:
+ case SI_FTYPE_V32QI:
+ case DI_FTYPE_V64QI:
+ case V16QI_FTYPE_HI:
+ case V32QI_FTYPE_SI:
+ case V64QI_FTYPE_DI:
+ case V8HI_FTYPE_QI:
+ case V16HI_FTYPE_HI:
+ case V32HI_FTYPE_SI:
+ case V4SI_FTYPE_QI:
+ case V8SI_FTYPE_QI:
+ case V4SI_FTYPE_HI:
+ case V8SI_FTYPE_HI:
+ case QI_FTYPE_V8HI:
+ case HI_FTYPE_V16HI:
+ case SI_FTYPE_V32HI:
+ case QI_FTYPE_V4SI:
+ case QI_FTYPE_V8SI:
+ case HI_FTYPE_V16SI:
+ case QI_FTYPE_V2DI:
+ case QI_FTYPE_V4DI:
+ case QI_FTYPE_V8DI:
case UINT_FTYPE_V2DF:
case UINT_FTYPE_V4SF:
case UINT64_FTYPE_V2DF:
@@ -33810,6 +35783,8 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V16QI_FTYPE_V8DI:
case V16HI_FTYPE_V16SI:
case V16SI_FTYPE_HI:
+ case V2DI_FTYPE_QI:
+ case V4DI_FTYPE_QI:
case V16SI_FTYPE_V16SI:
case V16SI_FTYPE_INT:
case V16SF_FTYPE_FLOAT:
@@ -33821,7 +35796,6 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V8HI_FTYPE_V8DI:
case V8UHI_FTYPE_V8UHI:
case V8SI_FTYPE_V8DI:
- case V8USI_FTYPE_V8USI:
case V8SF_FTYPE_V8DF:
case V8DI_FTYPE_QI:
case V8DI_FTYPE_INT64:
@@ -33902,6 +35876,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V4DI_FTYPE_V8SI_V8SI:
case V4UDI_FTYPE_V8USI_V8USI:
case QI_FTYPE_V8DI_V8DI:
+ case V8DI_FTYPE_V64QI_V64QI:
case HI_FTYPE_V16SI_V16SI:
if (comparison == UNKNOWN)
return ix86_expand_binop_builtin (icode, exp, target);
@@ -33941,6 +35916,8 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case UINT16_FTYPE_UINT16_INT:
case UINT8_FTYPE_UINT8_INT:
case HI_FTYPE_HI_HI:
+ case SI_FTYPE_SI_SI:
+ case DI_FTYPE_DI_DI:
case V16SI_FTYPE_V8DF_V8DF:
nargs = 2;
break;
@@ -33954,6 +35931,11 @@ ix86_expand_args_builtin (const struct builtin_description *d,
rmode = V2TImode;
nargs_constant = 1;
break;
+ case V8DI_FTYPE_V8DI_INT_CONVERT:
+ nargs = 2;
+ rmode = V4TImode;
+ nargs_constant = 1;
+ break;
case V8HI_FTYPE_V8HI_INT:
case V8HI_FTYPE_V8SF_INT:
case V16HI_FTYPE_V16SF_INT:
@@ -33979,6 +35961,8 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V2DI_FTYPE_V4DI_INT:
case V4DI_FTYPE_V8DI_INT:
case HI_FTYPE_HI_INT:
+ case QI_FTYPE_V4SF_INT:
+ case QI_FTYPE_V2DF_INT:
nargs = 2;
nargs_constant = 1;
break;
@@ -34003,20 +35987,118 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V16SI_FTYPE_V16HI_V16SI_HI:
case V16SI_FTYPE_V16QI_V16SI_HI:
case V16SI_FTYPE_V16SF_V16SI_HI:
+ case V8SF_FTYPE_V4SF_V8SF_QI:
+ case V4DF_FTYPE_V2DF_V4DF_QI:
+ case V8SI_FTYPE_V4SI_V8SI_QI:
+ case V8SI_FTYPE_SI_V8SI_QI:
+ case V4SI_FTYPE_V4SI_V4SI_QI:
+ case V4SI_FTYPE_SI_V4SI_QI:
+ case V4DI_FTYPE_V2DI_V4DI_QI:
+ case V4DI_FTYPE_DI_V4DI_QI:
+ case V2DI_FTYPE_V2DI_V2DI_QI:
+ case V2DI_FTYPE_DI_V2DI_QI:
+ case V64QI_FTYPE_V64QI_V64QI_DI:
+ case V64QI_FTYPE_V16QI_V64QI_DI:
+ case V64QI_FTYPE_QI_V64QI_DI:
+ case V32QI_FTYPE_V32QI_V32QI_SI:
+ case V32QI_FTYPE_V16QI_V32QI_SI:
+ case V32QI_FTYPE_QI_V32QI_SI:
+ case V16QI_FTYPE_V16QI_V16QI_HI:
+ case V16QI_FTYPE_QI_V16QI_HI:
+ case V32HI_FTYPE_V8HI_V32HI_SI:
+ case V32HI_FTYPE_HI_V32HI_SI:
+ case V16HI_FTYPE_V8HI_V16HI_HI:
+ case V16HI_FTYPE_HI_V16HI_HI:
+ case V8HI_FTYPE_V8HI_V8HI_QI:
+ case V8HI_FTYPE_HI_V8HI_QI:
+ case V8SF_FTYPE_V8HI_V8SF_QI:
+ case V4SF_FTYPE_V8HI_V4SF_QI:
+ case V8SI_FTYPE_V8SF_V8SI_QI:
+ case V4SI_FTYPE_V4SF_V4SI_QI:
+ case V8DI_FTYPE_V8SF_V8DI_QI:
+ case V4DI_FTYPE_V4SF_V4DI_QI:
+ case V2DI_FTYPE_V4SF_V2DI_QI:
+ case V8SF_FTYPE_V8DI_V8SF_QI:
+ case V4SF_FTYPE_V4DI_V4SF_QI:
+ case V4SF_FTYPE_V2DI_V4SF_QI:
+ case V8DF_FTYPE_V8DI_V8DF_QI:
+ case V4DF_FTYPE_V4DI_V4DF_QI:
+ case V2DF_FTYPE_V2DI_V2DF_QI:
+ case V16QI_FTYPE_V8HI_V16QI_QI:
+ case V16QI_FTYPE_V16HI_V16QI_HI:
+ case V16QI_FTYPE_V4SI_V16QI_QI:
+ case V16QI_FTYPE_V8SI_V16QI_QI:
+ case V8HI_FTYPE_V4SI_V8HI_QI:
+ case V8HI_FTYPE_V8SI_V8HI_QI:
+ case V16QI_FTYPE_V2DI_V16QI_QI:
+ case V16QI_FTYPE_V4DI_V16QI_QI:
+ case V8HI_FTYPE_V2DI_V8HI_QI:
+ case V8HI_FTYPE_V4DI_V8HI_QI:
+ case V4SI_FTYPE_V2DI_V4SI_QI:
+ case V4SI_FTYPE_V4DI_V4SI_QI:
+ case V32QI_FTYPE_V32HI_V32QI_SI:
+ case HI_FTYPE_V16QI_V16QI_HI:
+ case SI_FTYPE_V32QI_V32QI_SI:
+ case DI_FTYPE_V64QI_V64QI_DI:
+ case QI_FTYPE_V8HI_V8HI_QI:
+ case HI_FTYPE_V16HI_V16HI_HI:
+ case SI_FTYPE_V32HI_V32HI_SI:
+ case QI_FTYPE_V4SI_V4SI_QI:
+ case QI_FTYPE_V8SI_V8SI_QI:
+ case QI_FTYPE_V2DI_V2DI_QI:
+ case QI_FTYPE_V4DI_V4DI_QI:
+ case V4SF_FTYPE_V2DF_V4SF_QI:
+ case V4SF_FTYPE_V4DF_V4SF_QI:
+ nargs = 3;
case V16SI_FTYPE_V16SI_V16SI_HI:
case V16SI_FTYPE_V16SI_V16SI_V16SI:
case V16SI_FTYPE_V4SI_V16SI_HI:
case V2DI_FTYPE_V2DI_V2DI_V2DI:
+ case V2DI_FTYPE_V4SI_V2DI_QI:
+ case V2DI_FTYPE_V8HI_V2DI_QI:
+ case V2DI_FTYPE_V16QI_V2DI_QI:
+ case V4DI_FTYPE_V4DI_V4DI_QI:
+ case V4DI_FTYPE_V4SI_V4DI_QI:
+ case V4DI_FTYPE_V8HI_V4DI_QI:
+ case V4DI_FTYPE_V16QI_V4DI_QI:
+ case V8DI_FTYPE_V8DF_V8DI_QI:
+ case V4DI_FTYPE_V4DF_V4DI_QI:
+ case V2DI_FTYPE_V2DF_V2DI_QI:
+ case V4SI_FTYPE_V4DF_V4SI_QI:
+ case V4SI_FTYPE_V2DF_V4SI_QI:
+ case V4SI_FTYPE_V8HI_V4SI_QI:
+ case V4SI_FTYPE_V16QI_V4SI_QI:
+ case V8SI_FTYPE_V8SI_V8SI_V8SI:
case V4DI_FTYPE_V4DI_V4DI_V4DI:
case V8DF_FTYPE_V2DF_V8DF_QI:
case V8DF_FTYPE_V4DF_V8DF_QI:
case V8DF_FTYPE_V8DF_V8DF_QI:
case V8DF_FTYPE_V8DF_V8DF_V8DF:
+ case V8SF_FTYPE_V8SF_V8SF_QI:
+ case V8SF_FTYPE_V8SI_V8SF_QI:
+ case V4DF_FTYPE_V4DF_V4DF_QI:
+ case V4SF_FTYPE_V4SF_V4SF_QI:
+ case V2DF_FTYPE_V2DF_V2DF_QI:
+ case V2DF_FTYPE_V4SF_V2DF_QI:
+ case V2DF_FTYPE_V4SI_V2DF_QI:
+ case V4SF_FTYPE_V4SI_V4SF_QI:
+ case V4DF_FTYPE_V4SF_V4DF_QI:
+ case V4DF_FTYPE_V4SI_V4DF_QI:
+ case V8SI_FTYPE_V8SI_V8SI_QI:
+ case V8SI_FTYPE_V8HI_V8SI_QI:
+ case V8SI_FTYPE_V16QI_V8SI_QI:
case V8DF_FTYPE_V8DF_V8DI_V8DF:
case V8DF_FTYPE_V8DI_V8DF_V8DF:
case V8DF_FTYPE_V8SF_V8DF_QI:
case V8DF_FTYPE_V8SI_V8DF_QI:
case V8DI_FTYPE_DI_V8DI_QI:
+ case V16SF_FTYPE_V8SF_V16SF_HI:
+ case V16SI_FTYPE_V8SI_V16SI_HI:
+ case V16HI_FTYPE_V16HI_V16HI_HI:
+ case V8HI_FTYPE_V16QI_V8HI_QI:
+ case V16HI_FTYPE_V16QI_V16HI_HI:
+ case V32HI_FTYPE_V32HI_V32HI_SI:
+ case V32HI_FTYPE_V32QI_V32HI_SI:
case V8DI_FTYPE_V16QI_V8DI_QI:
case V8DI_FTYPE_V2DI_V8DI_QI:
case V8DI_FTYPE_V4DI_V8DI_QI:
@@ -34078,13 +36160,80 @@ ix86_expand_args_builtin (const struct builtin_description *d,
nargs = 3;
nargs_constant = 2;
break;
+ case V8DI_FTYPE_V8DI_V8DI_INT_CONVERT:
+ nargs = 3;
+ rmode = V8DImode;
+ nargs_constant = 1;
+ break;
+ case V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT:
+ nargs = 5;
+ rmode = V8DImode;
+ mask_pos = 2;
+ nargs_constant = 1;
+ break;
+ case QI_FTYPE_V8DF_INT_QI:
+ case QI_FTYPE_V4DF_INT_QI:
+ case QI_FTYPE_V2DF_INT_QI:
+ case HI_FTYPE_V16SF_INT_HI:
+ case QI_FTYPE_V8SF_INT_QI:
+ case QI_FTYPE_V4SF_INT_QI:
+ nargs = 3;
+ mask_pos = 1;
+ nargs_constant = 1;
+ break;
+ case V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT:
+ nargs = 5;
+ rmode = V4DImode;
+ mask_pos = 2;
+ nargs_constant = 1;
+ break;
+ case V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT:
+ nargs = 5;
+ rmode = V2DImode;
+ mask_pos = 2;
+ nargs_constant = 1;
+ break;
+ case V32QI_FTYPE_V32QI_V32QI_V32QI_SI:
+ case V32HI_FTYPE_V32HI_V32HI_V32HI_SI:
+ case V32HI_FTYPE_V64QI_V64QI_V32HI_SI:
+ case V16SI_FTYPE_V32HI_V32HI_V16SI_HI:
+ case V64QI_FTYPE_V64QI_V64QI_V64QI_DI:
+ case V32HI_FTYPE_V32HI_V8HI_V32HI_SI:
+ case V16HI_FTYPE_V16HI_V8HI_V16HI_HI:
+ case V8SI_FTYPE_V8SI_V4SI_V8SI_QI:
+ case V4DI_FTYPE_V4DI_V2DI_V4DI_QI:
+ case V64QI_FTYPE_V32HI_V32HI_V64QI_DI:
+ case V32QI_FTYPE_V16HI_V16HI_V32QI_SI:
+ case V16QI_FTYPE_V8HI_V8HI_V16QI_HI:
+ case V32HI_FTYPE_V16SI_V16SI_V32HI_SI:
+ case V16HI_FTYPE_V8SI_V8SI_V16HI_HI:
+ case V8HI_FTYPE_V4SI_V4SI_V8HI_QI:
+ case V4DF_FTYPE_V4DF_V4DI_V4DF_QI:
+ case V8SF_FTYPE_V8SF_V8SI_V8SF_QI:
+ case V4SF_FTYPE_V4SF_V4SI_V4SF_QI:
+ case V2DF_FTYPE_V2DF_V2DI_V2DF_QI:
+ case V2DI_FTYPE_V4SI_V4SI_V2DI_QI:
+ case V4DI_FTYPE_V8SI_V8SI_V4DI_QI:
+ case V4DF_FTYPE_V4DI_V4DF_V4DF_QI:
+ case V8SF_FTYPE_V8SI_V8SF_V8SF_QI:
+ case V2DF_FTYPE_V2DI_V2DF_V2DF_QI:
+ case V4SF_FTYPE_V4SI_V4SF_V4SF_QI:
case V16SF_FTYPE_V16SF_V16SF_V16SF_HI:
case V16SF_FTYPE_V16SF_V16SI_V16SF_HI:
case V16SF_FTYPE_V16SI_V16SF_V16SF_HI:
case V16SI_FTYPE_V16SI_V16SI_V16SI_HI:
case V16SI_FTYPE_V16SI_V4SI_V16SI_HI:
+ case V8HI_FTYPE_V8HI_V8HI_V8HI_QI:
+ case V8SI_FTYPE_V8SI_V8SI_V8SI_QI:
+ case V4SI_FTYPE_V4SI_V4SI_V4SI_QI:
+ case V8SF_FTYPE_V8SF_V8SF_V8SF_QI:
+ case V16QI_FTYPE_V16QI_V16QI_V16QI_HI:
+ case V16HI_FTYPE_V16HI_V16HI_V16HI_HI:
+ case V2DI_FTYPE_V2DI_V2DI_V2DI_QI:
case V2DF_FTYPE_V2DF_V2DF_V2DF_QI:
case V2DF_FTYPE_V2DF_V4SF_V2DF_QI:
+ case V4DI_FTYPE_V4DI_V4DI_V4DI_QI:
+ case V4DF_FTYPE_V4DF_V4DF_V4DF_QI:
case V4SF_FTYPE_V4SF_V2DF_V4SF_QI:
case V4SF_FTYPE_V4SF_V4SF_V4SF_QI:
case V8DF_FTYPE_V8DF_V8DF_V8DF_QI:
@@ -34094,6 +36243,10 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V8DI_FTYPE_V8DI_SI_V8DI_V8DI:
case V8DI_FTYPE_V8DI_V2DI_V8DI_QI:
case V8DI_FTYPE_V8DI_V8DI_V8DI_QI:
+ case V8HI_FTYPE_V16QI_V16QI_V8HI_QI:
+ case V16HI_FTYPE_V32QI_V32QI_V16HI_HI:
+ case V8SI_FTYPE_V16HI_V16HI_V8SI_QI:
+ case V4SI_FTYPE_V8HI_V8HI_V4SI_QI:
nargs = 4;
break;
case V2DF_FTYPE_V2DF_V2DF_V2DI_INT:
@@ -34104,8 +36257,20 @@ ix86_expand_args_builtin (const struct builtin_description *d,
nargs = 4;
nargs_constant = 1;
break;
+ case QI_FTYPE_V4DI_V4DI_INT_QI:
+ case QI_FTYPE_V8SI_V8SI_INT_QI:
+ case QI_FTYPE_V4DF_V4DF_INT_QI:
+ case QI_FTYPE_V8SF_V8SF_INT_QI:
+ case QI_FTYPE_V2DI_V2DI_INT_QI:
+ case QI_FTYPE_V4SI_V4SI_INT_QI:
case QI_FTYPE_V2DF_V2DF_INT_QI:
case QI_FTYPE_V4SF_V4SF_INT_QI:
+ case DI_FTYPE_V64QI_V64QI_INT_DI:
+ case SI_FTYPE_V32QI_V32QI_INT_SI:
+ case HI_FTYPE_V16QI_V16QI_INT_HI:
+ case SI_FTYPE_V32HI_V32HI_INT_SI:
+ case HI_FTYPE_V16HI_V16HI_INT_HI:
+ case QI_FTYPE_V8HI_V8HI_INT_QI:
nargs = 4;
mask_pos = 1;
nargs_constant = 1;
@@ -34126,6 +36291,27 @@ ix86_expand_args_builtin (const struct builtin_description *d,
nargs = 4;
nargs_constant = 1;
break;
+ case V8SF_FTYPE_V8SF_INT_V8SF_QI:
+ case V4SF_FTYPE_V4SF_INT_V4SF_QI:
+ case V2DF_FTYPE_V4DF_INT_V2DF_QI:
+ case V2DI_FTYPE_V4DI_INT_V2DI_QI:
+ case V8SF_FTYPE_V16SF_INT_V8SF_QI:
+ case V8SI_FTYPE_V16SI_INT_V8SI_QI:
+ case V2DF_FTYPE_V8DF_INT_V2DF_QI:
+ case V2DI_FTYPE_V8DI_INT_V2DI_QI:
+ case V4SF_FTYPE_V8SF_INT_V4SF_QI:
+ case V4SI_FTYPE_V8SI_INT_V4SI_QI:
+ case V8HI_FTYPE_V8SF_INT_V8HI_QI:
+ case V8HI_FTYPE_V4SF_INT_V8HI_QI:
+ case V32HI_FTYPE_V32HI_INT_V32HI_SI:
+ case V16HI_FTYPE_V16HI_INT_V16HI_HI:
+ case V8HI_FTYPE_V8HI_INT_V8HI_QI:
+ case V4DI_FTYPE_V4DI_INT_V4DI_QI:
+ case V2DI_FTYPE_V2DI_INT_V2DI_QI:
+ case V8SI_FTYPE_V8SI_INT_V8SI_QI:
+ case V4SI_FTYPE_V4SI_INT_V4SI_QI:
+ case V4DF_FTYPE_V4DF_INT_V4DF_QI:
+ case V2DF_FTYPE_V2DF_INT_V2DF_QI:
case V8DF_FTYPE_V8DF_INT_V8DF_QI:
case V16SF_FTYPE_V16SF_INT_V16SF_HI:
case V16HI_FTYPE_V16SF_INT_V16HI_HI:
@@ -34149,6 +36335,23 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI:
case V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI:
case V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI:
+ case V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI:
+ case V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI:
+ case V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI:
+ case V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI:
+ case V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI:
+ case V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI:
+ case V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI:
+ case V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI:
+ case V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI:
+ case V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI:
+ case V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI:
+ case V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI:
+ case V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI:
+ case V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI:
+ case V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI:
+ case V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI:
+ case V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI:
nargs = 5;
mask_pos = 2;
nargs_constant = 1;
@@ -34158,6 +36361,13 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI:
case V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI:
case V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI:
+ case V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI:
+ case V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI:
+ case V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI:
+ case V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI:
+ case V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI:
+ case V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI:
+ nargs = 5;
nargs = 5;
mask_pos = 1;
nargs_constant = 1;
@@ -34606,7 +36816,11 @@ ix86_expand_round_builtin (const struct builtin_description *d,
case V8SF_FTYPE_V8DF_V8SF_QI_INT:
case V8DF_FTYPE_V8DF_V8DF_QI_INT:
case V8SI_FTYPE_V8DF_V8SI_QI_INT:
+ case V8DI_FTYPE_V8DF_V8DI_QI_INT:
+ case V8SF_FTYPE_V8DI_V8SF_QI_INT:
+ case V8DF_FTYPE_V8DI_V8DF_QI_INT:
case V16SF_FTYPE_V16SF_V16SF_HI_INT:
+ case V8DI_FTYPE_V8SF_V8DI_QI_INT:
case V16SF_FTYPE_V16SI_V16SF_HI_INT:
case V16SI_FTYPE_V16SF_V16SI_HI_INT:
case V8DF_FTYPE_V8SF_V8DF_QI_INT:
@@ -34643,6 +36857,8 @@ ix86_expand_round_builtin (const struct builtin_description *d,
nargs_constant = 3;
nargs = 5;
break;
+ case V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT:
+ case V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT:
case V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI_INT:
case V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI_INT:
nargs = 6;
@@ -34905,7 +37121,11 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
case VOID_FTYPE_PV8DF_V8DF_QI:
case VOID_FTYPE_PV16SF_V16SF_HI:
case VOID_FTYPE_PV8DI_V8DI_QI:
+ case VOID_FTYPE_PV4DI_V4DI_QI:
+ case VOID_FTYPE_PV2DI_V2DI_QI:
case VOID_FTYPE_PV16SI_V16SI_HI:
+ case VOID_FTYPE_PV8SI_V8SI_QI:
+ case VOID_FTYPE_PV4SI_V4SI_QI:
switch (icode)
{
/* These builtins and instructions require the memory
@@ -34943,17 +37163,51 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
case VOID_FTYPE_PV16HI_V16SI_HI:
case VOID_FTYPE_PV16QI_V8DI_QI:
case VOID_FTYPE_PV16QI_V16SI_HI:
+ case VOID_FTYPE_PV4SI_V4DI_QI:
+ case VOID_FTYPE_PV4SI_V2DI_QI:
+ case VOID_FTYPE_PV8HI_V4DI_QI:
+ case VOID_FTYPE_PV8HI_V2DI_QI:
+ case VOID_FTYPE_PV8HI_V8SI_QI:
+ case VOID_FTYPE_PV8HI_V4SI_QI:
+ case VOID_FTYPE_PV16QI_V4DI_QI:
+ case VOID_FTYPE_PV16QI_V2DI_QI:
+ case VOID_FTYPE_PV16QI_V8SI_QI:
+ case VOID_FTYPE_PV16QI_V4SI_QI:
+ case VOID_FTYPE_PV8HI_V8HI_QI:
+ case VOID_FTYPE_PV16HI_V16HI_HI:
+ case VOID_FTYPE_PV32HI_V32HI_SI:
+ case VOID_FTYPE_PV16QI_V16QI_HI:
+ case VOID_FTYPE_PV32QI_V32QI_SI:
+ case VOID_FTYPE_PV64QI_V64QI_DI:
+ case VOID_FTYPE_PV4DF_V4DF_QI:
+ case VOID_FTYPE_PV2DF_V2DF_QI:
+ case VOID_FTYPE_PV8SF_V8SF_QI:
+ case VOID_FTYPE_PV4SF_V4SF_QI:
nargs = 2;
klass = store;
/* Reserve memory operand for target. */
memory = ARRAY_SIZE (args);
break;
+ case V4SF_FTYPE_PCV4SF_V4SF_QI:
+ case V8SF_FTYPE_PCV8SF_V8SF_QI:
case V16SF_FTYPE_PCV16SF_V16SF_HI:
+ case V4SI_FTYPE_PCV4SI_V4SI_QI:
+ case V8SI_FTYPE_PCV8SI_V8SI_QI:
case V16SI_FTYPE_PCV16SI_V16SI_HI:
+ case V2DF_FTYPE_PCV2DF_V2DF_QI:
+ case V4DF_FTYPE_PCV4DF_V4DF_QI:
case V8DF_FTYPE_PCV8DF_V8DF_QI:
+ case V2DI_FTYPE_PCV2DI_V2DI_QI:
+ case V4DI_FTYPE_PCV4DI_V4DI_QI:
case V8DI_FTYPE_PCV8DI_V8DI_QI:
case V2DF_FTYPE_PCDOUBLE_V2DF_QI:
case V4SF_FTYPE_PCFLOAT_V4SF_QI:
+ case V8HI_FTYPE_PCV8HI_V8HI_QI:
+ case V16HI_FTYPE_PCV16HI_V16HI_HI:
+ case V32HI_FTYPE_PCV32HI_V32HI_SI:
+ case V16QI_FTYPE_PCV16QI_V16QI_HI:
+ case V32QI_FTYPE_PCV32QI_V32QI_SI:
+ case V64QI_FTYPE_PCV64QI_V64QI_DI:
nargs = 3;
klass = load;
memory = 0;
diff --git a/gcc/tree-core.h b/gcc/tree-core.h
index b69312b..c9c248e 100644
--- a/gcc/tree-core.h
+++ b/gcc/tree-core.h
@@ -1498,7 +1498,9 @@ struct GTY(()) tree_decl_with_vis {
unsigned cxx_destructor : 1;
/* Belong to FUNCTION_DECL exclusively. */
unsigned final : 1;
- /* 15 unused bits. */
+ /* Belong to FUNCTION_DECL exclusively. */
+ unsigned regdecl_flag : 1;
+ /* 14 unused bits. */
};
struct GTY(()) tree_var_decl {
@@ -1539,7 +1541,7 @@ struct GTY(()) tree_function_decl {
DECL_FUNCTION_CODE. Otherwise unused.
??? The bitfield needs to be able to hold all target function
codes as well. */
- ENUM_BITFIELD(built_in_function) function_code : 11;
+ ENUM_BITFIELD(built_in_function) function_code : 12;
ENUM_BITFIELD(built_in_class) built_in_class : 2;
unsigned static_ctor_flag : 1;
@@ -1552,7 +1554,6 @@ struct GTY(()) tree_function_decl {
unsigned malloc_flag : 1;
unsigned operator_new_flag : 1;
unsigned declared_inline_flag : 1;
- unsigned regdecl_flag : 1;
unsigned no_inline_warning_flag : 1;
unsigned no_instrument_function_entry_exit : 1;
diff --git a/gcc/tree.h b/gcc/tree.h
index 45f127f..5ba6e0f 100644
--- a/gcc/tree.h
+++ b/gcc/tree.h
@@ -2334,6 +2334,10 @@ extern void decl_value_expr_insert (tree, tree);
#define DECL_COMDAT(NODE) \
(DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.comdat_flag)
+ /* In a FUNCTION_DECL indicates that a static chain is needed. */
+#define DECL_STATIC_CHAIN(NODE) \
+ (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.regdecl_flag)
+
#define DECL_COMDAT_GROUP(NODE) \
decl_comdat_group (NODE)
@@ -2551,10 +2555,6 @@ extern void decl_fini_priority_insert (tree, priority_type);
#define DECL_NO_LIMIT_STACK(NODE) \
(FUNCTION_DECL_CHECK (NODE)->function_decl.no_limit_stack)
-/* In a FUNCTION_DECL indicates that a static chain is needed. */
-#define DECL_STATIC_CHAIN(NODE) \
- (FUNCTION_DECL_CHECK (NODE)->function_decl.regdecl_flag)
-
/* Nonzero for a decl that cgraph has decided should be inlined into
at least one call site. It is not meaningful to look at this
directly; always use cgraph_function_possibly_inlined_p. */
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH i386 AVX512] [81/n] Add new built-ins.
2014-10-21 9:19 ` Richard Biener
@ 2014-10-21 14:19 ` Kirill Yukhin
0 siblings, 0 replies; 16+ messages in thread
From: Kirill Yukhin @ 2014-10-21 14:19 UTC (permalink / raw)
To: Richard Biener; +Cc: Jakub Jelinek, Uros Bizjak, Richard Henderson, GCC Patches
Hello,
On 21 Oct 11:17, Richard Biener wrote:
> On Mon, Oct 20, 2014 at 3:50 PM, Jakub Jelinek <jakub@redhat.com> wrote:
> > On Mon, Oct 20, 2014 at 05:41:25PM +0400, Kirill Yukhin wrote:
> >> Hello,
> >> This patch adds (almost) all built-ins needed by
> >> AVX-512VL,BW,DQ intrinsics.
> >>
> >> Main questionable hunk is:
> >>
> >> diff --git a/gcc/tree-core.h b/gcc/tree-core.h
> >> index b69312b..a639487 100644
> >> --- a/gcc/tree-core.h
> >> +++ b/gcc/tree-core.h
> >> @@ -1539,7 +1539,7 @@ struct GTY(()) tree_function_decl {
> >> DECL_FUNCTION_CODE. Otherwise unused.
> >> ??? The bitfield needs to be able to hold all target function
> >> codes as well. */
> >> - ENUM_BITFIELD(built_in_function) function_code : 11;
> >> + ENUM_BITFIELD(built_in_function) function_code : 12;
> >> ENUM_BITFIELD(built_in_class) built_in_class : 2;
> >>
> >> unsigned static_ctor_flag : 1;
> >
> > Well, decl_with_vis has 15 unused bits, so instead of growing
> > FUNCTION_DECL significantly, might be better to move one of the
> > flags to decl_with_vis and just document that it applies to FUNCTION_DECLs
> > only. Or move some flag to cgraph if possible.
> >
> > But seeing e.g.
> > IX86_BUILTIN_FIXUPIMMPD256, IX86_BUILTIN_FIXUPIMMPD256_MASK,
> > IX86_BUILTIN_FIXUPIMMPD256_MASKZ
> > etc. I wonder if you really need that many builtins, weren't we adding
> > for avx512f just single builtin instead of 3 different ones, always
> > providing mask argument and depending on whether it is all ones, etc.
> > figuring out what kind of masking should be performed?
>
> If only we had no lang-specific flags in tree_base we could use
> the same place as we use for internal function code ...
>
> But yes, not using that many builtins in the first place is preferred
> for example by making them type-generic and/or variadic.
We might try to refactor x86 built-ins toward type-generic approach, but
I think it can be postponed to 6.x release series.
--
Thanks, K
>
> Richard.
>
> > Jakub
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH i386 AVX512] [81/n] Add new built-ins.
2014-10-21 14:09 ` Kirill Yukhin
@ 2014-10-21 14:21 ` Jakub Jelinek
2014-10-21 14:52 ` Kirill Yukhin
2014-10-22 7:57 ` [PATCH AVX512] [81.1/n] Extend `function_code' field in `tree_var_decl' structure Kirill Yukhin
2014-10-21 14:24 ` [PATCH i386 AVX512] [81/n] Add new built-ins Richard Biener
1 sibling, 2 replies; 16+ messages in thread
From: Jakub Jelinek @ 2014-10-21 14:21 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Uros Bizjak, Richard Henderson, GCC Patches
On Tue, Oct 21, 2014 at 06:08:15PM +0400, Kirill Yukhin wrote:
> --- a/gcc/tree.h
> +++ b/gcc/tree.h
> @@ -2334,6 +2334,10 @@ extern void decl_value_expr_insert (tree, tree);
> #define DECL_COMDAT(NODE) \
> (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.comdat_flag)
>
> + /* In a FUNCTION_DECL indicates that a static chain is needed. */
> +#define DECL_STATIC_CHAIN(NODE) \
> + (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.regdecl_flag)
> +
I would say that you should still keep it together with the FUNCTION_DECL
macros and use FUNCTION_DECL_CHECK there, to make it clear we don't want
the macro to be used on VAR_DECLs etc.
So just s/function_decl/decl_with_vis/ in the definition IMHO.
Also, with so many added builtins, how does it affect
int i;
compilation time at -O0? If it is significant, maybe it is highest time to
make the md builtin decl building more lazy.
Jakub
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH i386 AVX512] [81/n] Add new built-ins.
2014-10-21 14:09 ` Kirill Yukhin
2014-10-21 14:21 ` Jakub Jelinek
@ 2014-10-21 14:24 ` Richard Biener
1 sibling, 0 replies; 16+ messages in thread
From: Richard Biener @ 2014-10-21 14:24 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Jakub Jelinek, Uros Bizjak, Richard Henderson, GCC Patches
On Tue, Oct 21, 2014 at 4:08 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Hello,
> On 20 Oct 15:50, Jakub Jelinek wrote:
>> On Mon, Oct 20, 2014 at 05:41:25PM +0400, Kirill Yukhin wrote:
>> > Hello,
>> > This patch adds (almost) all built-ins needed by
>> > AVX-512VL,BW,DQ intrinsics.
>> >
>> > Main questionable hunk is:
>> >
>> > diff --git a/gcc/tree-core.h b/gcc/tree-core.h
>> > index b69312b..a639487 100644
>> > --- a/gcc/tree-core.h
>> > +++ b/gcc/tree-core.h
>> > @@ -1539,7 +1539,7 @@ struct GTY(()) tree_function_decl {
>> > DECL_FUNCTION_CODE. Otherwise unused.
>> > ??? The bitfield needs to be able to hold all target function
>> > codes as well. */
>> > - ENUM_BITFIELD(built_in_function) function_code : 11;
>> > + ENUM_BITFIELD(built_in_function) function_code : 12;
>> > ENUM_BITFIELD(built_in_class) built_in_class : 2;
>> >
>> > unsigned static_ctor_flag : 1;
>>
>> Well, decl_with_vis has 15 unused bits, so instead of growing
>> FUNCTION_DECL significantly, might be better to move one of the
>> flags to decl_with_vis and just document that it applies to FUNCTION_DECLs
>> only. Or move some flag to cgraph if possible.
> That was exactly what I was thinking about. Updated patch in the
> bottom w/ moved `regdecl_flag' field.
>
>> But seeing e.g.
>> IX86_BUILTIN_FIXUPIMMPD256, IX86_BUILTIN_FIXUPIMMPD256_MASK,
>> IX86_BUILTIN_FIXUPIMMPD256_MASKZ
> FIXUPIMM w/o masking is really redundant. Fixed.
>
>> etc. I wonder if you really need that many builtins, weren't we adding
>> for avx512f just single builtin instead of 3 different ones, always
>> providing mask argument and depending on whether it is all ones, etc.
>> figuring out what kind of masking should be performed?
> In 3 operands insns w/
> destructive source we already have one operand w/ constraint `0'.
> As we don't support 2+ constraint `0' in single pattern, we have to
> use `match_dup' workaround, because of that we have two versions:
> one w/ `match_dup' for normal masking and one w/ constraint `0' for
> zero- and non-masking (generated by `subst'). Those two built-ins
> are for such cases.
> For non-destructive source we have one built-in.
>
> Is it ok for trunk (w/ appropriate ChangeLog change)?
Please keep the flags visually grouped in groups of 8.
Richard.
> Bootstrapped. Regtesting in progress.
>
> --
> Thanks, K
>
> AVX-512. 81/n. Add new builtins.
>
> diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def
> index 9161287..8315c5e 100644
> --- a/gcc/config/i386/i386-builtin-types.def
> +++ b/gcc/config/i386/i386-builtin-types.def
> @@ -56,6 +56,7 @@ DEF_PRIMITIVE_TYPE (UHI, unsigned_intHI_type_node)
> DEF_PRIMITIVE_TYPE (USI, unsigned_intSI_type_node)
> DEF_PRIMITIVE_TYPE (UDI, long_long_unsigned_type_node)
> # ??? Some of the types below should use the mode types above.
> +DEF_PRIMITIVE_TYPE (SHORT, short_integer_type_node)
> DEF_PRIMITIVE_TYPE (USHORT, short_unsigned_type_node)
> DEF_PRIMITIVE_TYPE (INT, integer_type_node)
> DEF_PRIMITIVE_TYPE (UINT, unsigned_type_node)
> @@ -107,7 +108,14 @@ DEF_VECTOR_TYPE (V16SF, FLOAT)
> DEF_VECTOR_TYPE (V8DF, DOUBLE)
> DEF_VECTOR_TYPE (V8DI, DI)
> DEF_VECTOR_TYPE (V16SI, SI)
> +DEF_VECTOR_TYPE (V32HI, HI)
> DEF_VECTOR_TYPE (V64QI, QI)
> +DEF_VECTOR_TYPE (V12QI, QI)
> +DEF_VECTOR_TYPE (V14QI, QI)
> +DEF_VECTOR_TYPE (V32SI, SI)
> +DEF_VECTOR_TYPE (V8UDI, UDI, V8DI)
> +DEF_VECTOR_TYPE (V16USI, USI, V16SI)
> +DEF_VECTOR_TYPE (V32UHI, UHI, V32HI)
>
> DEF_POINTER_TYPE (PCCHAR, CHAR, CONST)
> DEF_POINTER_TYPE (PCDOUBLE, DOUBLE, CONST)
> @@ -119,6 +127,7 @@ DEF_POINTER_TYPE (PCVOID, VOID, CONST)
> DEF_POINTER_TYPE (PVOID, VOID)
> DEF_POINTER_TYPE (PDOUBLE, DOUBLE)
> DEF_POINTER_TYPE (PFLOAT, FLOAT)
> +DEF_POINTER_TYPE (PSHORT, SHORT)
> DEF_POINTER_TYPE (PUSHORT, USHORT)
> DEF_POINTER_TYPE (PINT, INT)
> DEF_POINTER_TYPE (PLONGLONG, LONGLONG)
> @@ -142,6 +151,9 @@ DEF_POINTER_TYPE (PV16QI, V16QI)
> DEF_POINTER_TYPE (PV16HI, V16HI)
> DEF_POINTER_TYPE (PV16SI, V16SI)
> DEF_POINTER_TYPE (PV16SF, V16SF)
> +DEF_POINTER_TYPE (PV32QI, V32QI)
> +DEF_POINTER_TYPE (PV32HI, V32HI)
> +DEF_POINTER_TYPE (PV64QI, V64QI)
>
> DEF_POINTER_TYPE (PCV2SI, V2SI, CONST)
> DEF_POINTER_TYPE (PCV2DF, V2DF, CONST)
> @@ -155,9 +167,15 @@ DEF_POINTER_TYPE (PCV16SF, V16SF, CONST)
> DEF_POINTER_TYPE (PCV2DI, V2DI, CONST)
> DEF_POINTER_TYPE (PCV4SI, V4SI, CONST)
> DEF_POINTER_TYPE (PCV4DI, V4DI, CONST)
> +DEF_POINTER_TYPE (PCV8HI, V8HI, CONST)
> DEF_POINTER_TYPE (PCV8SI, V8SI, CONST)
> DEF_POINTER_TYPE (PCV8DI, V8DI, CONST)
> +DEF_POINTER_TYPE (PCV16QI, V16QI, CONST)
> +DEF_POINTER_TYPE (PCV16HI, V16HI, CONST)
> DEF_POINTER_TYPE (PCV16SI, V16SI, CONST)
> +DEF_POINTER_TYPE (PCV32QI, V32QI, CONST)
> +DEF_POINTER_TYPE (PCV32HI, V32HI, CONST)
> +DEF_POINTER_TYPE (PCV64QI, V64QI, CONST)
>
> DEF_FUNCTION_TYPE (FLOAT128)
> DEF_FUNCTION_TYPE (UINT64)
> @@ -217,12 +235,15 @@ DEF_FUNCTION_TYPE (V8DF, V8DF)
> DEF_FUNCTION_TYPE (V4HI, V4HI)
> DEF_FUNCTION_TYPE (V4SF, PCFLOAT)
> DEF_FUNCTION_TYPE (V4SF, V2DF)
> +DEF_FUNCTION_TYPE (V4SF, V2DF, V4SF, QI)
> DEF_FUNCTION_TYPE (V4SF, V4DF)
> +DEF_FUNCTION_TYPE (V4SF, V4DF, V4SF, QI)
> DEF_FUNCTION_TYPE (V4SF, V4SF)
> DEF_FUNCTION_TYPE (V4SF, PCV4SF)
> DEF_FUNCTION_TYPE (V4SF, V4SI)
> DEF_FUNCTION_TYPE (V4SF, V8SF)
> DEF_FUNCTION_TYPE (V4SF, V8HI)
> +DEF_FUNCTION_TYPE (V4SF, V8HI, V4SF, QI)
> DEF_FUNCTION_TYPE (V4SI, V16QI)
> DEF_FUNCTION_TYPE (V4SI, V2DF)
> DEF_FUNCTION_TYPE (V4SI, V4DF)
> @@ -241,6 +262,7 @@ DEF_FUNCTION_TYPE (V8SF, V4SF)
> DEF_FUNCTION_TYPE (V8SF, V8SF)
> DEF_FUNCTION_TYPE (V8SF, V8SI)
> DEF_FUNCTION_TYPE (V8SF, V8HI)
> +DEF_FUNCTION_TYPE (V8SF, V8HI, V8SF, QI)
> DEF_FUNCTION_TYPE (V16SF, V16SF)
> DEF_FUNCTION_TYPE (V8SI, V8DI)
> DEF_FUNCTION_TYPE (V8SI, V4SI)
> @@ -251,6 +273,9 @@ DEF_FUNCTION_TYPE (V32QI, V32QI)
> DEF_FUNCTION_TYPE (V32QI, V16QI)
> DEF_FUNCTION_TYPE (V16HI, V16SI)
> DEF_FUNCTION_TYPE (V16HI, V16HI)
> +DEF_FUNCTION_TYPE (V16SF, V16HI)
> +DEF_FUNCTION_TYPE (V16SF, V16HI, V16SF, HI)
> +DEF_FUNCTION_TYPE (V16SF, V16SI)
> DEF_FUNCTION_TYPE (V16HI, V8HI)
> DEF_FUNCTION_TYPE (V8SI, V8SI)
> DEF_FUNCTION_TYPE (VOID, PCVOID)
> @@ -266,8 +291,10 @@ DEF_FUNCTION_TYPE (V4DI, V16QI)
> DEF_FUNCTION_TYPE (V8SI, V8HI)
> DEF_FUNCTION_TYPE (V4DI, V8HI)
> DEF_FUNCTION_TYPE (V4DI, V4SI)
> +DEF_FUNCTION_TYPE (V4DI, V4DI)
> DEF_FUNCTION_TYPE (V4DI, PV4DI)
> DEF_FUNCTION_TYPE (V4DI, V2DI)
> +DEF_FUNCTION_TYPE (V16SI, V16SF)
> DEF_FUNCTION_TYPE (V16SF, FLOAT)
> DEF_FUNCTION_TYPE (V16SI, INT)
> DEF_FUNCTION_TYPE (V8DF, DOUBLE)
> @@ -290,10 +317,38 @@ DEF_FUNCTION_TYPE (V8DI, V8DI)
> DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, QI)
> DEF_FUNCTION_TYPE (V16SI, PV4SI)
> DEF_FUNCTION_TYPE (V16SF, PV4SF)
> +DEF_FUNCTION_TYPE (V8DI, PV2DI)
> +DEF_FUNCTION_TYPE (V8DF, PV2DF)
> +DEF_FUNCTION_TYPE (V4DI, PV2DI)
> +DEF_FUNCTION_TYPE (V4DF, PV2DF)
> +DEF_FUNCTION_TYPE (V16SI, PV2SI)
> +DEF_FUNCTION_TYPE (V16SF, PV2SF)
> DEF_FUNCTION_TYPE (V8DI, PV4DI)
> DEF_FUNCTION_TYPE (V8DF, PV4DF)
> +DEF_FUNCTION_TYPE (V8SF, FLOAT)
> +DEF_FUNCTION_TYPE (V4SF, FLOAT)
> +DEF_FUNCTION_TYPE (V4DF, DOUBLE)
> +DEF_FUNCTION_TYPE (V8SF, PV4SF)
> +DEF_FUNCTION_TYPE (V8SI, PV4SI)
> +DEF_FUNCTION_TYPE (V4SI, PV2SI)
> +DEF_FUNCTION_TYPE (V8SF, PV2SF)
> +DEF_FUNCTION_TYPE (V8SI, PV2SI)
> +DEF_FUNCTION_TYPE (V16SF, PV8SF)
> +DEF_FUNCTION_TYPE (V16SI, PV8SI)
> +DEF_FUNCTION_TYPE (V8DI, V8SF)
> +DEF_FUNCTION_TYPE (V4DI, V4SF)
> +DEF_FUNCTION_TYPE (V2DI, V4SF)
> +DEF_FUNCTION_TYPE (V64QI, QI)
> +DEF_FUNCTION_TYPE (V32HI, HI)
> DEF_FUNCTION_TYPE (V8UHI, V8UHI)
> +DEF_FUNCTION_TYPE (V16UHI, V16UHI)
> +DEF_FUNCTION_TYPE (V32UHI, V32UHI)
> +DEF_FUNCTION_TYPE (V2UDI, V2UDI)
> +DEF_FUNCTION_TYPE (V4UDI, V4UDI)
> +DEF_FUNCTION_TYPE (V8UDI, V8UDI)
> +DEF_FUNCTION_TYPE (V4USI, V4USI)
> DEF_FUNCTION_TYPE (V8USI, V8USI)
> +DEF_FUNCTION_TYPE (V16USI, V16USI)
> DEF_FUNCTION_TYPE (V8DI, PV8DI)
>
> DEF_FUNCTION_TYPE (DI, V2DI, INT)
> @@ -336,9 +391,13 @@ DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF)
> DEF_FUNCTION_TYPE (V2DF, V2DF, V2DI)
> DEF_FUNCTION_TYPE (V2DF, V2DF, V4SF)
> DEF_FUNCTION_TYPE (V2DF, V4DF, INT)
> +DEF_FUNCTION_TYPE (V2DF, V4DF, INT, V2DF, QI)
> +DEF_FUNCTION_TYPE (V2DF, V8DF, INT)
> +DEF_FUNCTION_TYPE (V2DF, V8DF, INT, V2DF, QI)
> DEF_FUNCTION_TYPE (V2DI, V16QI, V16QI)
> DEF_FUNCTION_TYPE (V2DI, V2DF, V2DF)
> DEF_FUNCTION_TYPE (V2DI, V2DI, INT)
> +DEF_FUNCTION_TYPE (V2DI, V2DI, INT, V2DI, QI)
> DEF_FUNCTION_TYPE (V2DI, V2DI, SI)
> DEF_FUNCTION_TYPE (V2DI, V2DI, V16QI)
> DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI)
> @@ -353,6 +412,7 @@ DEF_FUNCTION_TYPE (V2SI, V2SI, V2SI)
> DEF_FUNCTION_TYPE (V2SI, V4HI, V4HI)
> DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DI)
> DEF_FUNCTION_TYPE (V4DF, V4DF, INT)
> +DEF_FUNCTION_TYPE (V8DF, V8DF, INT)
> DEF_FUNCTION_TYPE (V4DF, V8DF, INT)
> DEF_FUNCTION_TYPE (V4DF, V8DF, INT, V4DF, QI)
> DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF)
> @@ -377,25 +437,36 @@ DEF_FUNCTION_TYPE (V4SF, V4SF, V2SI)
> DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF)
> DEF_FUNCTION_TYPE (V4SF, V4SF, V4SI)
> DEF_FUNCTION_TYPE (V4SF, V8SF, INT)
> +DEF_FUNCTION_TYPE (V4SF, V8SF, INT, V4SF, QI)
> DEF_FUNCTION_TYPE (V4SI, V2DF, V2DF)
> +DEF_FUNCTION_TYPE (V4SI, V2DF, V4SI, QI)
> DEF_FUNCTION_TYPE (V4SI, V4SF, V4SF)
> DEF_FUNCTION_TYPE (V4SI, V4SI, INT)
> +DEF_FUNCTION_TYPE (V4SI, V4SI, INT, V4SI, QI)
> DEF_FUNCTION_TYPE (V4SI, V4SI, SI)
> DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI)
> DEF_FUNCTION_TYPE (V4SI, V8HI, V8HI)
> +DEF_FUNCTION_TYPE (V4SI, V8HI, V8HI, V4SI, QI)
> DEF_FUNCTION_TYPE (V4SI, V8SI, INT)
> +DEF_FUNCTION_TYPE (V4SI, V8SI, INT, V4SI, QI)
> DEF_FUNCTION_TYPE (V4SI, PCV4SI, V4SI)
> DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI)
> +DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI, V8HI, QI)
> DEF_FUNCTION_TYPE (V8HI, V4SI, V4SI)
> DEF_FUNCTION_TYPE (V8HI, V8HI, INT)
> +DEF_FUNCTION_TYPE (V8DI, V8DI, INT)
> DEF_FUNCTION_TYPE (V8HI, V8HI, SI)
> DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI)
> DEF_FUNCTION_TYPE (V8HI, V8SF, INT)
> +DEF_FUNCTION_TYPE (V8HI, V8SF, INT, V8HI, QI)
> DEF_FUNCTION_TYPE (V8HI, V4SF, INT)
> +DEF_FUNCTION_TYPE (V8HI, V4SF, INT, V8HI, QI)
> DEF_FUNCTION_TYPE (V8QI, V4HI, V4HI)
> DEF_FUNCTION_TYPE (V8QI, V8QI, V8QI)
> DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SI)
> DEF_FUNCTION_TYPE (V8SF, V8SF, INT)
> +DEF_FUNCTION_TYPE (V8SF, V16SF, INT)
> +DEF_FUNCTION_TYPE (V8SF, V16SF, INT, V8SF, QI)
> DEF_FUNCTION_TYPE (V16SF, V16SF, INT)
> DEF_FUNCTION_TYPE (V4SF, V16SF, INT)
> DEF_FUNCTION_TYPE (V4SF, V16SF, INT, V4SF, QI)
> @@ -404,29 +475,46 @@ DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF)
> DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V16SI)
> DEF_FUNCTION_TYPE (V32QI, V16HI, V16HI)
> +DEF_FUNCTION_TYPE (V64QI, V32HI, V32HI)
> DEF_FUNCTION_TYPE (V16HI, V8SI, V8SI)
> +DEF_FUNCTION_TYPE (V32HI, V16SI, V16SI)
> +DEF_FUNCTION_TYPE (V8DF, V8DF, V2DF, INT)
> +DEF_FUNCTION_TYPE (V8DF, V8DF, V2DF, INT, V8DF, QI)
> DEF_FUNCTION_TYPE (V8DF, V8DF, V4DF, INT, V8DF, QI)
> +DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, INT)
> DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, INT, V8DF, QI)
> +DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, INT, V8DF, QI, INT)
> DEF_FUNCTION_TYPE (V8DF, V8DF, INT, V8DF, QI)
> +DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DI, INT)
> +DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DI, INT, QI)
> +DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DI, INT, QI)
> +DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT, QI)
> DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DI, INT, QI, INT)
> DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, INT)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, INT, V16SF, HI)
> +DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, INT, V16SF, HI, INT)
> DEF_FUNCTION_TYPE (V16SF, V16SF, INT, V16SF, HI)
> DEF_FUNCTION_TYPE (V16SI, V16SI, V4SI, INT, V16SI, HI)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SI, INT)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SI, INT, HI)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SI, INT, HI, INT)
> +DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SI, INT, QI)
> DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SI, INT, QI)
> DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SI, INT, QI, INT)
> -DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT, QI)
> DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT, QI, INT)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V4SF, INT)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V4SF, INT, V16SF, HI)
> +DEF_FUNCTION_TYPE (V16SF, V16SF, V8SF, INT, V16SF, HI)
> DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI)
> DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI)
> +DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI)
> +DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI, V16HI, HI)
> +DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI, V32HI, SI)
> DEF_FUNCTION_TYPE (V16HI, V16HI, V8HI)
> DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI)
> +DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI)
> +DEF_FUNCTION_TYPE (V32HI, V32HI, INT)
> DEF_FUNCTION_TYPE (V16HI, V16HI, INT)
> DEF_FUNCTION_TYPE (V16HI, V16SF, INT)
> DEF_FUNCTION_TYPE (V16HI, V16SF, INT, V16HI, HI)
> @@ -438,13 +526,20 @@ DEF_FUNCTION_TYPE (V8SI, V4DF, V4DF)
> DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI)
> DEF_FUNCTION_TYPE (V16SI, V16SI, V4SI)
> DEF_FUNCTION_TYPE (V16SI, V16SI, V4SI, INT)
> +DEF_FUNCTION_TYPE (V16SI, V16SI, V8SI, INT, V16SI, HI)
> DEF_FUNCTION_TYPE (V4SI, V16SI, INT)
> DEF_FUNCTION_TYPE (V4SI, V16SI, INT, V4SI, QI)
> DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI)
> DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI)
> DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, INT, V16SI, HI)
> DEF_FUNCTION_TYPE (V8SI, V16HI, V16HI)
> +DEF_FUNCTION_TYPE (V16SI, V32HI, V32HI)
> +DEF_FUNCTION_TYPE (V8SI, V16HI, V16HI, V8SI, QI)
> +DEF_FUNCTION_TYPE (V16SI, V32HI, V32HI, V16SI, HI)
> DEF_FUNCTION_TYPE (V8SI, V8SI, INT)
> +DEF_FUNCTION_TYPE (V8SI, V8SI, INT, V8SI, QI)
> +DEF_FUNCTION_TYPE (V8SI, V16SI, INT)
> +DEF_FUNCTION_TYPE (V8SI, V16SI, INT, V8SI, QI)
> DEF_FUNCTION_TYPE (V8SI, V8SI, SI)
> DEF_FUNCTION_TYPE (V16SI, V16SI, SI)
> DEF_FUNCTION_TYPE (V16SI, V16SI, INT)
> @@ -455,9 +550,17 @@ DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI)
> DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI)
> DEF_FUNCTION_TYPE (V16SI, V8DF, V8DF)
> DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, INT, V8DI, QI)
> +DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, INT, V8DI, DI)
> +DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT, V4DI, SI)
> +DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT, V2DI, HI)
> +DEF_FUNCTION_TYPE (V8DI, V8DI, V4DI, INT)
> +DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI, INT)
> +DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI, INT, V8DI, QI)
> DEF_FUNCTION_TYPE (V8DI, V8DI, V4DI, INT, V8DI, QI)
> DEF_FUNCTION_TYPE (V4DI, V8SI, V8SI)
> DEF_FUNCTION_TYPE (V4UDI, V8USI, V8USI)
> +DEF_FUNCTION_TYPE (V8DI, V16SI, V16SI)
> +DEF_FUNCTION_TYPE (V8DI, V64QI, V64QI)
> DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI)
> DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI)
> DEF_FUNCTION_TYPE (V4DI, PCV4DI, V4DI)
> @@ -466,8 +569,12 @@ DEF_FUNCTION_TYPE (V4DI, V8DI, INT, V4DI, QI)
> DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI, V8DI, QI)
> DEF_FUNCTION_TYPE (V8DI, V8DI, INT, V8DI, QI)
> DEF_FUNCTION_TYPE (V4DI, V4DI, INT)
> +DEF_FUNCTION_TYPE (V4DI, V4DI, INT, V4DI, QI)
> DEF_FUNCTION_TYPE (V2DI, V4DI, INT)
> DEF_FUNCTION_TYPE (VOID, PVOID, INT64)
> +DEF_FUNCTION_TYPE (V2DI, V4DI, INT, V2DI, QI)
> +DEF_FUNCTION_TYPE (V2DI, V8DI, INT)
> +DEF_FUNCTION_TYPE (V2DI, V8DI, INT, V2DI, QI)
> DEF_FUNCTION_TYPE (VOID, PCHAR, V16QI)
> DEF_FUNCTION_TYPE (VOID, PCHAR, V32QI)
> DEF_FUNCTION_TYPE (VOID, PDOUBLE, V2DF)
> @@ -489,9 +596,72 @@ DEF_FUNCTION_TYPE (VOID, UNSIGNED, UNSIGNED)
> DEF_FUNCTION_TYPE (VOID, PV8DI, V8DI)
>
> # Instructions returning mask
> +DEF_FUNCTION_TYPE (QI, QI)
> DEF_FUNCTION_TYPE (HI, HI)
> +DEF_FUNCTION_TYPE (SI, SI)
> +DEF_FUNCTION_TYPE (DI, DI)
> +DEF_FUNCTION_TYPE (HI, V16QI)
> +DEF_FUNCTION_TYPE (SI, V32QI)
> +DEF_FUNCTION_TYPE (DI, V64QI)
> +DEF_FUNCTION_TYPE (QI, V8HI)
> +DEF_FUNCTION_TYPE (HI, V16HI)
> +DEF_FUNCTION_TYPE (SI, V32HI)
> +DEF_FUNCTION_TYPE (QI, V4SI)
> +DEF_FUNCTION_TYPE (QI, V8SI)
> +DEF_FUNCTION_TYPE (HI, V16SI)
> +DEF_FUNCTION_TYPE (QI, V2DI)
> +DEF_FUNCTION_TYPE (QI, V4DI)
> +DEF_FUNCTION_TYPE (QI, V8DI)
> +DEF_FUNCTION_TYPE (V16QI, HI)
> +DEF_FUNCTION_TYPE (V32QI, SI)
> +DEF_FUNCTION_TYPE (V64QI, DI)
> +DEF_FUNCTION_TYPE (V8HI, QI)
> +DEF_FUNCTION_TYPE (V16HI, HI)
> +DEF_FUNCTION_TYPE (V32HI, SI)
> +DEF_FUNCTION_TYPE (V4SI, QI)
> +DEF_FUNCTION_TYPE (V4SI, HI)
> +DEF_FUNCTION_TYPE (V8SI, QI)
> +DEF_FUNCTION_TYPE (V8SI, HI)
> +DEF_FUNCTION_TYPE (V2DI, QI)
> +DEF_FUNCTION_TYPE (V4DI, QI)
> +DEF_FUNCTION_TYPE (QI, QI, QI)
> DEF_FUNCTION_TYPE (HI, HI, HI)
> +DEF_FUNCTION_TYPE (SI, SI, SI)
> +DEF_FUNCTION_TYPE (DI, DI, DI)
> +DEF_FUNCTION_TYPE (QI, QI, INT)
> DEF_FUNCTION_TYPE (HI, HI, INT)
> +DEF_FUNCTION_TYPE (SI, SI, INT)
> +DEF_FUNCTION_TYPE (DI, DI, INT)
> +DEF_FUNCTION_TYPE (HI, V16QI, V16QI)
> +DEF_FUNCTION_TYPE (HI, V16QI, V16QI, HI)
> +DEF_FUNCTION_TYPE (HI, V16QI, V16QI, INT, HI)
> +DEF_FUNCTION_TYPE (SI, V32QI, V32QI)
> +DEF_FUNCTION_TYPE (SI, V32QI, V32QI, SI)
> +DEF_FUNCTION_TYPE (SI, V32QI, V32QI, INT, SI)
> +DEF_FUNCTION_TYPE (DI, V64QI, V64QI)
> +DEF_FUNCTION_TYPE (DI, V64QI, V64QI, DI)
> +DEF_FUNCTION_TYPE (DI, V64QI, V64QI, INT, DI)
> +DEF_FUNCTION_TYPE (QI, V8HI, V8HI)
> +DEF_FUNCTION_TYPE (QI, V8HI, V8HI, QI)
> +DEF_FUNCTION_TYPE (QI, V8HI, V8HI, INT, QI)
> +DEF_FUNCTION_TYPE (HI, V16HI, V16HI)
> +DEF_FUNCTION_TYPE (HI, V16HI, V16HI, HI)
> +DEF_FUNCTION_TYPE (HI, V16HI, V16HI, INT, HI)
> +DEF_FUNCTION_TYPE (SI, V32HI, V32HI)
> +DEF_FUNCTION_TYPE (SI, V32HI, V32HI, SI)
> +DEF_FUNCTION_TYPE (SI, V32HI, V32HI, INT, SI)
> +DEF_FUNCTION_TYPE (QI, V4SI, V4SI)
> +DEF_FUNCTION_TYPE (QI, V4SI, V4SI, QI)
> +DEF_FUNCTION_TYPE (QI, V4SI, V4SI, INT, QI)
> +DEF_FUNCTION_TYPE (QI, V8SI, V8SI)
> +DEF_FUNCTION_TYPE (QI, V8SI, V8SI, QI)
> +DEF_FUNCTION_TYPE (QI, V8SI, V8SI, INT, QI)
> +DEF_FUNCTION_TYPE (QI, V2DI, V2DI)
> +DEF_FUNCTION_TYPE (QI, V2DI, V2DI, QI)
> +DEF_FUNCTION_TYPE (QI, V2DI, V2DI, INT, QI)
> +DEF_FUNCTION_TYPE (QI, V4DI, V4DI)
> +DEF_FUNCTION_TYPE (QI, V4DI, V4DI, QI)
> +DEF_FUNCTION_TYPE (QI, V4DI, V4DI, INT, QI)
> DEF_FUNCTION_TYPE (QI, V8DI, V8DI)
> DEF_FUNCTION_TYPE (QI, V8DI, V8DI, QI)
> DEF_FUNCTION_TYPE (HI, V16SI, V16SI)
> @@ -518,6 +688,7 @@ DEF_FUNCTION_TYPE (V8DI, QI)
> DEF_FUNCTION_TYPE (INT, V16QI, V16QI, INT)
> DEF_FUNCTION_TYPE (UCHAR, UINT, UINT, UINT)
> DEF_FUNCTION_TYPE (UCHAR, UINT64, UINT, UINT)
> +DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, V32HI)
> DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, V16HI)
> DEF_FUNCTION_TYPE (V16QI, V16QI, QI, INT)
> DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, INT)
> @@ -525,7 +696,10 @@ DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, V16QI)
> DEF_FUNCTION_TYPE (V1DI, V1DI, V1DI, INT)
> DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT)
> DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT, INT)
> +DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI, INT)
> DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DF)
> +DEF_FUNCTION_TYPE (V2DF, V2DI, V2DF, V2DF, QI)
> +DEF_FUNCTION_TYPE (V2DF, V2DF, V2DI, V2DF, QI)
> DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT)
> DEF_FUNCTION_TYPE (V2DI, V2DI, DI, INT)
> DEF_FUNCTION_TYPE (V2DI, V2DI, UINT, UINT)
> @@ -533,9 +707,11 @@ DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT)
> DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI)
> DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, V32QI)
> DEF_FUNCTION_TYPE (V4DF, V4DF, V2DF, INT)
> +DEF_FUNCTION_TYPE (V4DF, V4DF, V2DF, INT, V4DF, QI)
> DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, INT)
> DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DF)
> DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DI, INT)
> +DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, INT)
> DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V4DI)
> DEF_FUNCTION_TYPE (V4HI, V4HI, HI, INT)
> DEF_FUNCTION_TYPE (V4SF, V4SF, FLOAT, INT)
> @@ -544,6 +720,10 @@ DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, INT, INT)
> DEF_FUNCTION_TYPE (V4SF, V4SF, V2DF, INT)
> DEF_FUNCTION_TYPE (V2DF, V2DF, V4SF, INT)
> DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF)
> +DEF_FUNCTION_TYPE (V4SF, V4SI, V4SF, V4SF, QI)
> +DEF_FUNCTION_TYPE (V4SF, V4SF, V4SI, V4SF, QI)
> +DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF, QI)
> +DEF_FUNCTION_TYPE (V4SF, V4SF, V2DF, V4SF, QI)
> DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SI, INT)
> DEF_FUNCTION_TYPE (V4SI, V4SI, SI, INT)
> DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, INT)
> @@ -554,76 +734,263 @@ DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, INT)
> DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, V4SI)
> DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, V8HI)
> DEF_FUNCTION_TYPE (V8SF, V8SF, V4SF, INT)
> +DEF_FUNCTION_TYPE (V8SF, V8SF, V4SF, INT, V8SF, QI)
> DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, INT)
> DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SF)
> DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SI, INT)
> DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DF)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SF)
> DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI, INT)
> +DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI, INT, V8SI, QI)
> DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, INT)
> DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI)
> DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT)
> DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI, INT)
> +DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI, INT, V4DI, QI)
>
> # Instructions with masking
> +DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, QI)
> +DEF_FUNCTION_TYPE (V2DF, V4SF, V2DF, QI)
> +DEF_FUNCTION_TYPE (V2DF, V4SI, V2DF, QI)
> +DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, QI)
> +DEF_FUNCTION_TYPE (V4DF, V4SF, V4DF, QI)
> +DEF_FUNCTION_TYPE (V4DF, V4SI, V4DF, QI)
> DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, QI)
> DEF_FUNCTION_TYPE (V8DF, V8SF, V8DF, QI)
> DEF_FUNCTION_TYPE (V8DF, V8SI, V8DF, QI)
> +DEF_FUNCTION_TYPE (V2DI, V4SI, V2DI, QI)
> +DEF_FUNCTION_TYPE (V2DI, V8HI, V2DI, QI)
> +DEF_FUNCTION_TYPE (V8DI, V8DF, V8DI, QI)
> +DEF_FUNCTION_TYPE (V4DI, V4DF, V4DI, QI)
> +DEF_FUNCTION_TYPE (V2DI, V2DF, V2DI, QI)
> +DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI, QI)
> +DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT, V2DI, QI)
> +DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V4DI, QI)
> +DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT, V4DI, QI)
> DEF_FUNCTION_TYPE (V8DI, V8SI, V8DI, QI)
> DEF_FUNCTION_TYPE (V8DI, V8HI, V8DI, QI)
> DEF_FUNCTION_TYPE (V8DI, V16QI, V8DI, QI)
> +DEF_FUNCTION_TYPE (V2DI, V16QI, V2DI, QI)
> +DEF_FUNCTION_TYPE (V4DI, V16QI, V4DI, QI)
> +DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, QI)
> +DEF_FUNCTION_TYPE (V4DI, V4SI, V4DI, QI)
> +DEF_FUNCTION_TYPE (V4DI, V8HI, V4DI, QI)
> DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI, QI)
> DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, V8DF)
> DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, V8DF, QI)
> DEF_FUNCTION_TYPE (V8DF, V8DF, V8DI, V8DF, QI)
> +DEF_FUNCTION_TYPE (V4DF, V4DI, V4DF, V4DF, QI)
> +DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI, V4DF, QI)
> +DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DF, QI)
> DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DF, QI)
> +DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, V16QI, HI)
> +DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, V16HI, HI)
> DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI, HI)
> DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DF, QI)
> DEF_FUNCTION_TYPE (V2DF, V2DF, V4SF, V2DF, QI)
> +DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, V32HI, SI)
> +DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, V64QI, DI)
> +DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, V32QI, SI)
> +DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, V8HI, QI)
> +DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, QI)
> +DEF_FUNCTION_TYPE (V4SF, V4SI, V4SF, QI)
> +DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, QI)
> +DEF_FUNCTION_TYPE (V8SF, V8SI, V8SF, QI)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, HI)
> DEF_FUNCTION_TYPE (V16SF, V16SI, V16SF, HI)
> +DEF_FUNCTION_TYPE (V4SI, V16QI, V4SI, QI)
> +DEF_FUNCTION_TYPE (V4SI, V8HI, V4SI, QI)
> +DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, QI)
> +DEF_FUNCTION_TYPE (V8SI, V8HI, V8SI, QI)
> +DEF_FUNCTION_TYPE (V8SI, V16QI, V8SI, QI)
> +DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, QI)
> +DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, INT, V4SI, QI)
> +DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SF, QI)
> +DEF_FUNCTION_TYPE (V8SF, V8SI, V8SF, V8SF, QI)
> +DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI, V8SF, QI)
> +DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI, QI)
> +DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, INT, V8SI, QI)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SF, HI)
> DEF_FUNCTION_TYPE (V16SF, V16SI, V16SF, V16SF)
> DEF_FUNCTION_TYPE (V16SF, V16SI, V16SF, V16SF, HI)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V16SI, V16SF, HI)
> -DEF_FUNCTION_TYPE (V4SF, V4SF, V2DF, V4SF, QI)
> -DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF, QI)
> +DEF_FUNCTION_TYPE (V16SF, V8SF, V16SF, HI)
> DEF_FUNCTION_TYPE (V16SF, V4SF, V16SF, HI)
> DEF_FUNCTION_TYPE (V8DF, V4DF, V8DF, QI)
> DEF_FUNCTION_TYPE (V8DF, V2DF, V8DF, QI)
> +DEF_FUNCTION_TYPE (V16SI, V8SI, V16SI, HI)
> DEF_FUNCTION_TYPE (V16SI, V4SI, V16SI, HI)
> DEF_FUNCTION_TYPE (V16SI, SI, V16SI, HI)
> DEF_FUNCTION_TYPE (V16SI, V16HI, V16SI, HI)
> DEF_FUNCTION_TYPE (V16SI, V16QI, V16SI, HI)
> DEF_FUNCTION_TYPE (V8SI, V8DF, V8SI, QI)
> DEF_FUNCTION_TYPE (V8DI, V4DI, V8DI, QI)
> +DEF_FUNCTION_TYPE (V4SI, V4DF, V4SI, QI)
> DEF_FUNCTION_TYPE (V8DI, V2DI, V8DI, QI)
> DEF_FUNCTION_TYPE (V8DI, DI, V8DI, QI)
> +DEF_FUNCTION_TYPE (V8DI, PCCHAR, V8DI, QI)
> +DEF_FUNCTION_TYPE (V8SF, PCFLOAT, V8SF, QI)
> +DEF_FUNCTION_TYPE (V4SF, PCFLOAT, V4SF, QI)
> +DEF_FUNCTION_TYPE (V4DF, PCDOUBLE, V4DF, QI)
> +DEF_FUNCTION_TYPE (V2DF, PCDOUBLE, V2DF, QI)
> +DEF_FUNCTION_TYPE (V8SI, PCCHAR, V8SI, QI)
> +DEF_FUNCTION_TYPE (V4SI, PCCHAR, V4SI, QI)
> +DEF_FUNCTION_TYPE (V4DI, PCCHAR, V4DI, QI)
> +DEF_FUNCTION_TYPE (V2DI, PCCHAR, V2DI, QI)
> +DEF_FUNCTION_TYPE (V16QI, V16SI, V16QI, HI)
> +DEF_FUNCTION_TYPE (V16QI, V8DI, V16QI, QI)
> +DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, SI)
> +DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI, INT)
> +DEF_FUNCTION_TYPE (V32HI, V32QI, V32HI, SI)
> +DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, HI)
> +DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI, INT)
> +DEF_FUNCTION_TYPE (V16HI, V16QI, V16HI, HI)
> +DEF_FUNCTION_TYPE (V8HI, V16QI, V8HI, QI)
> +DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI, INT)
> +DEF_FUNCTION_TYPE (V8SF, V4SF, V8SF, QI)
> +DEF_FUNCTION_TYPE (V4DF, V2DF, V4DF, QI)
> +DEF_FUNCTION_TYPE (V8SI, V4SI, V8SI, QI)
> +DEF_FUNCTION_TYPE (V8SI, SI, V8SI, QI)
> +DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, QI)
> +DEF_FUNCTION_TYPE (V4SI, SI, V4SI, QI)
> +DEF_FUNCTION_TYPE (V4DI, V2DI, V4DI, QI)
> +DEF_FUNCTION_TYPE (V4DI, DI, V4DI, QI)
> +DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, QI)
> +DEF_FUNCTION_TYPE (V2DI, DI, V2DI, QI)
> +DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, DI)
> +DEF_FUNCTION_TYPE (V64QI, V16QI, V64QI, DI)
> +DEF_FUNCTION_TYPE (V64QI, QI, V64QI, DI)
> +DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, SI)
> +DEF_FUNCTION_TYPE (V32QI, V16QI, V32QI, SI)
> +DEF_FUNCTION_TYPE (V32QI, QI, V32QI, SI)
> +DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, HI)
> +DEF_FUNCTION_TYPE (V16QI, QI, V16QI, HI)
> +DEF_FUNCTION_TYPE (V32HI, V8HI, V32HI, SI)
> +DEF_FUNCTION_TYPE (V32HI, HI, V32HI, SI)
> +DEF_FUNCTION_TYPE (V16HI, V8HI, V16HI, HI)
> +DEF_FUNCTION_TYPE (V16HI, HI, V16HI, HI)
> +DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, QI)
> +DEF_FUNCTION_TYPE (V8HI, HI, V8HI, QI)
> +DEF_FUNCTION_TYPE (V64QI, PCV64QI, V64QI, DI)
> +DEF_FUNCTION_TYPE (V32HI, PCV32HI, V32HI, SI)
> +DEF_FUNCTION_TYPE (V32QI, PCV32QI, V32QI, SI)
> DEF_FUNCTION_TYPE (V16SF, PCV16SF, V16SF, HI)
> +DEF_FUNCTION_TYPE (V16SF, PCV8SF, V16SF, HI)
> DEF_FUNCTION_TYPE (V8DF, PCV8DF, V8DF, QI)
> DEF_FUNCTION_TYPE (V16SI, PCV16SI, V16SI, HI)
> +DEF_FUNCTION_TYPE (V16SI, PCV8SI, V16SI, HI)
> +DEF_FUNCTION_TYPE (V16HI, PCV16HI, V16HI, HI)
> +DEF_FUNCTION_TYPE (V16QI, PCV16QI, V16QI, HI)
> +DEF_FUNCTION_TYPE (V8DF, PCV2DF, V8DF, QI)
> +DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SF, QI)
> +DEF_FUNCTION_TYPE (V8SF, PCV4SF, V8SF, QI)
> DEF_FUNCTION_TYPE (V8DI, PCV8DI, V8DI, QI)
> -DEF_FUNCTION_TYPE (V2DF, PCDOUBLE, V2DF, QI)
> -DEF_FUNCTION_TYPE (V4SF, PCFLOAT, V4SF, QI)
> -DEF_FUNCTION_TYPE (V16QI, V16SI, V16QI, HI)
> +DEF_FUNCTION_TYPE (V8DI, PCV2DI, V8DI, QI)
> +DEF_FUNCTION_TYPE (V8SI, PCV8SI, V8SI, QI)
> +DEF_FUNCTION_TYPE (V8SI, PCV4SI, V8SI, QI)
> +DEF_FUNCTION_TYPE (V8HI, PCV8HI, V8HI, QI)
> +DEF_FUNCTION_TYPE (V4DF, PCV2DF, V4DF, QI)
> +DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DF, QI)
> +DEF_FUNCTION_TYPE (V4SF, PCV4SF, V4SF, QI)
> +DEF_FUNCTION_TYPE (V4DI, PCV4DI, V4DI, QI)
> +DEF_FUNCTION_TYPE (V4DI, PCV2DI, V4DI, QI)
> +DEF_FUNCTION_TYPE (V4SI, PCV4SI, V4SI, QI)
> +DEF_FUNCTION_TYPE (V2DF, PCV2DF, V2DF, QI)
> +DEF_FUNCTION_TYPE (V2DI, PCV2DI, V2DI, QI)
> DEF_FUNCTION_TYPE (V16HI, V16SI, V16HI, HI)
> DEF_FUNCTION_TYPE (V8SI, V8DI, V8SI, QI)
> DEF_FUNCTION_TYPE (V8HI, V8DI, V8HI, QI)
> -DEF_FUNCTION_TYPE (V16QI, V8DI, V16QI, QI)
> +DEF_FUNCTION_TYPE (V16QI, V8HI, V16QI, QI)
> +DEF_FUNCTION_TYPE (V16QI, V16HI, V16QI, HI)
> +DEF_FUNCTION_TYPE (V16QI, V4SI, V16QI, QI)
> +DEF_FUNCTION_TYPE (V16QI, V8SI, V16QI, QI)
> +DEF_FUNCTION_TYPE (V8HI, V4SI, V8HI, QI)
> +DEF_FUNCTION_TYPE (V8HI, V8SI, V8HI, QI)
> +DEF_FUNCTION_TYPE (V16QI, V2DI, V16QI, QI)
> +DEF_FUNCTION_TYPE (V16QI, V4DI, V16QI, QI)
> +DEF_FUNCTION_TYPE (V8HI, V2DI, V8HI, QI)
> +DEF_FUNCTION_TYPE (V8HI, V4DI, V8HI, QI)
> +DEF_FUNCTION_TYPE (V4SI, V2DI, V4SI, QI)
> +DEF_FUNCTION_TYPE (V4SI, V4DI, V4SI, QI)
> +DEF_FUNCTION_TYPE (V32QI, V32HI, V32QI, SI)
> +DEF_FUNCTION_TYPE (V2DF, V2DF, INT, V2DF, QI)
> +DEF_FUNCTION_TYPE (V4DF, V4DF, INT, V4DF, QI)
> +DEF_FUNCTION_TYPE (V4SF, V4SF, INT, V4SF, QI)
> +DEF_FUNCTION_TYPE (V8SF, V8SF, INT, V8SF, QI)
> +DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, INT, V4DF, QI)
> +DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT, V2DF, QI)
> +DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, INT, V8SF, QI)
> +DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, INT, V4SF, QI)
> DEF_FUNCTION_TYPE (VOID, PV8DF, V8DF, QI)
> DEF_FUNCTION_TYPE (VOID, PV8SI, V8DI, QI)
> DEF_FUNCTION_TYPE (VOID, PV8HI, V8DI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV8HI, V4DI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV8HI, V2DI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV4SI, V4DI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV4SI, V2DI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV8HI, V8SI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV8HI, V4SI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV4DF, V4DF, QI)
> +DEF_FUNCTION_TYPE (VOID, PV2DF, V2DF, QI)
> DEF_FUNCTION_TYPE (VOID, PV16SF, V16SF, HI)
> +DEF_FUNCTION_TYPE (VOID, PV8SF, V8SF, QI)
> +DEF_FUNCTION_TYPE (VOID, PV4SF, V4SF, QI)
> DEF_FUNCTION_TYPE (VOID, PV8DI, V8DI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV4DI, V4DI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV2DI, V2DI, QI)
> DEF_FUNCTION_TYPE (VOID, PV16SI, V16SI, HI)
> DEF_FUNCTION_TYPE (VOID, PV16HI, V16SI, HI)
> DEF_FUNCTION_TYPE (VOID, PV16QI, V16SI, HI)
> +DEF_FUNCTION_TYPE (VOID, PV16QI, V8SI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV16QI, V4SI, QI)
> DEF_FUNCTION_TYPE (VOID, PV16QI, V8DI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV16QI, V4DI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV16QI, V2DI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV8SI, V8SI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV4SI, V4SI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV32HI, V32HI, SI)
> +DEF_FUNCTION_TYPE (VOID, PV16HI, V16HI, HI)
> +DEF_FUNCTION_TYPE (VOID, PV8HI, V8HI, QI)
> +DEF_FUNCTION_TYPE (VOID, PV64QI, V64QI, DI)
> +DEF_FUNCTION_TYPE (VOID, PV32QI, V32QI, SI)
> +DEF_FUNCTION_TYPE (VOID, PV16QI, V16QI, HI)
> DEF_FUNCTION_TYPE (VOID, PDOUBLE, V2DF, QI)
> DEF_FUNCTION_TYPE (VOID, PFLOAT, V4SF, QI)
> DEF_FUNCTION_TYPE (V16SI, V16SF, V16SI, HI)
> DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI, INT, QI)
> +DEF_FUNCTION_TYPE (V8SI, V8SF, V8SI, QI)
> +DEF_FUNCTION_TYPE (V4SI, V4SF, V4SI, QI)
> +DEF_FUNCTION_TYPE (V8DI, V8SF, V8DI, QI)
> +DEF_FUNCTION_TYPE (V4DI, V4SF, V4DI, QI)
> +DEF_FUNCTION_TYPE (V2DI, V4SF, V2DI, QI)
> +DEF_FUNCTION_TYPE (V8SF, V8DI, V8SF, QI)
> +DEF_FUNCTION_TYPE (V4SF, V4DI, V4SF, QI)
> +DEF_FUNCTION_TYPE (V4SF, V2DI, V4SF, QI)
> +DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, QI)
> +DEF_FUNCTION_TYPE (V4DF, V4DI, V4DF, QI)
> +DEF_FUNCTION_TYPE (V2DF, V2DI, V2DF, QI)
> +DEF_FUNCTION_TYPE (V32HI, V32HI, INT, V32HI, SI)
> +DEF_FUNCTION_TYPE (V32HI, V32HI, V8HI, V32HI, SI)
> +DEF_FUNCTION_TYPE (V16HI, V16HI, INT, V16HI, HI)
> +DEF_FUNCTION_TYPE (V16HI, V16HI, V8HI, V16HI, HI)
> +DEF_FUNCTION_TYPE (V8HI, V8HI, INT, V8HI, QI)
> +DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI, INT, V32HI, SI)
> +DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI, INT, V16HI, HI)
> +DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI, INT, V8HI, QI)
> +DEF_FUNCTION_TYPE (V64QI, V32HI, V32HI, V64QI, DI)
> +DEF_FUNCTION_TYPE (V32QI, V16HI, V16HI, V32QI, SI)
> +DEF_FUNCTION_TYPE (V16QI, V8HI, V8HI, V16QI, HI)
> +DEF_FUNCTION_TYPE (V32HI, V16SI, V16SI, V32HI, SI)
> +DEF_FUNCTION_TYPE (V16HI, V8SI, V8SI, V16HI, HI)
> +DEF_FUNCTION_TYPE (V8HI, V4SI, V4SI, V8HI, QI)
> +DEF_FUNCTION_TYPE (V8DI, V16SI, V16SI, V8DI, QI)
> +DEF_FUNCTION_TYPE (V4DI, V8SI, V8SI, V4DI, QI)
> +DEF_FUNCTION_TYPE (V2DI, V4SI, V4SI, V2DI, QI)
> DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI, INT, HI)
> +DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI, INT, QI)
> +DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V4DI, INT, QI)
> +DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT, QI)
> +DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI, INT, QI)
>
> DEF_FUNCTION_TYPE (VOID, PCVOID, UNSIGNED, UNSIGNED)
> DEF_FUNCTION_TYPE (VOID, PV2DF, V2DI, V2DF)
> @@ -648,11 +1015,30 @@ DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DI)
> DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SI)
> DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI)
> DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI)
> +DEF_FUNCTION_TYPE (V2DF, V2DF, V2DI, V2DF)
> +DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI, V4DF)
> DEF_FUNCTION_TYPE (V8DF, V8DF, V8DI, V8DF)
> +DEF_FUNCTION_TYPE (V4SF, V4SF, V4SI, V4SF)
> +DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI, V8SF)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V16SI, V16SF)
> -DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, INT, V4SF, QI)
> -DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT, V2DF, QI)
> -DEF_FUNCTION_TYPE (V8DI, V16SI, V16SI, V8DI, QI)
> +
> +DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI, V8SI, QI)
> +DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI, V4DI, QI)
> +
> +DEF_FUNCTION_TYPE (QI, V8DF, INT)
> +DEF_FUNCTION_TYPE (QI, V4DF, INT)
> +DEF_FUNCTION_TYPE (QI, V4DF, V4DF, INT, QI)
> +DEF_FUNCTION_TYPE (QI, V2DF, INT)
> +DEF_FUNCTION_TYPE (HI, V16SF, INT)
> +DEF_FUNCTION_TYPE (QI, V8SF, INT)
> +DEF_FUNCTION_TYPE (QI, V8SF, V8SF, INT, QI)
> +DEF_FUNCTION_TYPE (QI, V4SF, INT)
> +DEF_FUNCTION_TYPE (QI, V8DF, INT, QI)
> +DEF_FUNCTION_TYPE (QI, V4DF, INT, QI)
> +DEF_FUNCTION_TYPE (QI, V2DF, INT, QI)
> +DEF_FUNCTION_TYPE (HI, V16SF, INT, HI)
> +DEF_FUNCTION_TYPE (QI, V8SF, INT, QI)
> +DEF_FUNCTION_TYPE (QI, V4SF, INT, QI)
>
> DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, UINT, UINT)
> DEF_FUNCTION_TYPE (V4HI, HI, HI, HI, HI)
> @@ -688,6 +1074,10 @@ DEF_FUNCTION_TYPE (V8SI, V8DF, V8SI, QI, INT)
> DEF_FUNCTION_TYPE (V8SF, V8DF, V8SF, QI, INT)
> DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, QI, INT)
> DEF_FUNCTION_TYPE (V8DF, V8SF, V8DF, QI, INT)
> +DEF_FUNCTION_TYPE (V8DI, V8DF, V8DI, QI, INT)
> +DEF_FUNCTION_TYPE (V8DI, V8SF, V8DI, QI, INT)
> +DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, QI, INT)
> +DEF_FUNCTION_TYPE (V8SF, V8DI, V8SF, QI, INT)
> DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SF, HI, INT)
> DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DF, QI, INT)
> DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF, QI, INT)
> @@ -736,16 +1126,53 @@ DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V8SI, QI, INT)
> DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V16SI, QI, INT)
> DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V8DI, QI, INT)
> DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V8DI, QI, INT)
> +DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE, V4SI, QI, INT)
> +DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V4SI, QI, INT)
> +DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V8SI, QI, INT)
> +DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE, V2DI, QI, INT)
> +DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V4DI, QI, INT)
> +DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V4SI, QI, INT)
> +DEF_FUNCTION_TYPE (V8SF, V8SF, PCFLOAT, V8SI, QI, INT)
> +DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V2DI, QI, INT)
> +DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V4DI, QI, INT)
> +DEF_FUNCTION_TYPE (V8SF, V8SF, PCFLOAT, V4DI, QI, INT)
> +DEF_FUNCTION_TYPE (V2DI, V2DI, PCINT64, V4SI, QI, INT)
> +DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V4SI, QI, INT)
> +DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V8SI, QI, INT)
> +DEF_FUNCTION_TYPE (V2DI, V2DI, PCINT64, V2DI, QI, INT)
> +DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V4DI, QI, INT)
> +DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V4SI, QI, INT)
> +DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V8SI, QI, INT)
> +DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V2DI, QI, INT)
> +DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V4DI, QI, INT)
> +DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V4DI, QI, INT)
> +
> DEF_FUNCTION_TYPE (VOID, PFLOAT, HI, V16SI, V16SF, INT)
> +DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V8SI, V8SF, INT)
> +DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V4SI, V4SF, INT)
> DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V8SI, V8DF, INT)
> +DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4SI, V4DF, INT)
> +DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4SI, V2DF, INT)
> DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V8DI, V8SF, INT)
> +DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V4DI, V4SF, INT)
> +DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V2DI, V4SF, INT)
> DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V8DI, V8DF, INT)
> +DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4DI, V4DF, INT)
> +DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V2DI, V2DF, INT)
> DEF_FUNCTION_TYPE (VOID, PINT, HI, V16SI, V16SI, INT)
> +DEF_FUNCTION_TYPE (VOID, PINT, QI, V8SI, V8SI, INT)
> +DEF_FUNCTION_TYPE (VOID, PINT, QI, V4SI, V4SI, INT)
> DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V8SI, V8DI, INT)
> +DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4SI, V4DI, INT)
> +DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4SI, V2DI, INT)
> DEF_FUNCTION_TYPE (VOID, PINT, QI, V8DI, V8SI, INT)
> +DEF_FUNCTION_TYPE (VOID, PINT, QI, V4DI, V4SI, INT)
> +DEF_FUNCTION_TYPE (VOID, PINT, QI, V2DI, V4SI, INT)
> DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V8DI, V8DI, INT)
>
> DEF_FUNCTION_TYPE (VOID, QI, V8SI, PCINT64, INT, INT)
> +DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4DI, V4DI, INT)
> +DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V2DI, V2DI, INT)
> DEF_FUNCTION_TYPE (VOID, HI, V16SI, PCINT, INT, INT)
> DEF_FUNCTION_TYPE (VOID, QI, V8DI, PCINT64, INT, INT)
> DEF_FUNCTION_TYPE (VOID, QI, V8DI, PCINT, INT, INT)
> @@ -793,8 +1220,13 @@ DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_V2DI, COUNT)
> DEF_FUNCTION_TYPE_ALIAS (V2DF_FTYPE_V2DF_V2DF, SWAP)
> DEF_FUNCTION_TYPE_ALIAS (V4SF_FTYPE_V4SF_V4SF, SWAP)
>
> +DEF_FUNCTION_TYPE_ALIAS (V8DI_FTYPE_V8DI_INT, CONVERT)
> DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_INT, CONVERT)
> DEF_FUNCTION_TYPE_ALIAS (V2DI_FTYPE_V2DI_INT, CONVERT)
> +DEF_FUNCTION_TYPE_ALIAS (V8DI_FTYPE_V8DI_V8DI_INT, CONVERT)
> +DEF_FUNCTION_TYPE_ALIAS (V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI, CONVERT)
> +DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI, CONVERT)
> +DEF_FUNCTION_TYPE_ALIAS (V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI, CONVERT)
> DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_V4DI_INT, CONVERT)
> DEF_FUNCTION_TYPE_ALIAS (V2DI_FTYPE_V2DI_V2DI_INT, CONVERT)
> DEF_FUNCTION_TYPE_ALIAS (V1DI_FTYPE_V1DI_V1DI_INT, CONVERT)
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 33b21f4..87992b0 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -28635,6 +28635,995 @@ enum ix86_builtins
> IX86_BUILTIN_KXOR16,
> IX86_BUILTIN_KMOV16,
>
> + /* AVX512VL. */
> + IX86_BUILTIN_PMOVUSQD256_MEM,
> + IX86_BUILTIN_PMOVUSQD128_MEM,
> + IX86_BUILTIN_PMOVSQD256_MEM,
> + IX86_BUILTIN_PMOVSQD128_MEM,
> + IX86_BUILTIN_PMOVQD256_MEM,
> + IX86_BUILTIN_PMOVQD128_MEM,
> + IX86_BUILTIN_PMOVUSQW256_MEM,
> + IX86_BUILTIN_PMOVUSQW128_MEM,
> + IX86_BUILTIN_PMOVSQW256_MEM,
> + IX86_BUILTIN_PMOVSQW128_MEM,
> + IX86_BUILTIN_PMOVQW256_MEM,
> + IX86_BUILTIN_PMOVQW128_MEM,
> + IX86_BUILTIN_PMOVUSQB256_MEM,
> + IX86_BUILTIN_PMOVUSQB128_MEM,
> + IX86_BUILTIN_PMOVSQB256_MEM,
> + IX86_BUILTIN_PMOVSQB128_MEM,
> + IX86_BUILTIN_PMOVQB256_MEM,
> + IX86_BUILTIN_PMOVQB128_MEM,
> + IX86_BUILTIN_PMOVUSDW256_MEM,
> + IX86_BUILTIN_PMOVUSDW128_MEM,
> + IX86_BUILTIN_PMOVSDW256_MEM,
> + IX86_BUILTIN_PMOVSDW128_MEM,
> + IX86_BUILTIN_PMOVDW256_MEM,
> + IX86_BUILTIN_PMOVDW128_MEM,
> + IX86_BUILTIN_PMOVUSDB256_MEM,
> + IX86_BUILTIN_PMOVUSDB128_MEM,
> + IX86_BUILTIN_PMOVSDB256_MEM,
> + IX86_BUILTIN_PMOVSDB128_MEM,
> + IX86_BUILTIN_PMOVDB256_MEM,
> + IX86_BUILTIN_PMOVDB128_MEM,
> + IX86_BUILTIN_MOVDQA64LOAD256_MASK,
> + IX86_BUILTIN_MOVDQA64LOAD128_MASK,
> + IX86_BUILTIN_MOVDQA32LOAD256_MASK,
> + IX86_BUILTIN_MOVDQA32LOAD128_MASK,
> + IX86_BUILTIN_MOVDQA64STORE256_MASK,
> + IX86_BUILTIN_MOVDQA64STORE128_MASK,
> + IX86_BUILTIN_MOVDQA32STORE256_MASK,
> + IX86_BUILTIN_MOVDQA32STORE128_MASK,
> + IX86_BUILTIN_LOADAPD256_MASK,
> + IX86_BUILTIN_LOADAPD128_MASK,
> + IX86_BUILTIN_LOADAPS256_MASK,
> + IX86_BUILTIN_LOADAPS128_MASK,
> + IX86_BUILTIN_STOREAPD256_MASK,
> + IX86_BUILTIN_STOREAPD128_MASK,
> + IX86_BUILTIN_STOREAPS256_MASK,
> + IX86_BUILTIN_STOREAPS128_MASK,
> + IX86_BUILTIN_LOADUPD256_MASK,
> + IX86_BUILTIN_LOADUPD128_MASK,
> + IX86_BUILTIN_LOADUPS256_MASK,
> + IX86_BUILTIN_LOADUPS128_MASK,
> + IX86_BUILTIN_STOREUPD256_MASK,
> + IX86_BUILTIN_STOREUPD128_MASK,
> + IX86_BUILTIN_STOREUPS256_MASK,
> + IX86_BUILTIN_STOREUPS128_MASK,
> + IX86_BUILTIN_LOADDQUDI256_MASK,
> + IX86_BUILTIN_LOADDQUDI128_MASK,
> + IX86_BUILTIN_LOADDQUSI256_MASK,
> + IX86_BUILTIN_LOADDQUSI128_MASK,
> + IX86_BUILTIN_LOADDQUHI256_MASK,
> + IX86_BUILTIN_LOADDQUHI128_MASK,
> + IX86_BUILTIN_LOADDQUQI256_MASK,
> + IX86_BUILTIN_LOADDQUQI128_MASK,
> + IX86_BUILTIN_STOREDQUDI256_MASK,
> + IX86_BUILTIN_STOREDQUDI128_MASK,
> + IX86_BUILTIN_STOREDQUSI256_MASK,
> + IX86_BUILTIN_STOREDQUSI128_MASK,
> + IX86_BUILTIN_STOREDQUHI256_MASK,
> + IX86_BUILTIN_STOREDQUHI128_MASK,
> + IX86_BUILTIN_STOREDQUQI256_MASK,
> + IX86_BUILTIN_STOREDQUQI128_MASK,
> + IX86_BUILTIN_COMPRESSPDSTORE256,
> + IX86_BUILTIN_COMPRESSPDSTORE128,
> + IX86_BUILTIN_COMPRESSPSSTORE256,
> + IX86_BUILTIN_COMPRESSPSSTORE128,
> + IX86_BUILTIN_PCOMPRESSQSTORE256,
> + IX86_BUILTIN_PCOMPRESSQSTORE128,
> + IX86_BUILTIN_PCOMPRESSDSTORE256,
> + IX86_BUILTIN_PCOMPRESSDSTORE128,
> + IX86_BUILTIN_EXPANDPDLOAD256,
> + IX86_BUILTIN_EXPANDPDLOAD128,
> + IX86_BUILTIN_EXPANDPSLOAD256,
> + IX86_BUILTIN_EXPANDPSLOAD128,
> + IX86_BUILTIN_PEXPANDQLOAD256,
> + IX86_BUILTIN_PEXPANDQLOAD128,
> + IX86_BUILTIN_PEXPANDDLOAD256,
> + IX86_BUILTIN_PEXPANDDLOAD128,
> + IX86_BUILTIN_EXPANDPDLOAD256Z,
> + IX86_BUILTIN_EXPANDPDLOAD128Z,
> + IX86_BUILTIN_EXPANDPSLOAD256Z,
> + IX86_BUILTIN_EXPANDPSLOAD128Z,
> + IX86_BUILTIN_PEXPANDQLOAD256Z,
> + IX86_BUILTIN_PEXPANDQLOAD128Z,
> + IX86_BUILTIN_PEXPANDDLOAD256Z,
> + IX86_BUILTIN_PEXPANDDLOAD128Z,
> + IX86_BUILTIN_PALIGNR256_MASK,
> + IX86_BUILTIN_PALIGNR128_MASK,
> + IX86_BUILTIN_MOVDQA64_256_MASK,
> + IX86_BUILTIN_MOVDQA64_128_MASK,
> + IX86_BUILTIN_MOVDQA32_256_MASK,
> + IX86_BUILTIN_MOVDQA32_128_MASK,
> + IX86_BUILTIN_MOVAPD256_MASK,
> + IX86_BUILTIN_MOVAPD128_MASK,
> + IX86_BUILTIN_MOVAPS256_MASK,
> + IX86_BUILTIN_MOVAPS128_MASK,
> + IX86_BUILTIN_MOVDQUHI256_MASK,
> + IX86_BUILTIN_MOVDQUHI128_MASK,
> + IX86_BUILTIN_MOVDQUQI256_MASK,
> + IX86_BUILTIN_MOVDQUQI128_MASK,
> + IX86_BUILTIN_MINPS128_MASK,
> + IX86_BUILTIN_MAXPS128_MASK,
> + IX86_BUILTIN_MINPD128_MASK,
> + IX86_BUILTIN_MAXPD128_MASK,
> + IX86_BUILTIN_MAXPD256_MASK,
> + IX86_BUILTIN_MAXPS256_MASK,
> + IX86_BUILTIN_MINPD256_MASK,
> + IX86_BUILTIN_MINPS256_MASK,
> + IX86_BUILTIN_MULPS128_MASK,
> + IX86_BUILTIN_DIVPS128_MASK,
> + IX86_BUILTIN_MULPD128_MASK,
> + IX86_BUILTIN_DIVPD128_MASK,
> + IX86_BUILTIN_DIVPD256_MASK,
> + IX86_BUILTIN_DIVPS256_MASK,
> + IX86_BUILTIN_MULPD256_MASK,
> + IX86_BUILTIN_MULPS256_MASK,
> + IX86_BUILTIN_ADDPD128_MASK,
> + IX86_BUILTIN_ADDPD256_MASK,
> + IX86_BUILTIN_ADDPS128_MASK,
> + IX86_BUILTIN_ADDPS256_MASK,
> + IX86_BUILTIN_SUBPD128_MASK,
> + IX86_BUILTIN_SUBPD256_MASK,
> + IX86_BUILTIN_SUBPS128_MASK,
> + IX86_BUILTIN_SUBPS256_MASK,
> + IX86_BUILTIN_XORPD256_MASK,
> + IX86_BUILTIN_XORPD128_MASK,
> + IX86_BUILTIN_XORPS256_MASK,
> + IX86_BUILTIN_XORPS128_MASK,
> + IX86_BUILTIN_ORPD256_MASK,
> + IX86_BUILTIN_ORPD128_MASK,
> + IX86_BUILTIN_ORPS256_MASK,
> + IX86_BUILTIN_ORPS128_MASK,
> + IX86_BUILTIN_BROADCASTF32x2_256,
> + IX86_BUILTIN_BROADCASTI32x2_256,
> + IX86_BUILTIN_BROADCASTI32x2_128,
> + IX86_BUILTIN_BROADCASTF64X2_256,
> + IX86_BUILTIN_BROADCASTI64X2_256,
> + IX86_BUILTIN_BROADCASTF32X4_256,
> + IX86_BUILTIN_BROADCASTI32X4_256,
> + IX86_BUILTIN_EXTRACTF32X4_256,
> + IX86_BUILTIN_EXTRACTI32X4_256,
> + IX86_BUILTIN_DBPSADBW256,
> + IX86_BUILTIN_DBPSADBW128,
> + IX86_BUILTIN_CVTTPD2QQ256,
> + IX86_BUILTIN_CVTTPD2QQ128,
> + IX86_BUILTIN_CVTTPD2UQQ256,
> + IX86_BUILTIN_CVTTPD2UQQ128,
> + IX86_BUILTIN_CVTPD2QQ256,
> + IX86_BUILTIN_CVTPD2QQ128,
> + IX86_BUILTIN_CVTPD2UQQ256,
> + IX86_BUILTIN_CVTPD2UQQ128,
> + IX86_BUILTIN_CVTPD2UDQ256_MASK,
> + IX86_BUILTIN_CVTPD2UDQ128_MASK,
> + IX86_BUILTIN_CVTTPS2QQ256,
> + IX86_BUILTIN_CVTTPS2QQ128,
> + IX86_BUILTIN_CVTTPS2UQQ256,
> + IX86_BUILTIN_CVTTPS2UQQ128,
> + IX86_BUILTIN_CVTTPS2DQ256_MASK,
> + IX86_BUILTIN_CVTTPS2DQ128_MASK,
> + IX86_BUILTIN_CVTTPS2UDQ256,
> + IX86_BUILTIN_CVTTPS2UDQ128,
> + IX86_BUILTIN_CVTTPD2DQ256_MASK,
> + IX86_BUILTIN_CVTTPD2DQ128_MASK,
> + IX86_BUILTIN_CVTTPD2UDQ256_MASK,
> + IX86_BUILTIN_CVTTPD2UDQ128_MASK,
> + IX86_BUILTIN_CVTPD2DQ256_MASK,
> + IX86_BUILTIN_CVTPD2DQ128_MASK,
> + IX86_BUILTIN_CVTDQ2PD256_MASK,
> + IX86_BUILTIN_CVTDQ2PD128_MASK,
> + IX86_BUILTIN_CVTUDQ2PD256_MASK,
> + IX86_BUILTIN_CVTUDQ2PD128_MASK,
> + IX86_BUILTIN_CVTDQ2PS256_MASK,
> + IX86_BUILTIN_CVTDQ2PS128_MASK,
> + IX86_BUILTIN_CVTUDQ2PS256_MASK,
> + IX86_BUILTIN_CVTUDQ2PS128_MASK,
> + IX86_BUILTIN_CVTPS2PD256_MASK,
> + IX86_BUILTIN_CVTPS2PD128_MASK,
> + IX86_BUILTIN_PBROADCASTB256_MASK,
> + IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
> + IX86_BUILTIN_PBROADCASTB128_MASK,
> + IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
> + IX86_BUILTIN_PBROADCASTW256_MASK,
> + IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
> + IX86_BUILTIN_PBROADCASTW128_MASK,
> + IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
> + IX86_BUILTIN_PBROADCASTD256_MASK,
> + IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
> + IX86_BUILTIN_PBROADCASTD128_MASK,
> + IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
> + IX86_BUILTIN_PBROADCASTQ256_MASK,
> + IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
> + IX86_BUILTIN_PBROADCASTQ256_MEM_MASK,
> + IX86_BUILTIN_PBROADCASTQ128_MASK,
> + IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
> + IX86_BUILTIN_PBROADCASTQ128_MEM_MASK,
> + IX86_BUILTIN_BROADCASTSS256,
> + IX86_BUILTIN_BROADCASTSS128,
> + IX86_BUILTIN_BROADCASTSD256,
> + IX86_BUILTIN_EXTRACTF64X2_256,
> + IX86_BUILTIN_EXTRACTI64X2_256,
> + IX86_BUILTIN_INSERTF32X4_256,
> + IX86_BUILTIN_INSERTI32X4_256,
> + IX86_BUILTIN_PMOVSXBW256_MASK,
> + IX86_BUILTIN_PMOVSXBW128_MASK,
> + IX86_BUILTIN_PMOVSXBD256_MASK,
> + IX86_BUILTIN_PMOVSXBD128_MASK,
> + IX86_BUILTIN_PMOVSXBQ256_MASK,
> + IX86_BUILTIN_PMOVSXBQ128_MASK,
> + IX86_BUILTIN_PMOVSXWD256_MASK,
> + IX86_BUILTIN_PMOVSXWD128_MASK,
> + IX86_BUILTIN_PMOVSXWQ256_MASK,
> + IX86_BUILTIN_PMOVSXWQ128_MASK,
> + IX86_BUILTIN_PMOVSXDQ256_MASK,
> + IX86_BUILTIN_PMOVSXDQ128_MASK,
> + IX86_BUILTIN_PMOVZXBW256_MASK,
> + IX86_BUILTIN_PMOVZXBW128_MASK,
> + IX86_BUILTIN_PMOVZXBD256_MASK,
> + IX86_BUILTIN_PMOVZXBD128_MASK,
> + IX86_BUILTIN_PMOVZXBQ256_MASK,
> + IX86_BUILTIN_PMOVZXBQ128_MASK,
> + IX86_BUILTIN_PMOVZXWD256_MASK,
> + IX86_BUILTIN_PMOVZXWD128_MASK,
> + IX86_BUILTIN_PMOVZXWQ256_MASK,
> + IX86_BUILTIN_PMOVZXWQ128_MASK,
> + IX86_BUILTIN_PMOVZXDQ256_MASK,
> + IX86_BUILTIN_PMOVZXDQ128_MASK,
> + IX86_BUILTIN_REDUCEPD256_MASK,
> + IX86_BUILTIN_REDUCEPD128_MASK,
> + IX86_BUILTIN_REDUCEPS256_MASK,
> + IX86_BUILTIN_REDUCEPS128_MASK,
> + IX86_BUILTIN_REDUCESD_MASK,
> + IX86_BUILTIN_REDUCESS_MASK,
> + IX86_BUILTIN_VPERMVARHI256_MASK,
> + IX86_BUILTIN_VPERMVARHI128_MASK,
> + IX86_BUILTIN_VPERMT2VARHI256,
> + IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
> + IX86_BUILTIN_VPERMT2VARHI128,
> + IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
> + IX86_BUILTIN_VPERMI2VARHI256,
> + IX86_BUILTIN_VPERMI2VARHI128,
> + IX86_BUILTIN_RCP14PD256,
> + IX86_BUILTIN_RCP14PD128,
> + IX86_BUILTIN_RCP14PS256,
> + IX86_BUILTIN_RCP14PS128,
> + IX86_BUILTIN_RSQRT14PD256_MASK,
> + IX86_BUILTIN_RSQRT14PD128_MASK,
> + IX86_BUILTIN_RSQRT14PS256_MASK,
> + IX86_BUILTIN_RSQRT14PS128_MASK,
> + IX86_BUILTIN_SQRTPD256_MASK,
> + IX86_BUILTIN_SQRTPD128_MASK,
> + IX86_BUILTIN_SQRTPS256_MASK,
> + IX86_BUILTIN_SQRTPS128_MASK,
> + IX86_BUILTIN_PADDB128_MASK,
> + IX86_BUILTIN_PADDW128_MASK,
> + IX86_BUILTIN_PADDD128_MASK,
> + IX86_BUILTIN_PADDQ128_MASK,
> + IX86_BUILTIN_PSUBB128_MASK,
> + IX86_BUILTIN_PSUBW128_MASK,
> + IX86_BUILTIN_PSUBD128_MASK,
> + IX86_BUILTIN_PSUBQ128_MASK,
> + IX86_BUILTIN_PADDSB128_MASK,
> + IX86_BUILTIN_PADDSW128_MASK,
> + IX86_BUILTIN_PSUBSB128_MASK,
> + IX86_BUILTIN_PSUBSW128_MASK,
> + IX86_BUILTIN_PADDUSB128_MASK,
> + IX86_BUILTIN_PADDUSW128_MASK,
> + IX86_BUILTIN_PSUBUSB128_MASK,
> + IX86_BUILTIN_PSUBUSW128_MASK,
> + IX86_BUILTIN_PADDB256_MASK,
> + IX86_BUILTIN_PADDW256_MASK,
> + IX86_BUILTIN_PADDD256_MASK,
> + IX86_BUILTIN_PADDQ256_MASK,
> + IX86_BUILTIN_PADDSB256_MASK,
> + IX86_BUILTIN_PADDSW256_MASK,
> + IX86_BUILTIN_PADDUSB256_MASK,
> + IX86_BUILTIN_PADDUSW256_MASK,
> + IX86_BUILTIN_PSUBB256_MASK,
> + IX86_BUILTIN_PSUBW256_MASK,
> + IX86_BUILTIN_PSUBD256_MASK,
> + IX86_BUILTIN_PSUBQ256_MASK,
> + IX86_BUILTIN_PSUBSB256_MASK,
> + IX86_BUILTIN_PSUBSW256_MASK,
> + IX86_BUILTIN_PSUBUSB256_MASK,
> + IX86_BUILTIN_PSUBUSW256_MASK,
> + IX86_BUILTIN_SHUF_F64x2_256,
> + IX86_BUILTIN_SHUF_I64x2_256,
> + IX86_BUILTIN_SHUF_I32x4_256,
> + IX86_BUILTIN_SHUF_F32x4_256,
> + IX86_BUILTIN_PMOVWB128,
> + IX86_BUILTIN_PMOVWB256,
> + IX86_BUILTIN_PMOVSWB128,
> + IX86_BUILTIN_PMOVSWB256,
> + IX86_BUILTIN_PMOVUSWB128,
> + IX86_BUILTIN_PMOVUSWB256,
> + IX86_BUILTIN_PMOVDB128,
> + IX86_BUILTIN_PMOVDB256,
> + IX86_BUILTIN_PMOVSDB128,
> + IX86_BUILTIN_PMOVSDB256,
> + IX86_BUILTIN_PMOVUSDB128,
> + IX86_BUILTIN_PMOVUSDB256,
> + IX86_BUILTIN_PMOVDW128,
> + IX86_BUILTIN_PMOVDW256,
> + IX86_BUILTIN_PMOVSDW128,
> + IX86_BUILTIN_PMOVSDW256,
> + IX86_BUILTIN_PMOVUSDW128,
> + IX86_BUILTIN_PMOVUSDW256,
> + IX86_BUILTIN_PMOVQB128,
> + IX86_BUILTIN_PMOVQB256,
> + IX86_BUILTIN_PMOVSQB128,
> + IX86_BUILTIN_PMOVSQB256,
> + IX86_BUILTIN_PMOVUSQB128,
> + IX86_BUILTIN_PMOVUSQB256,
> + IX86_BUILTIN_PMOVQW128,
> + IX86_BUILTIN_PMOVQW256,
> + IX86_BUILTIN_PMOVSQW128,
> + IX86_BUILTIN_PMOVSQW256,
> + IX86_BUILTIN_PMOVUSQW128,
> + IX86_BUILTIN_PMOVUSQW256,
> + IX86_BUILTIN_PMOVQD128,
> + IX86_BUILTIN_PMOVQD256,
> + IX86_BUILTIN_PMOVSQD128,
> + IX86_BUILTIN_PMOVSQD256,
> + IX86_BUILTIN_PMOVUSQD128,
> + IX86_BUILTIN_PMOVUSQD256,
> + IX86_BUILTIN_RANGEPD256,
> + IX86_BUILTIN_RANGEPD128,
> + IX86_BUILTIN_RANGEPS256,
> + IX86_BUILTIN_RANGEPS128,
> + IX86_BUILTIN_GETEXPPS256,
> + IX86_BUILTIN_GETEXPPD256,
> + IX86_BUILTIN_GETEXPPS128,
> + IX86_BUILTIN_GETEXPPD128,
> + IX86_BUILTIN_FIXUPIMMPD256_MASK,
> + IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
> + IX86_BUILTIN_FIXUPIMMPS256_MASK,
> + IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
> + IX86_BUILTIN_FIXUPIMMPD128_MASK,
> + IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
> + IX86_BUILTIN_FIXUPIMMPS128_MASK,
> + IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
> + IX86_BUILTIN_PABSQ256,
> + IX86_BUILTIN_PABSQ128,
> + IX86_BUILTIN_PABSD256_MASK,
> + IX86_BUILTIN_PABSD128_MASK,
> + IX86_BUILTIN_PMULHRSW256_MASK,
> + IX86_BUILTIN_PMULHRSW128_MASK,
> + IX86_BUILTIN_PMULHUW128_MASK,
> + IX86_BUILTIN_PMULHUW256_MASK,
> + IX86_BUILTIN_PMULHW256_MASK,
> + IX86_BUILTIN_PMULHW128_MASK,
> + IX86_BUILTIN_PMULLW256_MASK,
> + IX86_BUILTIN_PMULLW128_MASK,
> + IX86_BUILTIN_PMULLQ256,
> + IX86_BUILTIN_PMULLQ128,
> + IX86_BUILTIN_ANDPD256_MASK,
> + IX86_BUILTIN_ANDPD128_MASK,
> + IX86_BUILTIN_ANDPS256_MASK,
> + IX86_BUILTIN_ANDPS128_MASK,
> + IX86_BUILTIN_ANDNPD256_MASK,
> + IX86_BUILTIN_ANDNPD128_MASK,
> + IX86_BUILTIN_ANDNPS256_MASK,
> + IX86_BUILTIN_ANDNPS128_MASK,
> + IX86_BUILTIN_PSLLWI128_MASK,
> + IX86_BUILTIN_PSLLDI128_MASK,
> + IX86_BUILTIN_PSLLQI128_MASK,
> + IX86_BUILTIN_PSLLW128_MASK,
> + IX86_BUILTIN_PSLLD128_MASK,
> + IX86_BUILTIN_PSLLQ128_MASK,
> + IX86_BUILTIN_PSLLWI256_MASK ,
> + IX86_BUILTIN_PSLLW256_MASK,
> + IX86_BUILTIN_PSLLDI256_MASK,
> + IX86_BUILTIN_PSLLD256_MASK,
> + IX86_BUILTIN_PSLLQI256_MASK,
> + IX86_BUILTIN_PSLLQ256_MASK,
> + IX86_BUILTIN_PSRADI128_MASK,
> + IX86_BUILTIN_PSRAD128_MASK,
> + IX86_BUILTIN_PSRADI256_MASK,
> + IX86_BUILTIN_PSRAD256_MASK,
> + IX86_BUILTIN_PSRAQI128_MASK,
> + IX86_BUILTIN_PSRAQ128_MASK,
> + IX86_BUILTIN_PSRAQI256_MASK,
> + IX86_BUILTIN_PSRAQ256_MASK,
> + IX86_BUILTIN_PANDD256,
> + IX86_BUILTIN_PANDD128,
> + IX86_BUILTIN_PSRLDI128_MASK,
> + IX86_BUILTIN_PSRLD128_MASK,
> + IX86_BUILTIN_PSRLDI256_MASK,
> + IX86_BUILTIN_PSRLD256_MASK,
> + IX86_BUILTIN_PSRLQI128_MASK,
> + IX86_BUILTIN_PSRLQ128_MASK,
> + IX86_BUILTIN_PSRLQI256_MASK,
> + IX86_BUILTIN_PSRLQ256_MASK,
> + IX86_BUILTIN_PANDQ256,
> + IX86_BUILTIN_PANDQ128,
> + IX86_BUILTIN_PANDND256,
> + IX86_BUILTIN_PANDND128,
> + IX86_BUILTIN_PANDNQ256,
> + IX86_BUILTIN_PANDNQ128,
> + IX86_BUILTIN_PORD256,
> + IX86_BUILTIN_PORD128,
> + IX86_BUILTIN_PORQ256,
> + IX86_BUILTIN_PORQ128,
> + IX86_BUILTIN_PXORD256,
> + IX86_BUILTIN_PXORD128,
> + IX86_BUILTIN_PXORQ256,
> + IX86_BUILTIN_PXORQ128,
> + IX86_BUILTIN_PACKSSWB256_MASK,
> + IX86_BUILTIN_PACKSSWB128_MASK,
> + IX86_BUILTIN_PACKUSWB256_MASK,
> + IX86_BUILTIN_PACKUSWB128_MASK,
> + IX86_BUILTIN_RNDSCALEPS256,
> + IX86_BUILTIN_RNDSCALEPD256,
> + IX86_BUILTIN_RNDSCALEPS128,
> + IX86_BUILTIN_RNDSCALEPD128,
> + IX86_BUILTIN_VTERNLOGQ256_MASK,
> + IX86_BUILTIN_VTERNLOGQ256_MASKZ,
> + IX86_BUILTIN_VTERNLOGD256_MASK,
> + IX86_BUILTIN_VTERNLOGD256_MASKZ,
> + IX86_BUILTIN_VTERNLOGQ128_MASK,
> + IX86_BUILTIN_VTERNLOGQ128_MASKZ,
> + IX86_BUILTIN_VTERNLOGD128_MASK,
> + IX86_BUILTIN_VTERNLOGD128_MASKZ,
> + IX86_BUILTIN_SCALEFPD256,
> + IX86_BUILTIN_SCALEFPS256,
> + IX86_BUILTIN_SCALEFPD128,
> + IX86_BUILTIN_SCALEFPS128,
> + IX86_BUILTIN_VFMADDPD256_MASK,
> + IX86_BUILTIN_VFMADDPD256_MASK3,
> + IX86_BUILTIN_VFMADDPD256_MASKZ,
> + IX86_BUILTIN_VFMADDPD128_MASK,
> + IX86_BUILTIN_VFMADDPD128_MASK3,
> + IX86_BUILTIN_VFMADDPD128_MASKZ,
> + IX86_BUILTIN_VFMADDPS256_MASK,
> + IX86_BUILTIN_VFMADDPS256_MASK3,
> + IX86_BUILTIN_VFMADDPS256_MASKZ,
> + IX86_BUILTIN_VFMADDPS128_MASK,
> + IX86_BUILTIN_VFMADDPS128_MASK3,
> + IX86_BUILTIN_VFMADDPS128_MASKZ,
> + IX86_BUILTIN_VFMSUBPD256_MASK3,
> + IX86_BUILTIN_VFMSUBPD128_MASK3,
> + IX86_BUILTIN_VFMSUBPS256_MASK3,
> + IX86_BUILTIN_VFMSUBPS128_MASK3,
> + IX86_BUILTIN_VFNMADDPD256_MASK,
> + IX86_BUILTIN_VFNMADDPD128_MASK,
> + IX86_BUILTIN_VFNMADDPS256_MASK,
> + IX86_BUILTIN_VFNMADDPS128_MASK,
> + IX86_BUILTIN_VFNMSUBPD256_MASK,
> + IX86_BUILTIN_VFNMSUBPD256_MASK3,
> + IX86_BUILTIN_VFNMSUBPD128_MASK,
> + IX86_BUILTIN_VFNMSUBPD128_MASK3,
> + IX86_BUILTIN_VFNMSUBPS256_MASK,
> + IX86_BUILTIN_VFNMSUBPS256_MASK3,
> + IX86_BUILTIN_VFNMSUBPS128_MASK,
> + IX86_BUILTIN_VFNMSUBPS128_MASK3,
> + IX86_BUILTIN_VFMADDSUBPD256_MASK,
> + IX86_BUILTIN_VFMADDSUBPD256_MASK3,
> + IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
> + IX86_BUILTIN_VFMADDSUBPD128_MASK,
> + IX86_BUILTIN_VFMADDSUBPD128_MASK3,
> + IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
> + IX86_BUILTIN_VFMADDSUBPS256_MASK,
> + IX86_BUILTIN_VFMADDSUBPS256_MASK3,
> + IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
> + IX86_BUILTIN_VFMADDSUBPS128_MASK,
> + IX86_BUILTIN_VFMADDSUBPS128_MASK3,
> + IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
> + IX86_BUILTIN_VFMSUBADDPD256_MASK3,
> + IX86_BUILTIN_VFMSUBADDPD128_MASK3,
> + IX86_BUILTIN_VFMSUBADDPS256_MASK3,
> + IX86_BUILTIN_VFMSUBADDPS128_MASK3,
> + IX86_BUILTIN_INSERTF64X2_256,
> + IX86_BUILTIN_INSERTI64X2_256,
> + IX86_BUILTIN_PSRAVV16HI,
> + IX86_BUILTIN_PSRAVV8HI,
> + IX86_BUILTIN_PMADDUBSW256_MASK,
> + IX86_BUILTIN_PMADDUBSW128_MASK,
> + IX86_BUILTIN_PMADDWD256_MASK,
> + IX86_BUILTIN_PMADDWD128_MASK,
> + IX86_BUILTIN_PSRLVV16HI,
> + IX86_BUILTIN_PSRLVV8HI,
> + IX86_BUILTIN_CVTPS2DQ256_MASK,
> + IX86_BUILTIN_CVTPS2DQ128_MASK,
> + IX86_BUILTIN_CVTPS2UDQ256,
> + IX86_BUILTIN_CVTPS2UDQ128,
> + IX86_BUILTIN_CVTPS2QQ256,
> + IX86_BUILTIN_CVTPS2QQ128,
> + IX86_BUILTIN_CVTPS2UQQ256,
> + IX86_BUILTIN_CVTPS2UQQ128,
> + IX86_BUILTIN_GETMANTPS256,
> + IX86_BUILTIN_GETMANTPS128,
> + IX86_BUILTIN_GETMANTPD256,
> + IX86_BUILTIN_GETMANTPD128,
> + IX86_BUILTIN_MOVDDUP256_MASK,
> + IX86_BUILTIN_MOVDDUP128_MASK,
> + IX86_BUILTIN_MOVSHDUP256_MASK,
> + IX86_BUILTIN_MOVSHDUP128_MASK,
> + IX86_BUILTIN_MOVSLDUP256_MASK,
> + IX86_BUILTIN_MOVSLDUP128_MASK,
> + IX86_BUILTIN_CVTQQ2PS256,
> + IX86_BUILTIN_CVTQQ2PS128,
> + IX86_BUILTIN_CVTUQQ2PS256,
> + IX86_BUILTIN_CVTUQQ2PS128,
> + IX86_BUILTIN_CVTQQ2PD256,
> + IX86_BUILTIN_CVTQQ2PD128,
> + IX86_BUILTIN_CVTUQQ2PD256,
> + IX86_BUILTIN_CVTUQQ2PD128,
> + IX86_BUILTIN_VPERMT2VARQ256,
> + IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
> + IX86_BUILTIN_VPERMT2VARD256,
> + IX86_BUILTIN_VPERMT2VARD256_MASKZ,
> + IX86_BUILTIN_VPERMI2VARQ256,
> + IX86_BUILTIN_VPERMI2VARD256,
> + IX86_BUILTIN_VPERMT2VARPD256,
> + IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
> + IX86_BUILTIN_VPERMT2VARPS256,
> + IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
> + IX86_BUILTIN_VPERMI2VARPD256,
> + IX86_BUILTIN_VPERMI2VARPS256,
> + IX86_BUILTIN_VPERMT2VARQ128,
> + IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
> + IX86_BUILTIN_VPERMT2VARD128,
> + IX86_BUILTIN_VPERMT2VARD128_MASKZ,
> + IX86_BUILTIN_VPERMI2VARQ128,
> + IX86_BUILTIN_VPERMI2VARD128,
> + IX86_BUILTIN_VPERMT2VARPD128,
> + IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
> + IX86_BUILTIN_VPERMT2VARPS128,
> + IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
> + IX86_BUILTIN_VPERMI2VARPD128,
> + IX86_BUILTIN_VPERMI2VARPS128,
> + IX86_BUILTIN_PSHUFB256_MASK,
> + IX86_BUILTIN_PSHUFB128_MASK,
> + IX86_BUILTIN_PSHUFHW256_MASK,
> + IX86_BUILTIN_PSHUFHW128_MASK,
> + IX86_BUILTIN_PSHUFLW256_MASK,
> + IX86_BUILTIN_PSHUFLW128_MASK,
> + IX86_BUILTIN_PSHUFD256_MASK,
> + IX86_BUILTIN_PSHUFD128_MASK,
> + IX86_BUILTIN_SHUFPD256_MASK,
> + IX86_BUILTIN_SHUFPD128_MASK,
> + IX86_BUILTIN_SHUFPS256_MASK,
> + IX86_BUILTIN_SHUFPS128_MASK,
> + IX86_BUILTIN_PROLVQ256,
> + IX86_BUILTIN_PROLVQ128,
> + IX86_BUILTIN_PROLQ256,
> + IX86_BUILTIN_PROLQ128,
> + IX86_BUILTIN_PRORVQ256,
> + IX86_BUILTIN_PRORVQ128,
> + IX86_BUILTIN_PRORQ256,
> + IX86_BUILTIN_PRORQ128,
> + IX86_BUILTIN_PSRAVQ128,
> + IX86_BUILTIN_PSRAVQ256,
> + IX86_BUILTIN_PSLLVV4DI_MASK,
> + IX86_BUILTIN_PSLLVV2DI_MASK,
> + IX86_BUILTIN_PSLLVV8SI_MASK,
> + IX86_BUILTIN_PSLLVV4SI_MASK,
> + IX86_BUILTIN_PSRAVV8SI_MASK,
> + IX86_BUILTIN_PSRAVV4SI_MASK,
> + IX86_BUILTIN_PSRLVV4DI_MASK,
> + IX86_BUILTIN_PSRLVV2DI_MASK,
> + IX86_BUILTIN_PSRLVV8SI_MASK,
> + IX86_BUILTIN_PSRLVV4SI_MASK,
> + IX86_BUILTIN_PSRAWI256_MASK,
> + IX86_BUILTIN_PSRAW256_MASK,
> + IX86_BUILTIN_PSRAWI128_MASK,
> + IX86_BUILTIN_PSRAW128_MASK,
> + IX86_BUILTIN_PSRLWI256_MASK,
> + IX86_BUILTIN_PSRLW256_MASK,
> + IX86_BUILTIN_PSRLWI128_MASK,
> + IX86_BUILTIN_PSRLW128_MASK,
> + IX86_BUILTIN_PRORVD256,
> + IX86_BUILTIN_PROLVD256,
> + IX86_BUILTIN_PRORD256,
> + IX86_BUILTIN_PROLD256,
> + IX86_BUILTIN_PRORVD128,
> + IX86_BUILTIN_PROLVD128,
> + IX86_BUILTIN_PRORD128,
> + IX86_BUILTIN_PROLD128,
> + IX86_BUILTIN_FPCLASSPD256,
> + IX86_BUILTIN_FPCLASSPD128,
> + IX86_BUILTIN_FPCLASSSD,
> + IX86_BUILTIN_FPCLASSPS256,
> + IX86_BUILTIN_FPCLASSPS128,
> + IX86_BUILTIN_FPCLASSSS,
> + IX86_BUILTIN_CVTB2MASK128,
> + IX86_BUILTIN_CVTB2MASK256,
> + IX86_BUILTIN_CVTW2MASK128,
> + IX86_BUILTIN_CVTW2MASK256,
> + IX86_BUILTIN_CVTD2MASK128,
> + IX86_BUILTIN_CVTD2MASK256,
> + IX86_BUILTIN_CVTQ2MASK128,
> + IX86_BUILTIN_CVTQ2MASK256,
> + IX86_BUILTIN_CVTMASK2B128,
> + IX86_BUILTIN_CVTMASK2B256,
> + IX86_BUILTIN_CVTMASK2W128,
> + IX86_BUILTIN_CVTMASK2W256,
> + IX86_BUILTIN_CVTMASK2D128,
> + IX86_BUILTIN_CVTMASK2D256,
> + IX86_BUILTIN_CVTMASK2Q128,
> + IX86_BUILTIN_CVTMASK2Q256,
> + IX86_BUILTIN_PCMPEQB128_MASK,
> + IX86_BUILTIN_PCMPEQB256_MASK,
> + IX86_BUILTIN_PCMPEQW128_MASK,
> + IX86_BUILTIN_PCMPEQW256_MASK,
> + IX86_BUILTIN_PCMPEQD128_MASK,
> + IX86_BUILTIN_PCMPEQD256_MASK,
> + IX86_BUILTIN_PCMPEQQ128_MASK,
> + IX86_BUILTIN_PCMPEQQ256_MASK,
> + IX86_BUILTIN_PCMPGTB128_MASK,
> + IX86_BUILTIN_PCMPGTB256_MASK,
> + IX86_BUILTIN_PCMPGTW128_MASK,
> + IX86_BUILTIN_PCMPGTW256_MASK,
> + IX86_BUILTIN_PCMPGTD128_MASK,
> + IX86_BUILTIN_PCMPGTD256_MASK,
> + IX86_BUILTIN_PCMPGTQ128_MASK,
> + IX86_BUILTIN_PCMPGTQ256_MASK,
> + IX86_BUILTIN_PTESTMB128,
> + IX86_BUILTIN_PTESTMB256,
> + IX86_BUILTIN_PTESTMW128,
> + IX86_BUILTIN_PTESTMW256,
> + IX86_BUILTIN_PTESTMD128,
> + IX86_BUILTIN_PTESTMD256,
> + IX86_BUILTIN_PTESTMQ128,
> + IX86_BUILTIN_PTESTMQ256,
> + IX86_BUILTIN_PTESTNMB128,
> + IX86_BUILTIN_PTESTNMB256,
> + IX86_BUILTIN_PTESTNMW128,
> + IX86_BUILTIN_PTESTNMW256,
> + IX86_BUILTIN_PTESTNMD128,
> + IX86_BUILTIN_PTESTNMD256,
> + IX86_BUILTIN_PTESTNMQ128,
> + IX86_BUILTIN_PTESTNMQ256,
> + IX86_BUILTIN_PBROADCASTMB128,
> + IX86_BUILTIN_PBROADCASTMB256,
> + IX86_BUILTIN_PBROADCASTMW128,
> + IX86_BUILTIN_PBROADCASTMW256,
> + IX86_BUILTIN_COMPRESSPD256,
> + IX86_BUILTIN_COMPRESSPD128,
> + IX86_BUILTIN_COMPRESSPS256,
> + IX86_BUILTIN_COMPRESSPS128,
> + IX86_BUILTIN_PCOMPRESSQ256,
> + IX86_BUILTIN_PCOMPRESSQ128,
> + IX86_BUILTIN_PCOMPRESSD256,
> + IX86_BUILTIN_PCOMPRESSD128,
> + IX86_BUILTIN_EXPANDPD256,
> + IX86_BUILTIN_EXPANDPD128,
> + IX86_BUILTIN_EXPANDPS256,
> + IX86_BUILTIN_EXPANDPS128,
> + IX86_BUILTIN_PEXPANDQ256,
> + IX86_BUILTIN_PEXPANDQ128,
> + IX86_BUILTIN_PEXPANDD256,
> + IX86_BUILTIN_PEXPANDD128,
> + IX86_BUILTIN_EXPANDPD256Z,
> + IX86_BUILTIN_EXPANDPD128Z,
> + IX86_BUILTIN_EXPANDPS256Z,
> + IX86_BUILTIN_EXPANDPS128Z,
> + IX86_BUILTIN_PEXPANDQ256Z,
> + IX86_BUILTIN_PEXPANDQ128Z,
> + IX86_BUILTIN_PEXPANDD256Z,
> + IX86_BUILTIN_PEXPANDD128Z,
> + IX86_BUILTIN_PMAXSD256_MASK,
> + IX86_BUILTIN_PMINSD256_MASK,
> + IX86_BUILTIN_PMAXUD256_MASK,
> + IX86_BUILTIN_PMINUD256_MASK,
> + IX86_BUILTIN_PMAXSD128_MASK,
> + IX86_BUILTIN_PMINSD128_MASK,
> + IX86_BUILTIN_PMAXUD128_MASK,
> + IX86_BUILTIN_PMINUD128_MASK,
> + IX86_BUILTIN_PMAXSQ256_MASK,
> + IX86_BUILTIN_PMINSQ256_MASK,
> + IX86_BUILTIN_PMAXUQ256_MASK,
> + IX86_BUILTIN_PMINUQ256_MASK,
> + IX86_BUILTIN_PMAXSQ128_MASK,
> + IX86_BUILTIN_PMINSQ128_MASK,
> + IX86_BUILTIN_PMAXUQ128_MASK,
> + IX86_BUILTIN_PMINUQ128_MASK,
> + IX86_BUILTIN_PMINSB256_MASK,
> + IX86_BUILTIN_PMINUB256_MASK,
> + IX86_BUILTIN_PMAXSB256_MASK,
> + IX86_BUILTIN_PMAXUB256_MASK,
> + IX86_BUILTIN_PMINSB128_MASK,
> + IX86_BUILTIN_PMINUB128_MASK,
> + IX86_BUILTIN_PMAXSB128_MASK,
> + IX86_BUILTIN_PMAXUB128_MASK,
> + IX86_BUILTIN_PMINSW256_MASK,
> + IX86_BUILTIN_PMINUW256_MASK,
> + IX86_BUILTIN_PMAXSW256_MASK,
> + IX86_BUILTIN_PMAXUW256_MASK,
> + IX86_BUILTIN_PMINSW128_MASK,
> + IX86_BUILTIN_PMINUW128_MASK,
> + IX86_BUILTIN_PMAXSW128_MASK,
> + IX86_BUILTIN_PMAXUW128_MASK,
> + IX86_BUILTIN_VPCONFLICTQ256,
> + IX86_BUILTIN_VPCONFLICTD256,
> + IX86_BUILTIN_VPCLZCNTQ256,
> + IX86_BUILTIN_VPCLZCNTD256,
> + IX86_BUILTIN_UNPCKHPD256_MASK,
> + IX86_BUILTIN_UNPCKHPD128_MASK,
> + IX86_BUILTIN_UNPCKHPS256_MASK,
> + IX86_BUILTIN_UNPCKHPS128_MASK,
> + IX86_BUILTIN_UNPCKLPD256_MASK,
> + IX86_BUILTIN_UNPCKLPD128_MASK,
> + IX86_BUILTIN_UNPCKLPS256_MASK,
> + IX86_BUILTIN_VPCONFLICTQ128,
> + IX86_BUILTIN_VPCONFLICTD128,
> + IX86_BUILTIN_VPCLZCNTQ128,
> + IX86_BUILTIN_VPCLZCNTD128,
> + IX86_BUILTIN_UNPCKLPS128_MASK,
> + IX86_BUILTIN_ALIGND256,
> + IX86_BUILTIN_ALIGNQ256,
> + IX86_BUILTIN_ALIGND128,
> + IX86_BUILTIN_ALIGNQ128,
> + IX86_BUILTIN_CVTPS2PH256_MASK,
> + IX86_BUILTIN_CVTPS2PH_MASK,
> + IX86_BUILTIN_CVTPH2PS_MASK,
> + IX86_BUILTIN_CVTPH2PS256_MASK,
> + IX86_BUILTIN_PUNPCKHDQ128_MASK,
> + IX86_BUILTIN_PUNPCKHDQ256_MASK,
> + IX86_BUILTIN_PUNPCKHQDQ128_MASK,
> + IX86_BUILTIN_PUNPCKHQDQ256_MASK,
> + IX86_BUILTIN_PUNPCKLDQ128_MASK,
> + IX86_BUILTIN_PUNPCKLDQ256_MASK,
> + IX86_BUILTIN_PUNPCKLQDQ128_MASK,
> + IX86_BUILTIN_PUNPCKLQDQ256_MASK,
> + IX86_BUILTIN_PUNPCKHBW128_MASK,
> + IX86_BUILTIN_PUNPCKHBW256_MASK,
> + IX86_BUILTIN_PUNPCKHWD128_MASK,
> + IX86_BUILTIN_PUNPCKHWD256_MASK,
> + IX86_BUILTIN_PUNPCKLBW128_MASK,
> + IX86_BUILTIN_PUNPCKLBW256_MASK,
> + IX86_BUILTIN_PUNPCKLWD128_MASK,
> + IX86_BUILTIN_PUNPCKLWD256_MASK,
> + IX86_BUILTIN_PSLLVV16HI,
> + IX86_BUILTIN_PSLLVV8HI,
> + IX86_BUILTIN_PACKSSDW256_MASK,
> + IX86_BUILTIN_PACKSSDW128_MASK,
> + IX86_BUILTIN_PACKUSDW256_MASK,
> + IX86_BUILTIN_PACKUSDW128_MASK,
> + IX86_BUILTIN_PAVGB256_MASK,
> + IX86_BUILTIN_PAVGW256_MASK,
> + IX86_BUILTIN_PAVGB128_MASK,
> + IX86_BUILTIN_PAVGW128_MASK,
> + IX86_BUILTIN_VPERMVARSF256_MASK,
> + IX86_BUILTIN_VPERMVARDF256_MASK,
> + IX86_BUILTIN_VPERMDF256_MASK,
> + IX86_BUILTIN_PABSB256_MASK,
> + IX86_BUILTIN_PABSB128_MASK,
> + IX86_BUILTIN_PABSW256_MASK,
> + IX86_BUILTIN_PABSW128_MASK,
> + IX86_BUILTIN_VPERMILVARPD_MASK,
> + IX86_BUILTIN_VPERMILVARPS_MASK,
> + IX86_BUILTIN_VPERMILVARPD256_MASK,
> + IX86_BUILTIN_VPERMILVARPS256_MASK,
> + IX86_BUILTIN_VPERMILPD_MASK,
> + IX86_BUILTIN_VPERMILPS_MASK,
> + IX86_BUILTIN_VPERMILPD256_MASK,
> + IX86_BUILTIN_VPERMILPS256_MASK,
> + IX86_BUILTIN_BLENDMQ256,
> + IX86_BUILTIN_BLENDMD256,
> + IX86_BUILTIN_BLENDMPD256,
> + IX86_BUILTIN_BLENDMPS256,
> + IX86_BUILTIN_BLENDMQ128,
> + IX86_BUILTIN_BLENDMD128,
> + IX86_BUILTIN_BLENDMPD128,
> + IX86_BUILTIN_BLENDMPS128,
> + IX86_BUILTIN_BLENDMW256,
> + IX86_BUILTIN_BLENDMB256,
> + IX86_BUILTIN_BLENDMW128,
> + IX86_BUILTIN_BLENDMB128,
> + IX86_BUILTIN_PMULLD256_MASK,
> + IX86_BUILTIN_PMULLD128_MASK,
> + IX86_BUILTIN_PMULUDQ256_MASK,
> + IX86_BUILTIN_PMULDQ256_MASK,
> + IX86_BUILTIN_PMULDQ128_MASK,
> + IX86_BUILTIN_PMULUDQ128_MASK,
> + IX86_BUILTIN_CVTPD2PS256_MASK,
> + IX86_BUILTIN_CVTPD2PS_MASK,
> + IX86_BUILTIN_VPERMVARSI256_MASK,
> + IX86_BUILTIN_VPERMVARDI256_MASK,
> + IX86_BUILTIN_VPERMDI256_MASK,
> + IX86_BUILTIN_CMPQ256,
> + IX86_BUILTIN_CMPD256,
> + IX86_BUILTIN_UCMPQ256,
> + IX86_BUILTIN_UCMPD256,
> + IX86_BUILTIN_CMPB256,
> + IX86_BUILTIN_CMPW256,
> + IX86_BUILTIN_UCMPB256,
> + IX86_BUILTIN_UCMPW256,
> + IX86_BUILTIN_CMPPD256_MASK,
> + IX86_BUILTIN_CMPPS256_MASK,
> + IX86_BUILTIN_CMPQ128,
> + IX86_BUILTIN_CMPD128,
> + IX86_BUILTIN_UCMPQ128,
> + IX86_BUILTIN_UCMPD128,
> + IX86_BUILTIN_CMPB128,
> + IX86_BUILTIN_CMPW128,
> + IX86_BUILTIN_UCMPB128,
> + IX86_BUILTIN_UCMPW128,
> + IX86_BUILTIN_CMPPD128_MASK,
> + IX86_BUILTIN_CMPPS128_MASK,
> +
> + IX86_BUILTIN_GATHER3SIV8SF,
> + IX86_BUILTIN_GATHER3SIV4SF,
> + IX86_BUILTIN_GATHER3SIV4DF,
> + IX86_BUILTIN_GATHER3SIV2DF,
> + IX86_BUILTIN_GATHER3DIV8SF,
> + IX86_BUILTIN_GATHER3DIV4SF,
> + IX86_BUILTIN_GATHER3DIV4DF,
> + IX86_BUILTIN_GATHER3DIV2DF,
> + IX86_BUILTIN_GATHER3SIV8SI,
> + IX86_BUILTIN_GATHER3SIV4SI,
> + IX86_BUILTIN_GATHER3SIV4DI,
> + IX86_BUILTIN_GATHER3SIV2DI,
> + IX86_BUILTIN_GATHER3DIV8SI,
> + IX86_BUILTIN_GATHER3DIV4SI,
> + IX86_BUILTIN_GATHER3DIV4DI,
> + IX86_BUILTIN_GATHER3DIV2DI,
> + IX86_BUILTIN_SCATTERSIV8SF,
> + IX86_BUILTIN_SCATTERSIV4SF,
> + IX86_BUILTIN_SCATTERSIV4DF,
> + IX86_BUILTIN_SCATTERSIV2DF,
> + IX86_BUILTIN_SCATTERDIV8SF,
> + IX86_BUILTIN_SCATTERDIV4SF,
> + IX86_BUILTIN_SCATTERDIV4DF,
> + IX86_BUILTIN_SCATTERDIV2DF,
> + IX86_BUILTIN_SCATTERSIV8SI,
> + IX86_BUILTIN_SCATTERSIV4SI,
> + IX86_BUILTIN_SCATTERSIV4DI,
> + IX86_BUILTIN_SCATTERSIV2DI,
> + IX86_BUILTIN_SCATTERDIV8SI,
> + IX86_BUILTIN_SCATTERDIV4SI,
> + IX86_BUILTIN_SCATTERDIV4DI,
> + IX86_BUILTIN_SCATTERDIV2DI,
> +
> + /* AVX512DQ. */
> + IX86_BUILTIN_RANGESD128,
> + IX86_BUILTIN_RANGESS128,
> + IX86_BUILTIN_KUNPCKWD,
> + IX86_BUILTIN_KUNPCKDQ,
> + IX86_BUILTIN_BROADCASTF32x2_512,
> + IX86_BUILTIN_BROADCASTI32x2_512,
> + IX86_BUILTIN_BROADCASTF64X2_512,
> + IX86_BUILTIN_BROADCASTI64X2_512,
> + IX86_BUILTIN_BROADCASTF32X8_512,
> + IX86_BUILTIN_BROADCASTI32X8_512,
> + IX86_BUILTIN_EXTRACTF64X2_512,
> + IX86_BUILTIN_EXTRACTF32X8,
> + IX86_BUILTIN_EXTRACTI64X2_512,
> + IX86_BUILTIN_EXTRACTI32X8,
> + IX86_BUILTIN_REDUCEPD512_MASK,
> + IX86_BUILTIN_REDUCEPS512_MASK,
> + IX86_BUILTIN_PMULLQ512,
> + IX86_BUILTIN_XORPD512,
> + IX86_BUILTIN_XORPS512,
> + IX86_BUILTIN_ORPD512,
> + IX86_BUILTIN_ORPS512,
> + IX86_BUILTIN_ANDPD512,
> + IX86_BUILTIN_ANDPS512,
> + IX86_BUILTIN_ANDNPD512,
> + IX86_BUILTIN_ANDNPS512,
> + IX86_BUILTIN_INSERTF32X8,
> + IX86_BUILTIN_INSERTI32X8,
> + IX86_BUILTIN_INSERTF64X2_512,
> + IX86_BUILTIN_INSERTI64X2_512,
> + IX86_BUILTIN_FPCLASSPD512,
> + IX86_BUILTIN_FPCLASSPS512,
> + IX86_BUILTIN_CVTD2MASK512,
> + IX86_BUILTIN_CVTQ2MASK512,
> + IX86_BUILTIN_CVTMASK2D512,
> + IX86_BUILTIN_CVTMASK2Q512,
> + IX86_BUILTIN_CVTPD2QQ512,
> + IX86_BUILTIN_CVTPS2QQ512,
> + IX86_BUILTIN_CVTPD2UQQ512,
> + IX86_BUILTIN_CVTPS2UQQ512,
> + IX86_BUILTIN_CVTQQ2PS512,
> + IX86_BUILTIN_CVTUQQ2PS512,
> + IX86_BUILTIN_CVTQQ2PD512,
> + IX86_BUILTIN_CVTUQQ2PD512,
> + IX86_BUILTIN_CVTTPS2QQ512,
> + IX86_BUILTIN_CVTTPS2UQQ512,
> + IX86_BUILTIN_CVTTPD2QQ512,
> + IX86_BUILTIN_CVTTPD2UQQ512,
> + IX86_BUILTIN_RANGEPS512,
> + IX86_BUILTIN_RANGEPD512,
> +
> + /* AVX512BW. */
> + IX86_BUILTIN_PACKUSDW512,
> + IX86_BUILTIN_PACKSSDW512,
> + IX86_BUILTIN_LOADDQUHI512_MASK,
> + IX86_BUILTIN_LOADDQUQI512_MASK,
> + IX86_BUILTIN_PSLLDQ512,
> + IX86_BUILTIN_PSRLDQ512,
> + IX86_BUILTIN_STOREDQUHI512_MASK,
> + IX86_BUILTIN_STOREDQUQI512_MASK,
> + IX86_BUILTIN_PALIGNR512,
> + IX86_BUILTIN_PALIGNR512_MASK,
> + IX86_BUILTIN_MOVDQUHI512_MASK,
> + IX86_BUILTIN_MOVDQUQI512_MASK,
> + IX86_BUILTIN_PSADBW512,
> + IX86_BUILTIN_DBPSADBW512,
> + IX86_BUILTIN_PBROADCASTB512,
> + IX86_BUILTIN_PBROADCASTB512_GPR,
> + IX86_BUILTIN_PBROADCASTW512,
> + IX86_BUILTIN_PBROADCASTW512_GPR,
> + IX86_BUILTIN_PMOVSXBW512_MASK,
> + IX86_BUILTIN_PMOVZXBW512_MASK,
> + IX86_BUILTIN_VPERMVARHI512_MASK,
> + IX86_BUILTIN_VPERMT2VARHI512,
> + IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
> + IX86_BUILTIN_VPERMI2VARHI512,
> + IX86_BUILTIN_PAVGB512,
> + IX86_BUILTIN_PAVGW512,
> + IX86_BUILTIN_PADDB512,
> + IX86_BUILTIN_PSUBB512,
> + IX86_BUILTIN_PSUBSB512,
> + IX86_BUILTIN_PADDSB512,
> + IX86_BUILTIN_PSUBUSB512,
> + IX86_BUILTIN_PADDUSB512,
> + IX86_BUILTIN_PSUBW512,
> + IX86_BUILTIN_PADDW512,
> + IX86_BUILTIN_PSUBSW512,
> + IX86_BUILTIN_PADDSW512,
> + IX86_BUILTIN_PSUBUSW512,
> + IX86_BUILTIN_PADDUSW512,
> + IX86_BUILTIN_PMAXUW512,
> + IX86_BUILTIN_PMAXSW512,
> + IX86_BUILTIN_PMINUW512,
> + IX86_BUILTIN_PMINSW512,
> + IX86_BUILTIN_PMAXUB512,
> + IX86_BUILTIN_PMAXSB512,
> + IX86_BUILTIN_PMINUB512,
> + IX86_BUILTIN_PMINSB512,
> + IX86_BUILTIN_PMOVWB512,
> + IX86_BUILTIN_PMOVSWB512,
> + IX86_BUILTIN_PMOVUSWB512,
> + IX86_BUILTIN_PMULHRSW512_MASK,
> + IX86_BUILTIN_PMULHUW512_MASK,
> + IX86_BUILTIN_PMULHW512_MASK,
> + IX86_BUILTIN_PMULLW512_MASK,
> + IX86_BUILTIN_PSLLWI512_MASK,
> + IX86_BUILTIN_PSLLW512_MASK,
> + IX86_BUILTIN_PACKSSWB512,
> + IX86_BUILTIN_PACKUSWB512,
> + IX86_BUILTIN_PSRAVV32HI,
> + IX86_BUILTIN_PMADDUBSW512_MASK,
> + IX86_BUILTIN_PMADDWD512_MASK,
> + IX86_BUILTIN_PSRLVV32HI,
> + IX86_BUILTIN_PUNPCKHBW512,
> + IX86_BUILTIN_PUNPCKHWD512,
> + IX86_BUILTIN_PUNPCKLBW512,
> + IX86_BUILTIN_PUNPCKLWD512,
> + IX86_BUILTIN_PSHUFB512,
> + IX86_BUILTIN_PSHUFHW512,
> + IX86_BUILTIN_PSHUFLW512,
> + IX86_BUILTIN_PSRAWI512,
> + IX86_BUILTIN_PSRAW512,
> + IX86_BUILTIN_PSRLWI512,
> + IX86_BUILTIN_PSRLW512,
> + IX86_BUILTIN_CVTB2MASK512,
> + IX86_BUILTIN_CVTW2MASK512,
> + IX86_BUILTIN_CVTMASK2B512,
> + IX86_BUILTIN_CVTMASK2W512,
> + IX86_BUILTIN_PCMPEQB512_MASK,
> + IX86_BUILTIN_PCMPEQW512_MASK,
> + IX86_BUILTIN_PCMPGTB512_MASK,
> + IX86_BUILTIN_PCMPGTW512_MASK,
> + IX86_BUILTIN_PTESTMB512,
> + IX86_BUILTIN_PTESTMW512,
> + IX86_BUILTIN_PTESTNMB512,
> + IX86_BUILTIN_PTESTNMW512,
> + IX86_BUILTIN_PSLLVV32HI,
> + IX86_BUILTIN_PABSB512,
> + IX86_BUILTIN_PABSW512,
> + IX86_BUILTIN_BLENDMW512,
> + IX86_BUILTIN_BLENDMB512,
> + IX86_BUILTIN_CMPB512,
> + IX86_BUILTIN_CMPW512,
> + IX86_BUILTIN_UCMPB512,
> + IX86_BUILTIN_UCMPW512,
> +
> /* Alternate 4 and 8 element gather/scatter for the vectorizer
> where all operands are 32-byte or 64-byte wide respectively. */
> IX86_BUILTIN_GATHERALTSIV4DF,
> @@ -29330,6 +30319,108 @@ static const struct builtin_description bdesc_special_args[] =
> { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
> { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
> { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
> +
> + /* AVX512BW */
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
> +
> + /* AVX512VL */
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
> };
>
> /* Builtins with variable number of arguments. */
> @@ -30389,6 +31480,848 @@ static const struct builtin_description bdesc_args[] =
> { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
> { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
> { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
> +
> + /* AVX512VL. */
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv4di_mask, "__builtin_ia32_pbroadcastq256_mem_mask", IX86_BUILTIN_PBROADCASTQ256_MEM_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv2di_mask, "__builtin_ia32_pbroadcastq128_mem_mask", IX86_BUILTIN_PBROADCASTQ128_MEM_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
> + { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
> + { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
> + { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
> + { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
> + { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
> + { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
> +
> + /* AVX512DQ. */
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
> +
> + /* AVX512BW. */
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
> + { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
> };
>
> /* Builtins with rounding support. */
> @@ -30526,6 +32459,24 @@ static const struct builtin_description bdesc_round_args[] =
> { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
> { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
> { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
> +
> + /* AVX512DQ. */
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
> + { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
> };
>
> /* FMA4 and XOP. */
> @@ -33803,6 +35754,28 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> case V4DI_FTYPE_V4SI:
> case V4DI_FTYPE_V2DI:
> case HI_FTYPE_HI:
> + case HI_FTYPE_V16QI:
> + case SI_FTYPE_V32QI:
> + case DI_FTYPE_V64QI:
> + case V16QI_FTYPE_HI:
> + case V32QI_FTYPE_SI:
> + case V64QI_FTYPE_DI:
> + case V8HI_FTYPE_QI:
> + case V16HI_FTYPE_HI:
> + case V32HI_FTYPE_SI:
> + case V4SI_FTYPE_QI:
> + case V8SI_FTYPE_QI:
> + case V4SI_FTYPE_HI:
> + case V8SI_FTYPE_HI:
> + case QI_FTYPE_V8HI:
> + case HI_FTYPE_V16HI:
> + case SI_FTYPE_V32HI:
> + case QI_FTYPE_V4SI:
> + case QI_FTYPE_V8SI:
> + case HI_FTYPE_V16SI:
> + case QI_FTYPE_V2DI:
> + case QI_FTYPE_V4DI:
> + case QI_FTYPE_V8DI:
> case UINT_FTYPE_V2DF:
> case UINT_FTYPE_V4SF:
> case UINT64_FTYPE_V2DF:
> @@ -33810,6 +35783,8 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> case V16QI_FTYPE_V8DI:
> case V16HI_FTYPE_V16SI:
> case V16SI_FTYPE_HI:
> + case V2DI_FTYPE_QI:
> + case V4DI_FTYPE_QI:
> case V16SI_FTYPE_V16SI:
> case V16SI_FTYPE_INT:
> case V16SF_FTYPE_FLOAT:
> @@ -33821,7 +35796,6 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> case V8HI_FTYPE_V8DI:
> case V8UHI_FTYPE_V8UHI:
> case V8SI_FTYPE_V8DI:
> - case V8USI_FTYPE_V8USI:
> case V8SF_FTYPE_V8DF:
> case V8DI_FTYPE_QI:
> case V8DI_FTYPE_INT64:
> @@ -33902,6 +35876,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> case V4DI_FTYPE_V8SI_V8SI:
> case V4UDI_FTYPE_V8USI_V8USI:
> case QI_FTYPE_V8DI_V8DI:
> + case V8DI_FTYPE_V64QI_V64QI:
> case HI_FTYPE_V16SI_V16SI:
> if (comparison == UNKNOWN)
> return ix86_expand_binop_builtin (icode, exp, target);
> @@ -33941,6 +35916,8 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> case UINT16_FTYPE_UINT16_INT:
> case UINT8_FTYPE_UINT8_INT:
> case HI_FTYPE_HI_HI:
> + case SI_FTYPE_SI_SI:
> + case DI_FTYPE_DI_DI:
> case V16SI_FTYPE_V8DF_V8DF:
> nargs = 2;
> break;
> @@ -33954,6 +35931,11 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> rmode = V2TImode;
> nargs_constant = 1;
> break;
> + case V8DI_FTYPE_V8DI_INT_CONVERT:
> + nargs = 2;
> + rmode = V4TImode;
> + nargs_constant = 1;
> + break;
> case V8HI_FTYPE_V8HI_INT:
> case V8HI_FTYPE_V8SF_INT:
> case V16HI_FTYPE_V16SF_INT:
> @@ -33979,6 +35961,8 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> case V2DI_FTYPE_V4DI_INT:
> case V4DI_FTYPE_V8DI_INT:
> case HI_FTYPE_HI_INT:
> + case QI_FTYPE_V4SF_INT:
> + case QI_FTYPE_V2DF_INT:
> nargs = 2;
> nargs_constant = 1;
> break;
> @@ -34003,20 +35987,118 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> case V16SI_FTYPE_V16HI_V16SI_HI:
> case V16SI_FTYPE_V16QI_V16SI_HI:
> case V16SI_FTYPE_V16SF_V16SI_HI:
> + case V8SF_FTYPE_V4SF_V8SF_QI:
> + case V4DF_FTYPE_V2DF_V4DF_QI:
> + case V8SI_FTYPE_V4SI_V8SI_QI:
> + case V8SI_FTYPE_SI_V8SI_QI:
> + case V4SI_FTYPE_V4SI_V4SI_QI:
> + case V4SI_FTYPE_SI_V4SI_QI:
> + case V4DI_FTYPE_V2DI_V4DI_QI:
> + case V4DI_FTYPE_DI_V4DI_QI:
> + case V2DI_FTYPE_V2DI_V2DI_QI:
> + case V2DI_FTYPE_DI_V2DI_QI:
> + case V64QI_FTYPE_V64QI_V64QI_DI:
> + case V64QI_FTYPE_V16QI_V64QI_DI:
> + case V64QI_FTYPE_QI_V64QI_DI:
> + case V32QI_FTYPE_V32QI_V32QI_SI:
> + case V32QI_FTYPE_V16QI_V32QI_SI:
> + case V32QI_FTYPE_QI_V32QI_SI:
> + case V16QI_FTYPE_V16QI_V16QI_HI:
> + case V16QI_FTYPE_QI_V16QI_HI:
> + case V32HI_FTYPE_V8HI_V32HI_SI:
> + case V32HI_FTYPE_HI_V32HI_SI:
> + case V16HI_FTYPE_V8HI_V16HI_HI:
> + case V16HI_FTYPE_HI_V16HI_HI:
> + case V8HI_FTYPE_V8HI_V8HI_QI:
> + case V8HI_FTYPE_HI_V8HI_QI:
> + case V8SF_FTYPE_V8HI_V8SF_QI:
> + case V4SF_FTYPE_V8HI_V4SF_QI:
> + case V8SI_FTYPE_V8SF_V8SI_QI:
> + case V4SI_FTYPE_V4SF_V4SI_QI:
> + case V8DI_FTYPE_V8SF_V8DI_QI:
> + case V4DI_FTYPE_V4SF_V4DI_QI:
> + case V2DI_FTYPE_V4SF_V2DI_QI:
> + case V8SF_FTYPE_V8DI_V8SF_QI:
> + case V4SF_FTYPE_V4DI_V4SF_QI:
> + case V4SF_FTYPE_V2DI_V4SF_QI:
> + case V8DF_FTYPE_V8DI_V8DF_QI:
> + case V4DF_FTYPE_V4DI_V4DF_QI:
> + case V2DF_FTYPE_V2DI_V2DF_QI:
> + case V16QI_FTYPE_V8HI_V16QI_QI:
> + case V16QI_FTYPE_V16HI_V16QI_HI:
> + case V16QI_FTYPE_V4SI_V16QI_QI:
> + case V16QI_FTYPE_V8SI_V16QI_QI:
> + case V8HI_FTYPE_V4SI_V8HI_QI:
> + case V8HI_FTYPE_V8SI_V8HI_QI:
> + case V16QI_FTYPE_V2DI_V16QI_QI:
> + case V16QI_FTYPE_V4DI_V16QI_QI:
> + case V8HI_FTYPE_V2DI_V8HI_QI:
> + case V8HI_FTYPE_V4DI_V8HI_QI:
> + case V4SI_FTYPE_V2DI_V4SI_QI:
> + case V4SI_FTYPE_V4DI_V4SI_QI:
> + case V32QI_FTYPE_V32HI_V32QI_SI:
> + case HI_FTYPE_V16QI_V16QI_HI:
> + case SI_FTYPE_V32QI_V32QI_SI:
> + case DI_FTYPE_V64QI_V64QI_DI:
> + case QI_FTYPE_V8HI_V8HI_QI:
> + case HI_FTYPE_V16HI_V16HI_HI:
> + case SI_FTYPE_V32HI_V32HI_SI:
> + case QI_FTYPE_V4SI_V4SI_QI:
> + case QI_FTYPE_V8SI_V8SI_QI:
> + case QI_FTYPE_V2DI_V2DI_QI:
> + case QI_FTYPE_V4DI_V4DI_QI:
> + case V4SF_FTYPE_V2DF_V4SF_QI:
> + case V4SF_FTYPE_V4DF_V4SF_QI:
> + nargs = 3;
> case V16SI_FTYPE_V16SI_V16SI_HI:
> case V16SI_FTYPE_V16SI_V16SI_V16SI:
> case V16SI_FTYPE_V4SI_V16SI_HI:
> case V2DI_FTYPE_V2DI_V2DI_V2DI:
> + case V2DI_FTYPE_V4SI_V2DI_QI:
> + case V2DI_FTYPE_V8HI_V2DI_QI:
> + case V2DI_FTYPE_V16QI_V2DI_QI:
> + case V4DI_FTYPE_V4DI_V4DI_QI:
> + case V4DI_FTYPE_V4SI_V4DI_QI:
> + case V4DI_FTYPE_V8HI_V4DI_QI:
> + case V4DI_FTYPE_V16QI_V4DI_QI:
> + case V8DI_FTYPE_V8DF_V8DI_QI:
> + case V4DI_FTYPE_V4DF_V4DI_QI:
> + case V2DI_FTYPE_V2DF_V2DI_QI:
> + case V4SI_FTYPE_V4DF_V4SI_QI:
> + case V4SI_FTYPE_V2DF_V4SI_QI:
> + case V4SI_FTYPE_V8HI_V4SI_QI:
> + case V4SI_FTYPE_V16QI_V4SI_QI:
> + case V8SI_FTYPE_V8SI_V8SI_V8SI:
> case V4DI_FTYPE_V4DI_V4DI_V4DI:
> case V8DF_FTYPE_V2DF_V8DF_QI:
> case V8DF_FTYPE_V4DF_V8DF_QI:
> case V8DF_FTYPE_V8DF_V8DF_QI:
> case V8DF_FTYPE_V8DF_V8DF_V8DF:
> + case V8SF_FTYPE_V8SF_V8SF_QI:
> + case V8SF_FTYPE_V8SI_V8SF_QI:
> + case V4DF_FTYPE_V4DF_V4DF_QI:
> + case V4SF_FTYPE_V4SF_V4SF_QI:
> + case V2DF_FTYPE_V2DF_V2DF_QI:
> + case V2DF_FTYPE_V4SF_V2DF_QI:
> + case V2DF_FTYPE_V4SI_V2DF_QI:
> + case V4SF_FTYPE_V4SI_V4SF_QI:
> + case V4DF_FTYPE_V4SF_V4DF_QI:
> + case V4DF_FTYPE_V4SI_V4DF_QI:
> + case V8SI_FTYPE_V8SI_V8SI_QI:
> + case V8SI_FTYPE_V8HI_V8SI_QI:
> + case V8SI_FTYPE_V16QI_V8SI_QI:
> case V8DF_FTYPE_V8DF_V8DI_V8DF:
> case V8DF_FTYPE_V8DI_V8DF_V8DF:
> case V8DF_FTYPE_V8SF_V8DF_QI:
> case V8DF_FTYPE_V8SI_V8DF_QI:
> case V8DI_FTYPE_DI_V8DI_QI:
> + case V16SF_FTYPE_V8SF_V16SF_HI:
> + case V16SI_FTYPE_V8SI_V16SI_HI:
> + case V16HI_FTYPE_V16HI_V16HI_HI:
> + case V8HI_FTYPE_V16QI_V8HI_QI:
> + case V16HI_FTYPE_V16QI_V16HI_HI:
> + case V32HI_FTYPE_V32HI_V32HI_SI:
> + case V32HI_FTYPE_V32QI_V32HI_SI:
> case V8DI_FTYPE_V16QI_V8DI_QI:
> case V8DI_FTYPE_V2DI_V8DI_QI:
> case V8DI_FTYPE_V4DI_V8DI_QI:
> @@ -34078,13 +36160,80 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> nargs = 3;
> nargs_constant = 2;
> break;
> + case V8DI_FTYPE_V8DI_V8DI_INT_CONVERT:
> + nargs = 3;
> + rmode = V8DImode;
> + nargs_constant = 1;
> + break;
> + case V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT:
> + nargs = 5;
> + rmode = V8DImode;
> + mask_pos = 2;
> + nargs_constant = 1;
> + break;
> + case QI_FTYPE_V8DF_INT_QI:
> + case QI_FTYPE_V4DF_INT_QI:
> + case QI_FTYPE_V2DF_INT_QI:
> + case HI_FTYPE_V16SF_INT_HI:
> + case QI_FTYPE_V8SF_INT_QI:
> + case QI_FTYPE_V4SF_INT_QI:
> + nargs = 3;
> + mask_pos = 1;
> + nargs_constant = 1;
> + break;
> + case V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT:
> + nargs = 5;
> + rmode = V4DImode;
> + mask_pos = 2;
> + nargs_constant = 1;
> + break;
> + case V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT:
> + nargs = 5;
> + rmode = V2DImode;
> + mask_pos = 2;
> + nargs_constant = 1;
> + break;
> + case V32QI_FTYPE_V32QI_V32QI_V32QI_SI:
> + case V32HI_FTYPE_V32HI_V32HI_V32HI_SI:
> + case V32HI_FTYPE_V64QI_V64QI_V32HI_SI:
> + case V16SI_FTYPE_V32HI_V32HI_V16SI_HI:
> + case V64QI_FTYPE_V64QI_V64QI_V64QI_DI:
> + case V32HI_FTYPE_V32HI_V8HI_V32HI_SI:
> + case V16HI_FTYPE_V16HI_V8HI_V16HI_HI:
> + case V8SI_FTYPE_V8SI_V4SI_V8SI_QI:
> + case V4DI_FTYPE_V4DI_V2DI_V4DI_QI:
> + case V64QI_FTYPE_V32HI_V32HI_V64QI_DI:
> + case V32QI_FTYPE_V16HI_V16HI_V32QI_SI:
> + case V16QI_FTYPE_V8HI_V8HI_V16QI_HI:
> + case V32HI_FTYPE_V16SI_V16SI_V32HI_SI:
> + case V16HI_FTYPE_V8SI_V8SI_V16HI_HI:
> + case V8HI_FTYPE_V4SI_V4SI_V8HI_QI:
> + case V4DF_FTYPE_V4DF_V4DI_V4DF_QI:
> + case V8SF_FTYPE_V8SF_V8SI_V8SF_QI:
> + case V4SF_FTYPE_V4SF_V4SI_V4SF_QI:
> + case V2DF_FTYPE_V2DF_V2DI_V2DF_QI:
> + case V2DI_FTYPE_V4SI_V4SI_V2DI_QI:
> + case V4DI_FTYPE_V8SI_V8SI_V4DI_QI:
> + case V4DF_FTYPE_V4DI_V4DF_V4DF_QI:
> + case V8SF_FTYPE_V8SI_V8SF_V8SF_QI:
> + case V2DF_FTYPE_V2DI_V2DF_V2DF_QI:
> + case V4SF_FTYPE_V4SI_V4SF_V4SF_QI:
> case V16SF_FTYPE_V16SF_V16SF_V16SF_HI:
> case V16SF_FTYPE_V16SF_V16SI_V16SF_HI:
> case V16SF_FTYPE_V16SI_V16SF_V16SF_HI:
> case V16SI_FTYPE_V16SI_V16SI_V16SI_HI:
> case V16SI_FTYPE_V16SI_V4SI_V16SI_HI:
> + case V8HI_FTYPE_V8HI_V8HI_V8HI_QI:
> + case V8SI_FTYPE_V8SI_V8SI_V8SI_QI:
> + case V4SI_FTYPE_V4SI_V4SI_V4SI_QI:
> + case V8SF_FTYPE_V8SF_V8SF_V8SF_QI:
> + case V16QI_FTYPE_V16QI_V16QI_V16QI_HI:
> + case V16HI_FTYPE_V16HI_V16HI_V16HI_HI:
> + case V2DI_FTYPE_V2DI_V2DI_V2DI_QI:
> case V2DF_FTYPE_V2DF_V2DF_V2DF_QI:
> case V2DF_FTYPE_V2DF_V4SF_V2DF_QI:
> + case V4DI_FTYPE_V4DI_V4DI_V4DI_QI:
> + case V4DF_FTYPE_V4DF_V4DF_V4DF_QI:
> case V4SF_FTYPE_V4SF_V2DF_V4SF_QI:
> case V4SF_FTYPE_V4SF_V4SF_V4SF_QI:
> case V8DF_FTYPE_V8DF_V8DF_V8DF_QI:
> @@ -34094,6 +36243,10 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> case V8DI_FTYPE_V8DI_SI_V8DI_V8DI:
> case V8DI_FTYPE_V8DI_V2DI_V8DI_QI:
> case V8DI_FTYPE_V8DI_V8DI_V8DI_QI:
> + case V8HI_FTYPE_V16QI_V16QI_V8HI_QI:
> + case V16HI_FTYPE_V32QI_V32QI_V16HI_HI:
> + case V8SI_FTYPE_V16HI_V16HI_V8SI_QI:
> + case V4SI_FTYPE_V8HI_V8HI_V4SI_QI:
> nargs = 4;
> break;
> case V2DF_FTYPE_V2DF_V2DF_V2DI_INT:
> @@ -34104,8 +36257,20 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> nargs = 4;
> nargs_constant = 1;
> break;
> + case QI_FTYPE_V4DI_V4DI_INT_QI:
> + case QI_FTYPE_V8SI_V8SI_INT_QI:
> + case QI_FTYPE_V4DF_V4DF_INT_QI:
> + case QI_FTYPE_V8SF_V8SF_INT_QI:
> + case QI_FTYPE_V2DI_V2DI_INT_QI:
> + case QI_FTYPE_V4SI_V4SI_INT_QI:
> case QI_FTYPE_V2DF_V2DF_INT_QI:
> case QI_FTYPE_V4SF_V4SF_INT_QI:
> + case DI_FTYPE_V64QI_V64QI_INT_DI:
> + case SI_FTYPE_V32QI_V32QI_INT_SI:
> + case HI_FTYPE_V16QI_V16QI_INT_HI:
> + case SI_FTYPE_V32HI_V32HI_INT_SI:
> + case HI_FTYPE_V16HI_V16HI_INT_HI:
> + case QI_FTYPE_V8HI_V8HI_INT_QI:
> nargs = 4;
> mask_pos = 1;
> nargs_constant = 1;
> @@ -34126,6 +36291,27 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> nargs = 4;
> nargs_constant = 1;
> break;
> + case V8SF_FTYPE_V8SF_INT_V8SF_QI:
> + case V4SF_FTYPE_V4SF_INT_V4SF_QI:
> + case V2DF_FTYPE_V4DF_INT_V2DF_QI:
> + case V2DI_FTYPE_V4DI_INT_V2DI_QI:
> + case V8SF_FTYPE_V16SF_INT_V8SF_QI:
> + case V8SI_FTYPE_V16SI_INT_V8SI_QI:
> + case V2DF_FTYPE_V8DF_INT_V2DF_QI:
> + case V2DI_FTYPE_V8DI_INT_V2DI_QI:
> + case V4SF_FTYPE_V8SF_INT_V4SF_QI:
> + case V4SI_FTYPE_V8SI_INT_V4SI_QI:
> + case V8HI_FTYPE_V8SF_INT_V8HI_QI:
> + case V8HI_FTYPE_V4SF_INT_V8HI_QI:
> + case V32HI_FTYPE_V32HI_INT_V32HI_SI:
> + case V16HI_FTYPE_V16HI_INT_V16HI_HI:
> + case V8HI_FTYPE_V8HI_INT_V8HI_QI:
> + case V4DI_FTYPE_V4DI_INT_V4DI_QI:
> + case V2DI_FTYPE_V2DI_INT_V2DI_QI:
> + case V8SI_FTYPE_V8SI_INT_V8SI_QI:
> + case V4SI_FTYPE_V4SI_INT_V4SI_QI:
> + case V4DF_FTYPE_V4DF_INT_V4DF_QI:
> + case V2DF_FTYPE_V2DF_INT_V2DF_QI:
> case V8DF_FTYPE_V8DF_INT_V8DF_QI:
> case V16SF_FTYPE_V16SF_INT_V16SF_HI:
> case V16HI_FTYPE_V16SF_INT_V16HI_HI:
> @@ -34149,6 +36335,23 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> case V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI:
> case V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI:
> case V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI:
> + case V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI:
> + case V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI:
> + case V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI:
> + case V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI:
> + case V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI:
> + case V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI:
> + case V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI:
> + case V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI:
> + case V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI:
> + case V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI:
> + case V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI:
> + case V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI:
> + case V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI:
> + case V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI:
> + case V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI:
> + case V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI:
> + case V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI:
> nargs = 5;
> mask_pos = 2;
> nargs_constant = 1;
> @@ -34158,6 +36361,13 @@ ix86_expand_args_builtin (const struct builtin_description *d,
> case V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI:
> case V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI:
> case V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI:
> + case V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI:
> + case V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI:
> + case V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI:
> + case V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI:
> + case V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI:
> + case V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI:
> + nargs = 5;
> nargs = 5;
> mask_pos = 1;
> nargs_constant = 1;
> @@ -34606,7 +36816,11 @@ ix86_expand_round_builtin (const struct builtin_description *d,
> case V8SF_FTYPE_V8DF_V8SF_QI_INT:
> case V8DF_FTYPE_V8DF_V8DF_QI_INT:
> case V8SI_FTYPE_V8DF_V8SI_QI_INT:
> + case V8DI_FTYPE_V8DF_V8DI_QI_INT:
> + case V8SF_FTYPE_V8DI_V8SF_QI_INT:
> + case V8DF_FTYPE_V8DI_V8DF_QI_INT:
> case V16SF_FTYPE_V16SF_V16SF_HI_INT:
> + case V8DI_FTYPE_V8SF_V8DI_QI_INT:
> case V16SF_FTYPE_V16SI_V16SF_HI_INT:
> case V16SI_FTYPE_V16SF_V16SI_HI_INT:
> case V8DF_FTYPE_V8SF_V8DF_QI_INT:
> @@ -34643,6 +36857,8 @@ ix86_expand_round_builtin (const struct builtin_description *d,
> nargs_constant = 3;
> nargs = 5;
> break;
> + case V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT:
> + case V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT:
> case V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI_INT:
> case V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI_INT:
> nargs = 6;
> @@ -34905,7 +37121,11 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
> case VOID_FTYPE_PV8DF_V8DF_QI:
> case VOID_FTYPE_PV16SF_V16SF_HI:
> case VOID_FTYPE_PV8DI_V8DI_QI:
> + case VOID_FTYPE_PV4DI_V4DI_QI:
> + case VOID_FTYPE_PV2DI_V2DI_QI:
> case VOID_FTYPE_PV16SI_V16SI_HI:
> + case VOID_FTYPE_PV8SI_V8SI_QI:
> + case VOID_FTYPE_PV4SI_V4SI_QI:
> switch (icode)
> {
> /* These builtins and instructions require the memory
> @@ -34943,17 +37163,51 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
> case VOID_FTYPE_PV16HI_V16SI_HI:
> case VOID_FTYPE_PV16QI_V8DI_QI:
> case VOID_FTYPE_PV16QI_V16SI_HI:
> + case VOID_FTYPE_PV4SI_V4DI_QI:
> + case VOID_FTYPE_PV4SI_V2DI_QI:
> + case VOID_FTYPE_PV8HI_V4DI_QI:
> + case VOID_FTYPE_PV8HI_V2DI_QI:
> + case VOID_FTYPE_PV8HI_V8SI_QI:
> + case VOID_FTYPE_PV8HI_V4SI_QI:
> + case VOID_FTYPE_PV16QI_V4DI_QI:
> + case VOID_FTYPE_PV16QI_V2DI_QI:
> + case VOID_FTYPE_PV16QI_V8SI_QI:
> + case VOID_FTYPE_PV16QI_V4SI_QI:
> + case VOID_FTYPE_PV8HI_V8HI_QI:
> + case VOID_FTYPE_PV16HI_V16HI_HI:
> + case VOID_FTYPE_PV32HI_V32HI_SI:
> + case VOID_FTYPE_PV16QI_V16QI_HI:
> + case VOID_FTYPE_PV32QI_V32QI_SI:
> + case VOID_FTYPE_PV64QI_V64QI_DI:
> + case VOID_FTYPE_PV4DF_V4DF_QI:
> + case VOID_FTYPE_PV2DF_V2DF_QI:
> + case VOID_FTYPE_PV8SF_V8SF_QI:
> + case VOID_FTYPE_PV4SF_V4SF_QI:
> nargs = 2;
> klass = store;
> /* Reserve memory operand for target. */
> memory = ARRAY_SIZE (args);
> break;
> + case V4SF_FTYPE_PCV4SF_V4SF_QI:
> + case V8SF_FTYPE_PCV8SF_V8SF_QI:
> case V16SF_FTYPE_PCV16SF_V16SF_HI:
> + case V4SI_FTYPE_PCV4SI_V4SI_QI:
> + case V8SI_FTYPE_PCV8SI_V8SI_QI:
> case V16SI_FTYPE_PCV16SI_V16SI_HI:
> + case V2DF_FTYPE_PCV2DF_V2DF_QI:
> + case V4DF_FTYPE_PCV4DF_V4DF_QI:
> case V8DF_FTYPE_PCV8DF_V8DF_QI:
> + case V2DI_FTYPE_PCV2DI_V2DI_QI:
> + case V4DI_FTYPE_PCV4DI_V4DI_QI:
> case V8DI_FTYPE_PCV8DI_V8DI_QI:
> case V2DF_FTYPE_PCDOUBLE_V2DF_QI:
> case V4SF_FTYPE_PCFLOAT_V4SF_QI:
> + case V8HI_FTYPE_PCV8HI_V8HI_QI:
> + case V16HI_FTYPE_PCV16HI_V16HI_HI:
> + case V32HI_FTYPE_PCV32HI_V32HI_SI:
> + case V16QI_FTYPE_PCV16QI_V16QI_HI:
> + case V32QI_FTYPE_PCV32QI_V32QI_SI:
> + case V64QI_FTYPE_PCV64QI_V64QI_DI:
> nargs = 3;
> klass = load;
> memory = 0;
> diff --git a/gcc/tree-core.h b/gcc/tree-core.h
> index b69312b..c9c248e 100644
> --- a/gcc/tree-core.h
> +++ b/gcc/tree-core.h
> @@ -1498,7 +1498,9 @@ struct GTY(()) tree_decl_with_vis {
> unsigned cxx_destructor : 1;
> /* Belong to FUNCTION_DECL exclusively. */
> unsigned final : 1;
> - /* 15 unused bits. */
> + /* Belong to FUNCTION_DECL exclusively. */
> + unsigned regdecl_flag : 1;
> + /* 14 unused bits. */
> };
>
> struct GTY(()) tree_var_decl {
> @@ -1539,7 +1541,7 @@ struct GTY(()) tree_function_decl {
> DECL_FUNCTION_CODE. Otherwise unused.
> ??? The bitfield needs to be able to hold all target function
> codes as well. */
> - ENUM_BITFIELD(built_in_function) function_code : 11;
> + ENUM_BITFIELD(built_in_function) function_code : 12;
> ENUM_BITFIELD(built_in_class) built_in_class : 2;
>
> unsigned static_ctor_flag : 1;
> @@ -1552,7 +1554,6 @@ struct GTY(()) tree_function_decl {
> unsigned malloc_flag : 1;
> unsigned operator_new_flag : 1;
> unsigned declared_inline_flag : 1;
> - unsigned regdecl_flag : 1;
> unsigned no_inline_warning_flag : 1;
>
> unsigned no_instrument_function_entry_exit : 1;
> diff --git a/gcc/tree.h b/gcc/tree.h
> index 45f127f..5ba6e0f 100644
> --- a/gcc/tree.h
> +++ b/gcc/tree.h
> @@ -2334,6 +2334,10 @@ extern void decl_value_expr_insert (tree, tree);
> #define DECL_COMDAT(NODE) \
> (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.comdat_flag)
>
> + /* In a FUNCTION_DECL indicates that a static chain is needed. */
> +#define DECL_STATIC_CHAIN(NODE) \
> + (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.regdecl_flag)
> +
> #define DECL_COMDAT_GROUP(NODE) \
> decl_comdat_group (NODE)
>
> @@ -2551,10 +2555,6 @@ extern void decl_fini_priority_insert (tree, priority_type);
> #define DECL_NO_LIMIT_STACK(NODE) \
> (FUNCTION_DECL_CHECK (NODE)->function_decl.no_limit_stack)
>
> -/* In a FUNCTION_DECL indicates that a static chain is needed. */
> -#define DECL_STATIC_CHAIN(NODE) \
> - (FUNCTION_DECL_CHECK (NODE)->function_decl.regdecl_flag)
> -
> /* Nonzero for a decl that cgraph has decided should be inlined into
> at least one call site. It is not meaningful to look at this
> directly; always use cgraph_function_possibly_inlined_p. */
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH i386 AVX512] [81/n] Add new built-ins.
2014-10-21 14:21 ` Jakub Jelinek
@ 2014-10-21 14:52 ` Kirill Yukhin
2014-10-21 15:13 ` Kirill Yukhin
2014-10-22 7:57 ` [PATCH AVX512] [81.1/n] Extend `function_code' field in `tree_var_decl' structure Kirill Yukhin
1 sibling, 1 reply; 16+ messages in thread
From: Kirill Yukhin @ 2014-10-21 14:52 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: Uros Bizjak, Richard Henderson, GCC Patches
On 21 Oct 16:20, Jakub Jelinek wrote:
> On Tue, Oct 21, 2014 at 06:08:15PM +0400, Kirill Yukhin wrote:
> > --- a/gcc/tree.h
> > +++ b/gcc/tree.h
> > @@ -2334,6 +2334,10 @@ extern void decl_value_expr_insert (tree, tree);
> > #define DECL_COMDAT(NODE) \
> > (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.comdat_flag)
> >
> > + /* In a FUNCTION_DECL indicates that a static chain is needed. */
> > +#define DECL_STATIC_CHAIN(NODE) \
> > + (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.regdecl_flag)
> > +
>
> I would say that you should still keep it together with the FUNCTION_DECL
> macros and use FUNCTION_DECL_CHECK there, to make it clear we don't want
> the macro to be used on VAR_DECLs etc.
> So just s/function_decl/decl_with_vis/ in the definition IMHO.
Yeah, sure.
> Also, with so many added builtins, how does it affect
> int i;
> compilation time at -O0? If it is significant, maybe it is highest time to
> make the md builtin decl building more lazy.
I've tried this:
$ echo "int i;" > test.c
$ time for i in `seq 10000` ; do ./build-x86_64-linux/gcc/xgcc -B./build-x86_64-linux/gcc -O0 -S test.c ; done
For trunk w/ and w/o the patch applied.
Got 106.86 vs. 106.85 secs. which looks equal.
So, I think we may say that this patch does not affect compile time.
--
Thanks, K
>
> Jakub
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH i386 AVX512] [81/n] Add new built-ins.
2014-10-21 14:52 ` Kirill Yukhin
@ 2014-10-21 15:13 ` Kirill Yukhin
2014-10-22 8:18 ` Richard Biener
0 siblings, 1 reply; 16+ messages in thread
From: Kirill Yukhin @ 2014-10-21 15:13 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: Uros Bizjak, Richard Henderson, GCC Patches
On 21 Oct 18:47, Kirill Yukhin wrote:
> On 21 Oct 16:20, Jakub Jelinek wrote:
> > On Tue, Oct 21, 2014 at 06:08:15PM +0400, Kirill Yukhin wrote:
> > > --- a/gcc/tree.h
> > > +++ b/gcc/tree.h
> > > @@ -2334,6 +2334,10 @@ extern void decl_value_expr_insert (tree, tree);
> > > #define DECL_COMDAT(NODE) \
> > > (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.comdat_flag)
> > >
> > > + /* In a FUNCTION_DECL indicates that a static chain is needed. */
> > > +#define DECL_STATIC_CHAIN(NODE) \
> > > + (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.regdecl_flag)
> > > +
> >
> > I would say that you should still keep it together with the FUNCTION_DECL
> > macros and use FUNCTION_DECL_CHECK there, to make it clear we don't want
> > the macro to be used on VAR_DECLs etc.
> > So just s/function_decl/decl_with_vis/ in the definition IMHO.
> Yeah, sure.
>
> > Also, with so many added builtins, how does it affect
> > int i;
> > compilation time at -O0? If it is significant, maybe it is highest time to
> > make the md builtin decl building more lazy.
> I've tried this:
> $ echo "int i;" > test.c
> $ time for i in `seq 10000` ; do ./build-x86_64-linux/gcc/xgcc -B./build-x86_64-linux/gcc -O0 -S test.c ; done
>
> For trunk w/ and w/o the patch applied.
> Got 106.86 vs. 106.85 secs. which looks equal.
Retested on clear machine (SandyBridge). Got 189 vs. 192 secs., i.e. ~1%
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH AVX512] [81.1/n] Extend `function_code' field in `tree_var_decl' structure.
2014-10-21 14:21 ` Jakub Jelinek
2014-10-21 14:52 ` Kirill Yukhin
@ 2014-10-22 7:57 ` Kirill Yukhin
2014-10-23 11:10 ` Jakub Jelinek
1 sibling, 1 reply; 16+ messages in thread
From: Kirill Yukhin @ 2014-10-22 7:57 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: Uros Bizjak, Richard Henderson, GCC Patches
Hello,
Patch was separated into two parts: tree-core.h changes and target
changes.
On 21 Oct 16:20, Jakub Jelinek wrote:
> On Tue, Oct 21, 2014 at 06:08:15PM +0400, Kirill Yukhin wrote:
> > --- a/gcc/tree.h
> > +++ b/gcc/tree.h
> > @@ -2334,6 +2334,10 @@ extern void decl_value_expr_insert (tree, tree);
> > #define DECL_COMDAT(NODE) \
> > (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.comdat_flag)
> >
> > + /* In a FUNCTION_DECL indicates that a static chain is needed. */
> > +#define DECL_STATIC_CHAIN(NODE) \
> > + (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.regdecl_flag)
> > +
>
> I would say that you should still keep it together with the FUNCTION_DECL
> macros and use FUNCTION_DECL_CHECK there, to make it clear we don't want
> the macro to be used on VAR_DECLs etc.
> So just s/function_decl/decl_with_vis/ in the definition IMHO.
Thanks, updated.
Also taken into account Richard's input about logical groping of the fields.
> Also, with so many added builtins, how does it affect
> int i;
> compilation time at -O0? If it is significant, maybe it is highest time to
> make the md builtin decl building more lazy.
As mentioned in previous mail, change is less than 1%.
But I will put the task of making built-ins lazy into the queue (probably after
AVX-512 and offload are finished).
gcc/
* tree-core.h (tree_var_decl): Extend `function_code' field
by one bit, move `regdecl_flag' field to ...
(tree_decl_with_vis): Here.
* tree.h (DECL_STATIC_CHAIN): Update struct name.
Bootstrapped.
Is it ok for trunk?
>
> Jakub
diff --git a/gcc/tree-core.h b/gcc/tree-core.h
index b69312b..30db893 100644
--- a/gcc/tree-core.h
+++ b/gcc/tree-core.h
@@ -1498,7 +1498,9 @@ struct GTY(()) tree_decl_with_vis {
unsigned cxx_destructor : 1;
/* Belong to FUNCTION_DECL exclusively. */
unsigned final : 1;
- /* 15 unused bits. */
+ /* Belong to FUNCTION_DECL exclusively. */
+ unsigned regdecl_flag : 1;
+ /* 14 unused bits. */
};
struct GTY(()) tree_var_decl {
@@ -1539,20 +1541,19 @@ struct GTY(()) tree_function_decl {
DECL_FUNCTION_CODE. Otherwise unused.
??? The bitfield needs to be able to hold all target function
codes as well. */
- ENUM_BITFIELD(built_in_function) function_code : 11;
+ ENUM_BITFIELD(built_in_function) function_code : 12;
ENUM_BITFIELD(built_in_class) built_in_class : 2;
unsigned static_ctor_flag : 1;
unsigned static_dtor_flag : 1;
- unsigned uninlinable : 1;
+ unsigned uninlinable : 1;
unsigned possibly_inlined : 1;
unsigned novops_flag : 1;
unsigned returns_twice_flag : 1;
unsigned malloc_flag : 1;
unsigned operator_new_flag : 1;
unsigned declared_inline_flag : 1;
- unsigned regdecl_flag : 1;
unsigned no_inline_warning_flag : 1;
unsigned no_instrument_function_entry_exit : 1;
diff --git a/gcc/tree.h b/gcc/tree.h
index 45f127f..2a085c9 100644
--- a/gcc/tree.h
+++ b/gcc/tree.h
@@ -2553,7 +2553,7 @@ extern void decl_fini_priority_insert (tree, priority_type);
/* In a FUNCTION_DECL indicates that a static chain is needed. */
#define DECL_STATIC_CHAIN(NODE) \
- (FUNCTION_DECL_CHECK (NODE)->function_decl.regdecl_flag)
+ (FUNCTION_DECL_CHECK (NODE)->decl_with_vis.regdecl_flag)
/* Nonzero for a decl that cgraph has decided should be inlined into
at least one call site. It is not meaningful to look at this
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH i386 AVX512] [81/n] Add new built-ins.
2014-10-21 15:13 ` Kirill Yukhin
@ 2014-10-22 8:18 ` Richard Biener
2014-10-22 11:40 ` Kirill Yukhin
0 siblings, 1 reply; 16+ messages in thread
From: Richard Biener @ 2014-10-22 8:18 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Jakub Jelinek, Uros Bizjak, Richard Henderson, GCC Patches
On Tue, Oct 21, 2014 at 5:08 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> On 21 Oct 18:47, Kirill Yukhin wrote:
>> On 21 Oct 16:20, Jakub Jelinek wrote:
>> > On Tue, Oct 21, 2014 at 06:08:15PM +0400, Kirill Yukhin wrote:
>> > > --- a/gcc/tree.h
>> > > +++ b/gcc/tree.h
>> > > @@ -2334,6 +2334,10 @@ extern void decl_value_expr_insert (tree, tree);
>> > > #define DECL_COMDAT(NODE) \
>> > > (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.comdat_flag)
>> > >
>> > > + /* In a FUNCTION_DECL indicates that a static chain is needed. */
>> > > +#define DECL_STATIC_CHAIN(NODE) \
>> > > + (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.regdecl_flag)
>> > > +
>> >
>> > I would say that you should still keep it together with the FUNCTION_DECL
>> > macros and use FUNCTION_DECL_CHECK there, to make it clear we don't want
>> > the macro to be used on VAR_DECLs etc.
>> > So just s/function_decl/decl_with_vis/ in the definition IMHO.
>> Yeah, sure.
>>
>> > Also, with so many added builtins, how does it affect
>> > int i;
>> > compilation time at -O0? If it is significant, maybe it is highest time to
>> > make the md builtin decl building more lazy.
>> I've tried this:
>> $ echo "int i;" > test.c
>> $ time for i in `seq 10000` ; do ./build-x86_64-linux/gcc/xgcc -B./build-x86_64-linux/gcc -O0 -S test.c ; done
>>
>> For trunk w/ and w/o the patch applied.
>> Got 106.86 vs. 106.85 secs. which looks equal.
> Retested on clear machine (SandyBridge). Got 189 vs. 192 secs., i.e. ~1%
Can you test with -mavx512 (or whatever enables the builtins?)
Richard.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH i386 AVX512] [81/n] Add new built-ins.
2014-10-22 8:18 ` Richard Biener
@ 2014-10-22 11:40 ` Kirill Yukhin
2014-10-22 11:43 ` Jakub Jelinek
0 siblings, 1 reply; 16+ messages in thread
From: Kirill Yukhin @ 2014-10-22 11:40 UTC (permalink / raw)
To: Richard Biener; +Cc: Jakub Jelinek, Uros Bizjak, Richard Henderson, GCC Patches
Hello,
On 22 Oct 10:09, Richard Biener wrote:
> On Tue, Oct 21, 2014 at 5:08 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> > On 21 Oct 18:47, Kirill Yukhin wrote:
> >> On 21 Oct 16:20, Jakub Jelinek wrote:
> >> > On Tue, Oct 21, 2014 at 06:08:15PM +0400, Kirill Yukhin wrote:
> >> > > --- a/gcc/tree.h
> >> > > +++ b/gcc/tree.h
> >> > > @@ -2334,6 +2334,10 @@ extern void decl_value_expr_insert (tree, tree);
> >> > > #define DECL_COMDAT(NODE) \
> >> > > (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.comdat_flag)
> >> > >
> >> > > + /* In a FUNCTION_DECL indicates that a static chain is needed. */
> >> > > +#define DECL_STATIC_CHAIN(NODE) \
> >> > > + (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.regdecl_flag)
> >> > > +
> >> >
> >> > I would say that you should still keep it together with the FUNCTION_DECL
> >> > macros and use FUNCTION_DECL_CHECK there, to make it clear we don't want
> >> > the macro to be used on VAR_DECLs etc.
> >> > So just s/function_decl/decl_with_vis/ in the definition IMHO.
> >> Yeah, sure.
> >>
> >> > Also, with so many added builtins, how does it affect
> >> > int i;
> >> > compilation time at -O0? If it is significant, maybe it is highest time to
> >> > make the md builtin decl building more lazy.
> >> I've tried this:
> >> $ echo "int i;" > test.c
> >> $ time for i in `seq 10000` ; do ./build-x86_64-linux/gcc/xgcc -B./build-x86_64-linux/gcc -O0 -S test.c ; done
> >>
> >> For trunk w/ and w/o the patch applied.
> >> Got 106.86 vs. 106.85 secs. which looks equal.
> > Retested on clear machine (SandyBridge). Got 189 vs. 192 secs., i.e. ~1%
>
> Can you test with -mavx512 (or whatever enables the builtins?)
Done.
I did:
sync && time for i in `seq 1000` ; do ./build-x86_64-linux/gcc/xgcc -B./build-x86_64-linux/gcc -O0 -S test.c -mavx512vl ; done
Here're results.
w/o the patch applied:
real 0m14.245s
user 0m10.753s
sys 0m2.150s
w/ the patch applied:
real 0m16.404s
user 0m12.935s
sys 0m2.577s
So, we have compilation 15% slowdown when -mavx512vl
is provided and no difference when not.
Is this change is acceptable?
--
Thanks, K
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH i386 AVX512] [81/n] Add new built-ins.
2014-10-22 11:40 ` Kirill Yukhin
@ 2014-10-22 11:43 ` Jakub Jelinek
0 siblings, 0 replies; 16+ messages in thread
From: Jakub Jelinek @ 2014-10-22 11:43 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Richard Biener, Uros Bizjak, Richard Henderson, GCC Patches
On Wed, Oct 22, 2014 at 03:34:22PM +0400, Kirill Yukhin wrote:
> > Can you test with -mavx512 (or whatever enables the builtins?)
> Done.
> I did:
> sync && time for i in `seq 1000` ; do ./build-x86_64-linux/gcc/xgcc -B./build-x86_64-linux/gcc -O0 -S test.c -mavx512vl ; done
>
> Here're results.
> w/o the patch applied:
> real 0m14.245s
> user 0m10.753s
> sys 0m2.150s
>
> w/ the patch applied:
> real 0m16.404s
> user 0m12.935s
> sys 0m2.577s
>
> So, we have compilation 15% slowdown when -mavx512vl
> is provided and no difference when not.
> Is this change is acceptable?
As #include <x86intrin.h> enables everything these days,
it will affect also that.
I'd say the 15% slowdown for -mavx512vl and #include <x86intrin.h>
is not something that would preclude applying the patch, but definitely
something to work on later on.
Unfortunately, for the x86intrin.h case, lazy initialization of the builtins
supposedly doesn't help at all, because pretty much all the builtins will be
there.
Jakub
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH AVX512] [81.1/n] Extend `function_code' field in `tree_var_decl' structure.
2014-10-22 7:57 ` [PATCH AVX512] [81.1/n] Extend `function_code' field in `tree_var_decl' structure Kirill Yukhin
@ 2014-10-23 11:10 ` Jakub Jelinek
0 siblings, 0 replies; 16+ messages in thread
From: Jakub Jelinek @ 2014-10-23 11:10 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Uros Bizjak, Richard Henderson, GCC Patches
On Wed, Oct 22, 2014 at 11:51:32AM +0400, Kirill Yukhin wrote:
> gcc/
> * tree-core.h (tree_var_decl): Extend `function_code' field
> by one bit, move `regdecl_flag' field to ...
> (tree_decl_with_vis): Here.
> * tree.h (DECL_STATIC_CHAIN): Update struct name.
>
>
> Bootstrapped.
>
> Is it ok for trunk?
Ok for trunk for now, I hope we can reduce the number of builtins in the future
though. Even the current 1470 i?86 builtins is too big IMHO, and if you add
hundreds further builtins...
Jakub
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH i386 AVX512] [81.2/n] Add new built-ins.
2014-10-20 13:50 [PATCH i386 AVX512] [81/n] Add new built-ins Kirill Yukhin
2014-10-20 13:56 ` Jakub Jelinek
@ 2014-10-23 12:58 ` Kirill Yukhin
2014-10-23 13:46 ` Uros Bizjak
1 sibling, 1 reply; 16+ messages in thread
From: Kirill Yukhin @ 2014-10-23 12:58 UTC (permalink / raw)
To: Uros Bizjak; +Cc: Jakub Jelinek, Richard Henderson, GCC Patches
Hello Uroš,
On 20 Oct 17:41, Kirill Yukhin wrote:
> This patch adds (almost) all built-ins
This is second, target dependent, part of the initial patch.
ChangeLog is the same as in intial mail - tree* changes.
Is it ok for trunk?
--
Thanks, K
diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def
index 9161287..8315c5e 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -56,6 +56,7 @@ DEF_PRIMITIVE_TYPE (UHI, unsigned_intHI_type_node)
DEF_PRIMITIVE_TYPE (USI, unsigned_intSI_type_node)
DEF_PRIMITIVE_TYPE (UDI, long_long_unsigned_type_node)
# ??? Some of the types below should use the mode types above.
+DEF_PRIMITIVE_TYPE (SHORT, short_integer_type_node)
DEF_PRIMITIVE_TYPE (USHORT, short_unsigned_type_node)
DEF_PRIMITIVE_TYPE (INT, integer_type_node)
DEF_PRIMITIVE_TYPE (UINT, unsigned_type_node)
@@ -107,7 +108,14 @@ DEF_VECTOR_TYPE (V16SF, FLOAT)
DEF_VECTOR_TYPE (V8DF, DOUBLE)
DEF_VECTOR_TYPE (V8DI, DI)
DEF_VECTOR_TYPE (V16SI, SI)
+DEF_VECTOR_TYPE (V32HI, HI)
DEF_VECTOR_TYPE (V64QI, QI)
+DEF_VECTOR_TYPE (V12QI, QI)
+DEF_VECTOR_TYPE (V14QI, QI)
+DEF_VECTOR_TYPE (V32SI, SI)
+DEF_VECTOR_TYPE (V8UDI, UDI, V8DI)
+DEF_VECTOR_TYPE (V16USI, USI, V16SI)
+DEF_VECTOR_TYPE (V32UHI, UHI, V32HI)
DEF_POINTER_TYPE (PCCHAR, CHAR, CONST)
DEF_POINTER_TYPE (PCDOUBLE, DOUBLE, CONST)
@@ -119,6 +127,7 @@ DEF_POINTER_TYPE (PCVOID, VOID, CONST)
DEF_POINTER_TYPE (PVOID, VOID)
DEF_POINTER_TYPE (PDOUBLE, DOUBLE)
DEF_POINTER_TYPE (PFLOAT, FLOAT)
+DEF_POINTER_TYPE (PSHORT, SHORT)
DEF_POINTER_TYPE (PUSHORT, USHORT)
DEF_POINTER_TYPE (PINT, INT)
DEF_POINTER_TYPE (PLONGLONG, LONGLONG)
@@ -142,6 +151,9 @@ DEF_POINTER_TYPE (PV16QI, V16QI)
DEF_POINTER_TYPE (PV16HI, V16HI)
DEF_POINTER_TYPE (PV16SI, V16SI)
DEF_POINTER_TYPE (PV16SF, V16SF)
+DEF_POINTER_TYPE (PV32QI, V32QI)
+DEF_POINTER_TYPE (PV32HI, V32HI)
+DEF_POINTER_TYPE (PV64QI, V64QI)
DEF_POINTER_TYPE (PCV2SI, V2SI, CONST)
DEF_POINTER_TYPE (PCV2DF, V2DF, CONST)
@@ -155,9 +167,15 @@ DEF_POINTER_TYPE (PCV16SF, V16SF, CONST)
DEF_POINTER_TYPE (PCV2DI, V2DI, CONST)
DEF_POINTER_TYPE (PCV4SI, V4SI, CONST)
DEF_POINTER_TYPE (PCV4DI, V4DI, CONST)
+DEF_POINTER_TYPE (PCV8HI, V8HI, CONST)
DEF_POINTER_TYPE (PCV8SI, V8SI, CONST)
DEF_POINTER_TYPE (PCV8DI, V8DI, CONST)
+DEF_POINTER_TYPE (PCV16QI, V16QI, CONST)
+DEF_POINTER_TYPE (PCV16HI, V16HI, CONST)
DEF_POINTER_TYPE (PCV16SI, V16SI, CONST)
+DEF_POINTER_TYPE (PCV32QI, V32QI, CONST)
+DEF_POINTER_TYPE (PCV32HI, V32HI, CONST)
+DEF_POINTER_TYPE (PCV64QI, V64QI, CONST)
DEF_FUNCTION_TYPE (FLOAT128)
DEF_FUNCTION_TYPE (UINT64)
@@ -217,12 +235,15 @@ DEF_FUNCTION_TYPE (V8DF, V8DF)
DEF_FUNCTION_TYPE (V4HI, V4HI)
DEF_FUNCTION_TYPE (V4SF, PCFLOAT)
DEF_FUNCTION_TYPE (V4SF, V2DF)
+DEF_FUNCTION_TYPE (V4SF, V2DF, V4SF, QI)
DEF_FUNCTION_TYPE (V4SF, V4DF)
+DEF_FUNCTION_TYPE (V4SF, V4DF, V4SF, QI)
DEF_FUNCTION_TYPE (V4SF, V4SF)
DEF_FUNCTION_TYPE (V4SF, PCV4SF)
DEF_FUNCTION_TYPE (V4SF, V4SI)
DEF_FUNCTION_TYPE (V4SF, V8SF)
DEF_FUNCTION_TYPE (V4SF, V8HI)
+DEF_FUNCTION_TYPE (V4SF, V8HI, V4SF, QI)
DEF_FUNCTION_TYPE (V4SI, V16QI)
DEF_FUNCTION_TYPE (V4SI, V2DF)
DEF_FUNCTION_TYPE (V4SI, V4DF)
@@ -241,6 +262,7 @@ DEF_FUNCTION_TYPE (V8SF, V4SF)
DEF_FUNCTION_TYPE (V8SF, V8SF)
DEF_FUNCTION_TYPE (V8SF, V8SI)
DEF_FUNCTION_TYPE (V8SF, V8HI)
+DEF_FUNCTION_TYPE (V8SF, V8HI, V8SF, QI)
DEF_FUNCTION_TYPE (V16SF, V16SF)
DEF_FUNCTION_TYPE (V8SI, V8DI)
DEF_FUNCTION_TYPE (V8SI, V4SI)
@@ -251,6 +273,9 @@ DEF_FUNCTION_TYPE (V32QI, V32QI)
DEF_FUNCTION_TYPE (V32QI, V16QI)
DEF_FUNCTION_TYPE (V16HI, V16SI)
DEF_FUNCTION_TYPE (V16HI, V16HI)
+DEF_FUNCTION_TYPE (V16SF, V16HI)
+DEF_FUNCTION_TYPE (V16SF, V16HI, V16SF, HI)
+DEF_FUNCTION_TYPE (V16SF, V16SI)
DEF_FUNCTION_TYPE (V16HI, V8HI)
DEF_FUNCTION_TYPE (V8SI, V8SI)
DEF_FUNCTION_TYPE (VOID, PCVOID)
@@ -266,8 +291,10 @@ DEF_FUNCTION_TYPE (V4DI, V16QI)
DEF_FUNCTION_TYPE (V8SI, V8HI)
DEF_FUNCTION_TYPE (V4DI, V8HI)
DEF_FUNCTION_TYPE (V4DI, V4SI)
+DEF_FUNCTION_TYPE (V4DI, V4DI)
DEF_FUNCTION_TYPE (V4DI, PV4DI)
DEF_FUNCTION_TYPE (V4DI, V2DI)
+DEF_FUNCTION_TYPE (V16SI, V16SF)
DEF_FUNCTION_TYPE (V16SF, FLOAT)
DEF_FUNCTION_TYPE (V16SI, INT)
DEF_FUNCTION_TYPE (V8DF, DOUBLE)
@@ -290,10 +317,38 @@ DEF_FUNCTION_TYPE (V8DI, V8DI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, QI)
DEF_FUNCTION_TYPE (V16SI, PV4SI)
DEF_FUNCTION_TYPE (V16SF, PV4SF)
+DEF_FUNCTION_TYPE (V8DI, PV2DI)
+DEF_FUNCTION_TYPE (V8DF, PV2DF)
+DEF_FUNCTION_TYPE (V4DI, PV2DI)
+DEF_FUNCTION_TYPE (V4DF, PV2DF)
+DEF_FUNCTION_TYPE (V16SI, PV2SI)
+DEF_FUNCTION_TYPE (V16SF, PV2SF)
DEF_FUNCTION_TYPE (V8DI, PV4DI)
DEF_FUNCTION_TYPE (V8DF, PV4DF)
+DEF_FUNCTION_TYPE (V8SF, FLOAT)
+DEF_FUNCTION_TYPE (V4SF, FLOAT)
+DEF_FUNCTION_TYPE (V4DF, DOUBLE)
+DEF_FUNCTION_TYPE (V8SF, PV4SF)
+DEF_FUNCTION_TYPE (V8SI, PV4SI)
+DEF_FUNCTION_TYPE (V4SI, PV2SI)
+DEF_FUNCTION_TYPE (V8SF, PV2SF)
+DEF_FUNCTION_TYPE (V8SI, PV2SI)
+DEF_FUNCTION_TYPE (V16SF, PV8SF)
+DEF_FUNCTION_TYPE (V16SI, PV8SI)
+DEF_FUNCTION_TYPE (V8DI, V8SF)
+DEF_FUNCTION_TYPE (V4DI, V4SF)
+DEF_FUNCTION_TYPE (V2DI, V4SF)
+DEF_FUNCTION_TYPE (V64QI, QI)
+DEF_FUNCTION_TYPE (V32HI, HI)
DEF_FUNCTION_TYPE (V8UHI, V8UHI)
+DEF_FUNCTION_TYPE (V16UHI, V16UHI)
+DEF_FUNCTION_TYPE (V32UHI, V32UHI)
+DEF_FUNCTION_TYPE (V2UDI, V2UDI)
+DEF_FUNCTION_TYPE (V4UDI, V4UDI)
+DEF_FUNCTION_TYPE (V8UDI, V8UDI)
+DEF_FUNCTION_TYPE (V4USI, V4USI)
DEF_FUNCTION_TYPE (V8USI, V8USI)
+DEF_FUNCTION_TYPE (V16USI, V16USI)
DEF_FUNCTION_TYPE (V8DI, PV8DI)
DEF_FUNCTION_TYPE (DI, V2DI, INT)
@@ -336,9 +391,13 @@ DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V4SF)
DEF_FUNCTION_TYPE (V2DF, V4DF, INT)
+DEF_FUNCTION_TYPE (V2DF, V4DF, INT, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V8DF, INT)
+DEF_FUNCTION_TYPE (V2DF, V8DF, INT, V2DF, QI)
DEF_FUNCTION_TYPE (V2DI, V16QI, V16QI)
DEF_FUNCTION_TYPE (V2DI, V2DF, V2DF)
DEF_FUNCTION_TYPE (V2DI, V2DI, INT)
+DEF_FUNCTION_TYPE (V2DI, V2DI, INT, V2DI, QI)
DEF_FUNCTION_TYPE (V2DI, V2DI, SI)
DEF_FUNCTION_TYPE (V2DI, V2DI, V16QI)
DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI)
@@ -353,6 +412,7 @@ DEF_FUNCTION_TYPE (V2SI, V2SI, V2SI)
DEF_FUNCTION_TYPE (V2SI, V4HI, V4HI)
DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DI)
DEF_FUNCTION_TYPE (V4DF, V4DF, INT)
+DEF_FUNCTION_TYPE (V8DF, V8DF, INT)
DEF_FUNCTION_TYPE (V4DF, V8DF, INT)
DEF_FUNCTION_TYPE (V4DF, V8DF, INT, V4DF, QI)
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF)
@@ -377,25 +437,36 @@ DEF_FUNCTION_TYPE (V4SF, V4SF, V2SI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SI)
DEF_FUNCTION_TYPE (V4SF, V8SF, INT)
+DEF_FUNCTION_TYPE (V4SF, V8SF, INT, V4SF, QI)
DEF_FUNCTION_TYPE (V4SI, V2DF, V2DF)
+DEF_FUNCTION_TYPE (V4SI, V2DF, V4SI, QI)
DEF_FUNCTION_TYPE (V4SI, V4SF, V4SF)
DEF_FUNCTION_TYPE (V4SI, V4SI, INT)
+DEF_FUNCTION_TYPE (V4SI, V4SI, INT, V4SI, QI)
DEF_FUNCTION_TYPE (V4SI, V4SI, SI)
DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI)
DEF_FUNCTION_TYPE (V4SI, V8HI, V8HI)
+DEF_FUNCTION_TYPE (V4SI, V8HI, V8HI, V4SI, QI)
DEF_FUNCTION_TYPE (V4SI, V8SI, INT)
+DEF_FUNCTION_TYPE (V4SI, V8SI, INT, V4SI, QI)
DEF_FUNCTION_TYPE (V4SI, PCV4SI, V4SI)
DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI)
+DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI, V8HI, QI)
DEF_FUNCTION_TYPE (V8HI, V4SI, V4SI)
DEF_FUNCTION_TYPE (V8HI, V8HI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DI, INT)
DEF_FUNCTION_TYPE (V8HI, V8HI, SI)
DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI)
DEF_FUNCTION_TYPE (V8HI, V8SF, INT)
+DEF_FUNCTION_TYPE (V8HI, V8SF, INT, V8HI, QI)
DEF_FUNCTION_TYPE (V8HI, V4SF, INT)
+DEF_FUNCTION_TYPE (V8HI, V4SF, INT, V8HI, QI)
DEF_FUNCTION_TYPE (V8QI, V4HI, V4HI)
DEF_FUNCTION_TYPE (V8QI, V8QI, V8QI)
DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SI)
DEF_FUNCTION_TYPE (V8SF, V8SF, INT)
+DEF_FUNCTION_TYPE (V8SF, V16SF, INT)
+DEF_FUNCTION_TYPE (V8SF, V16SF, INT, V8SF, QI)
DEF_FUNCTION_TYPE (V16SF, V16SF, INT)
DEF_FUNCTION_TYPE (V4SF, V16SF, INT)
DEF_FUNCTION_TYPE (V4SF, V16SF, INT, V4SF, QI)
@@ -404,29 +475,46 @@ DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SI)
DEF_FUNCTION_TYPE (V32QI, V16HI, V16HI)
+DEF_FUNCTION_TYPE (V64QI, V32HI, V32HI)
DEF_FUNCTION_TYPE (V16HI, V8SI, V8SI)
+DEF_FUNCTION_TYPE (V32HI, V16SI, V16SI)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V2DF, INT)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V2DF, INT, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V4DF, INT, V8DF, QI)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, INT, V8DF, QI)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, INT, V8DF, QI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, INT, V8DF, QI)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DI, INT)
+DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DI, INT, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DI, INT, QI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DI, INT, QI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, INT, V16SF, HI)
+DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, INT, V16SF, HI, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, INT, V16SF, HI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V4SI, INT, V16SI, HI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SI, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SI, INT, HI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SI, INT, HI, INT)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SI, INT, QI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SI, INT, QI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SI, INT, QI, INT)
-DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT, QI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT, QI, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V4SF, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V4SF, INT, V16SF, HI)
+DEF_FUNCTION_TYPE (V16SF, V16SF, V8SF, INT, V16SF, HI)
DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI)
DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI)
+DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI)
+DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI, V16HI, HI)
+DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI, V32HI, SI)
DEF_FUNCTION_TYPE (V16HI, V16HI, V8HI)
DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, INT)
DEF_FUNCTION_TYPE (V16HI, V16HI, INT)
DEF_FUNCTION_TYPE (V16HI, V16SF, INT)
DEF_FUNCTION_TYPE (V16HI, V16SF, INT, V16HI, HI)
@@ -438,13 +526,20 @@ DEF_FUNCTION_TYPE (V8SI, V4DF, V4DF)
DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V4SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V4SI, INT)
+DEF_FUNCTION_TYPE (V16SI, V16SI, V8SI, INT, V16SI, HI)
DEF_FUNCTION_TYPE (V4SI, V16SI, INT)
DEF_FUNCTION_TYPE (V4SI, V16SI, INT, V4SI, QI)
DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, INT, V16SI, HI)
DEF_FUNCTION_TYPE (V8SI, V16HI, V16HI)
+DEF_FUNCTION_TYPE (V16SI, V32HI, V32HI)
+DEF_FUNCTION_TYPE (V8SI, V16HI, V16HI, V8SI, QI)
+DEF_FUNCTION_TYPE (V16SI, V32HI, V32HI, V16SI, HI)
DEF_FUNCTION_TYPE (V8SI, V8SI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SI, INT, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V16SI, INT)
+DEF_FUNCTION_TYPE (V8SI, V16SI, INT, V8SI, QI)
DEF_FUNCTION_TYPE (V8SI, V8SI, SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, SI)
DEF_FUNCTION_TYPE (V16SI, V16SI, INT)
@@ -455,9 +550,17 @@ DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI)
DEF_FUNCTION_TYPE (V16SI, V8DF, V8DF)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, INT, V8DI, QI)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, INT, V8DI, DI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT, V4DI, SI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT, V2DI, HI)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V4DI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI, INT, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V4DI, INT, V8DI, QI)
DEF_FUNCTION_TYPE (V4DI, V8SI, V8SI)
DEF_FUNCTION_TYPE (V4UDI, V8USI, V8USI)
+DEF_FUNCTION_TYPE (V8DI, V16SI, V16SI)
+DEF_FUNCTION_TYPE (V8DI, V64QI, V64QI)
DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI)
DEF_FUNCTION_TYPE (V4DI, PCV4DI, V4DI)
@@ -466,8 +569,12 @@ DEF_FUNCTION_TYPE (V4DI, V8DI, INT, V4DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V2DI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8DI, INT, V8DI, QI)
DEF_FUNCTION_TYPE (V4DI, V4DI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, INT, V4DI, QI)
DEF_FUNCTION_TYPE (V2DI, V4DI, INT)
DEF_FUNCTION_TYPE (VOID, PVOID, INT64)
+DEF_FUNCTION_TYPE (V2DI, V4DI, INT, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V8DI, INT)
+DEF_FUNCTION_TYPE (V2DI, V8DI, INT, V2DI, QI)
DEF_FUNCTION_TYPE (VOID, PCHAR, V16QI)
DEF_FUNCTION_TYPE (VOID, PCHAR, V32QI)
DEF_FUNCTION_TYPE (VOID, PDOUBLE, V2DF)
@@ -489,9 +596,72 @@ DEF_FUNCTION_TYPE (VOID, UNSIGNED, UNSIGNED)
DEF_FUNCTION_TYPE (VOID, PV8DI, V8DI)
# Instructions returning mask
+DEF_FUNCTION_TYPE (QI, QI)
DEF_FUNCTION_TYPE (HI, HI)
+DEF_FUNCTION_TYPE (SI, SI)
+DEF_FUNCTION_TYPE (DI, DI)
+DEF_FUNCTION_TYPE (HI, V16QI)
+DEF_FUNCTION_TYPE (SI, V32QI)
+DEF_FUNCTION_TYPE (DI, V64QI)
+DEF_FUNCTION_TYPE (QI, V8HI)
+DEF_FUNCTION_TYPE (HI, V16HI)
+DEF_FUNCTION_TYPE (SI, V32HI)
+DEF_FUNCTION_TYPE (QI, V4SI)
+DEF_FUNCTION_TYPE (QI, V8SI)
+DEF_FUNCTION_TYPE (HI, V16SI)
+DEF_FUNCTION_TYPE (QI, V2DI)
+DEF_FUNCTION_TYPE (QI, V4DI)
+DEF_FUNCTION_TYPE (QI, V8DI)
+DEF_FUNCTION_TYPE (V16QI, HI)
+DEF_FUNCTION_TYPE (V32QI, SI)
+DEF_FUNCTION_TYPE (V64QI, DI)
+DEF_FUNCTION_TYPE (V8HI, QI)
+DEF_FUNCTION_TYPE (V16HI, HI)
+DEF_FUNCTION_TYPE (V32HI, SI)
+DEF_FUNCTION_TYPE (V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, HI)
+DEF_FUNCTION_TYPE (V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, HI)
+DEF_FUNCTION_TYPE (V2DI, QI)
+DEF_FUNCTION_TYPE (V4DI, QI)
+DEF_FUNCTION_TYPE (QI, QI, QI)
DEF_FUNCTION_TYPE (HI, HI, HI)
+DEF_FUNCTION_TYPE (SI, SI, SI)
+DEF_FUNCTION_TYPE (DI, DI, DI)
+DEF_FUNCTION_TYPE (QI, QI, INT)
DEF_FUNCTION_TYPE (HI, HI, INT)
+DEF_FUNCTION_TYPE (SI, SI, INT)
+DEF_FUNCTION_TYPE (DI, DI, INT)
+DEF_FUNCTION_TYPE (HI, V16QI, V16QI)
+DEF_FUNCTION_TYPE (HI, V16QI, V16QI, HI)
+DEF_FUNCTION_TYPE (HI, V16QI, V16QI, INT, HI)
+DEF_FUNCTION_TYPE (SI, V32QI, V32QI)
+DEF_FUNCTION_TYPE (SI, V32QI, V32QI, SI)
+DEF_FUNCTION_TYPE (SI, V32QI, V32QI, INT, SI)
+DEF_FUNCTION_TYPE (DI, V64QI, V64QI)
+DEF_FUNCTION_TYPE (DI, V64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (DI, V64QI, V64QI, INT, DI)
+DEF_FUNCTION_TYPE (QI, V8HI, V8HI)
+DEF_FUNCTION_TYPE (QI, V8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (QI, V8HI, V8HI, INT, QI)
+DEF_FUNCTION_TYPE (HI, V16HI, V16HI)
+DEF_FUNCTION_TYPE (HI, V16HI, V16HI, HI)
+DEF_FUNCTION_TYPE (HI, V16HI, V16HI, INT, HI)
+DEF_FUNCTION_TYPE (SI, V32HI, V32HI)
+DEF_FUNCTION_TYPE (SI, V32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (SI, V32HI, V32HI, INT, SI)
+DEF_FUNCTION_TYPE (QI, V4SI, V4SI)
+DEF_FUNCTION_TYPE (QI, V4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (QI, V4SI, V4SI, INT, QI)
+DEF_FUNCTION_TYPE (QI, V8SI, V8SI)
+DEF_FUNCTION_TYPE (QI, V8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (QI, V8SI, V8SI, INT, QI)
+DEF_FUNCTION_TYPE (QI, V2DI, V2DI)
+DEF_FUNCTION_TYPE (QI, V2DI, V2DI, QI)
+DEF_FUNCTION_TYPE (QI, V2DI, V2DI, INT, QI)
+DEF_FUNCTION_TYPE (QI, V4DI, V4DI)
+DEF_FUNCTION_TYPE (QI, V4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (QI, V4DI, V4DI, INT, QI)
DEF_FUNCTION_TYPE (QI, V8DI, V8DI)
DEF_FUNCTION_TYPE (QI, V8DI, V8DI, QI)
DEF_FUNCTION_TYPE (HI, V16SI, V16SI)
@@ -518,6 +688,7 @@ DEF_FUNCTION_TYPE (V8DI, QI)
DEF_FUNCTION_TYPE (INT, V16QI, V16QI, INT)
DEF_FUNCTION_TYPE (UCHAR, UINT, UINT, UINT)
DEF_FUNCTION_TYPE (UCHAR, UINT64, UINT, UINT)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, V32HI)
DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, V16HI)
DEF_FUNCTION_TYPE (V16QI, V16QI, QI, INT)
DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, INT)
@@ -525,7 +696,10 @@ DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, V16QI)
DEF_FUNCTION_TYPE (V1DI, V1DI, V1DI, INT)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI, INT)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DF)
+DEF_FUNCTION_TYPE (V2DF, V2DI, V2DF, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DI, V2DF, QI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DI, INT)
DEF_FUNCTION_TYPE (V2DI, V2DI, DI, INT)
DEF_FUNCTION_TYPE (V2DI, V2DI, UINT, UINT)
@@ -533,9 +707,11 @@ DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT)
DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI)
DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, V32QI)
DEF_FUNCTION_TYPE (V4DF, V4DF, V2DF, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V2DF, INT, V4DF, QI)
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, INT)
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DF)
DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, INT)
DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V4DI)
DEF_FUNCTION_TYPE (V4HI, V4HI, HI, INT)
DEF_FUNCTION_TYPE (V4SF, V4SF, FLOAT, INT)
@@ -544,6 +720,10 @@ DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, INT, INT)
DEF_FUNCTION_TYPE (V4SF, V4SF, V2DF, INT)
DEF_FUNCTION_TYPE (V2DF, V2DF, V4SF, INT)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF)
+DEF_FUNCTION_TYPE (V4SF, V4SI, V4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SI, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V2DF, V4SF, QI)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SI, INT)
DEF_FUNCTION_TYPE (V4SI, V4SI, SI, INT)
DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, INT)
@@ -554,76 +734,263 @@ DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, INT)
DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, V4SI)
DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, V8HI)
DEF_FUNCTION_TYPE (V8SF, V8SF, V4SF, INT)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V4SF, INT, V8SF, QI)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, INT)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SF)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DF)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SF)
DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI, INT, V8SI, QI)
DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, INT)
DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI)
DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT)
DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI, INT, V4DI, QI)
# Instructions with masking
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V4SF, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V4SI, V2DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4SF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4SI, V4DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8SF, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8SI, V8DF, QI)
+DEF_FUNCTION_TYPE (V2DI, V4SI, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V8HI, V2DI, QI)
+DEF_FUNCTION_TYPE (V8DI, V8DF, V8DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DF, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DF, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, INT, V2DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, INT, V4DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8SI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8HI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, V16QI, V8DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V16QI, V2DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V16QI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4SI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V8HI, V4DI, QI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, V8DF)
DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DI, V8DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DI, V4DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DF, QI)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DF, QI)
+DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, V16QI, HI)
+DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, V16HI, HI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI, HI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, V2DF, QI)
DEF_FUNCTION_TYPE (V2DF, V2DF, V4SF, V2DF, QI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, V32QI, SI)
+DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SI, V4SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SI, V8SF, QI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, HI)
DEF_FUNCTION_TYPE (V16SF, V16SI, V16SF, HI)
+DEF_FUNCTION_TYPE (V4SI, V16QI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V8HI, V4SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V8HI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V16QI, V8SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, INT, V4SI, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SI, V8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, INT, V8SI, QI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SF, HI)
DEF_FUNCTION_TYPE (V16SF, V16SI, V16SF, V16SF)
DEF_FUNCTION_TYPE (V16SF, V16SI, V16SF, V16SF, HI)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SI, V16SF, HI)
-DEF_FUNCTION_TYPE (V4SF, V4SF, V2DF, V4SF, QI)
-DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V16SF, V8SF, V16SF, HI)
DEF_FUNCTION_TYPE (V16SF, V4SF, V16SF, HI)
DEF_FUNCTION_TYPE (V8DF, V4DF, V8DF, QI)
DEF_FUNCTION_TYPE (V8DF, V2DF, V8DF, QI)
+DEF_FUNCTION_TYPE (V16SI, V8SI, V16SI, HI)
DEF_FUNCTION_TYPE (V16SI, V4SI, V16SI, HI)
DEF_FUNCTION_TYPE (V16SI, SI, V16SI, HI)
DEF_FUNCTION_TYPE (V16SI, V16HI, V16SI, HI)
DEF_FUNCTION_TYPE (V16SI, V16QI, V16SI, HI)
DEF_FUNCTION_TYPE (V8SI, V8DF, V8SI, QI)
DEF_FUNCTION_TYPE (V8DI, V4DI, V8DI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4DF, V4SI, QI)
DEF_FUNCTION_TYPE (V8DI, V2DI, V8DI, QI)
DEF_FUNCTION_TYPE (V8DI, DI, V8DI, QI)
+DEF_FUNCTION_TYPE (V8DI, PCCHAR, V8DI, QI)
+DEF_FUNCTION_TYPE (V8SF, PCFLOAT, V8SF, QI)
+DEF_FUNCTION_TYPE (V4SF, PCFLOAT, V4SF, QI)
+DEF_FUNCTION_TYPE (V4DF, PCDOUBLE, V4DF, QI)
+DEF_FUNCTION_TYPE (V2DF, PCDOUBLE, V2DF, QI)
+DEF_FUNCTION_TYPE (V8SI, PCCHAR, V8SI, QI)
+DEF_FUNCTION_TYPE (V4SI, PCCHAR, V4SI, QI)
+DEF_FUNCTION_TYPE (V4DI, PCCHAR, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, PCCHAR, V2DI, QI)
+DEF_FUNCTION_TYPE (V16QI, V16SI, V16QI, HI)
+DEF_FUNCTION_TYPE (V16QI, V8DI, V16QI, QI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI, INT)
+DEF_FUNCTION_TYPE (V32HI, V32QI, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V16HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI, INT)
+DEF_FUNCTION_TYPE (V16HI, V16QI, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V16QI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI, INT)
+DEF_FUNCTION_TYPE (V8SF, V4SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V4DF, V2DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V8SI, V4SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, SI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4DI, V2DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, QI)
+DEF_FUNCTION_TYPE (V2DI, DI, V2DI, QI)
+DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V64QI, V16QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V64QI, QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, SI)
+DEF_FUNCTION_TYPE (V32QI, V16QI, V32QI, SI)
+DEF_FUNCTION_TYPE (V32QI, QI, V32QI, SI)
+DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, HI)
+DEF_FUNCTION_TYPE (V16QI, QI, V16QI, HI)
+DEF_FUNCTION_TYPE (V32HI, V8HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V32HI, HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V8HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V16HI, HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8HI, HI, V8HI, QI)
+DEF_FUNCTION_TYPE (V64QI, PCV64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (V32HI, PCV32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V32QI, PCV32QI, V32QI, SI)
DEF_FUNCTION_TYPE (V16SF, PCV16SF, V16SF, HI)
+DEF_FUNCTION_TYPE (V16SF, PCV8SF, V16SF, HI)
DEF_FUNCTION_TYPE (V8DF, PCV8DF, V8DF, QI)
DEF_FUNCTION_TYPE (V16SI, PCV16SI, V16SI, HI)
+DEF_FUNCTION_TYPE (V16SI, PCV8SI, V16SI, HI)
+DEF_FUNCTION_TYPE (V16HI, PCV16HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V16QI, PCV16QI, V16QI, HI)
+DEF_FUNCTION_TYPE (V8DF, PCV2DF, V8DF, QI)
+DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (V8SF, PCV4SF, V8SF, QI)
DEF_FUNCTION_TYPE (V8DI, PCV8DI, V8DI, QI)
-DEF_FUNCTION_TYPE (V2DF, PCDOUBLE, V2DF, QI)
-DEF_FUNCTION_TYPE (V4SF, PCFLOAT, V4SF, QI)
-DEF_FUNCTION_TYPE (V16QI, V16SI, V16QI, HI)
+DEF_FUNCTION_TYPE (V8DI, PCV2DI, V8DI, QI)
+DEF_FUNCTION_TYPE (V8SI, PCV8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8SI, PCV4SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V8HI, PCV8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (V4DF, PCV2DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DF, QI)
+DEF_FUNCTION_TYPE (V4SF, PCV4SF, V4SF, QI)
+DEF_FUNCTION_TYPE (V4DI, PCV4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4DI, PCV2DI, V4DI, QI)
+DEF_FUNCTION_TYPE (V4SI, PCV4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (V2DF, PCV2DF, V2DF, QI)
+DEF_FUNCTION_TYPE (V2DI, PCV2DI, V2DI, QI)
DEF_FUNCTION_TYPE (V16HI, V16SI, V16HI, HI)
DEF_FUNCTION_TYPE (V8SI, V8DI, V8SI, QI)
DEF_FUNCTION_TYPE (V8HI, V8DI, V8HI, QI)
-DEF_FUNCTION_TYPE (V16QI, V8DI, V16QI, QI)
+DEF_FUNCTION_TYPE (V16QI, V8HI, V16QI, QI)
+DEF_FUNCTION_TYPE (V16QI, V16HI, V16QI, HI)
+DEF_FUNCTION_TYPE (V16QI, V4SI, V16QI, QI)
+DEF_FUNCTION_TYPE (V16QI, V8SI, V16QI, QI)
+DEF_FUNCTION_TYPE (V8HI, V4SI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8HI, V8SI, V8HI, QI)
+DEF_FUNCTION_TYPE (V16QI, V2DI, V16QI, QI)
+DEF_FUNCTION_TYPE (V16QI, V4DI, V16QI, QI)
+DEF_FUNCTION_TYPE (V8HI, V2DI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8HI, V4DI, V8HI, QI)
+DEF_FUNCTION_TYPE (V4SI, V2DI, V4SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4DI, V4SI, QI)
+DEF_FUNCTION_TYPE (V32QI, V32HI, V32QI, SI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, INT, V2DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, INT, V4DF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, INT, V4SF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, INT, V8SF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, INT, V4DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT, V2DF, QI)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, INT, V8SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, INT, V4SF, QI)
DEF_FUNCTION_TYPE (VOID, PV8DF, V8DF, QI)
DEF_FUNCTION_TYPE (VOID, PV8SI, V8DI, QI)
DEF_FUNCTION_TYPE (VOID, PV8HI, V8DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V4DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V2DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4SI, V4DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4SI, V2DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V8SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V4SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4DF, V4DF, QI)
+DEF_FUNCTION_TYPE (VOID, PV2DF, V2DF, QI)
DEF_FUNCTION_TYPE (VOID, PV16SF, V16SF, HI)
+DEF_FUNCTION_TYPE (VOID, PV8SF, V8SF, QI)
+DEF_FUNCTION_TYPE (VOID, PV4SF, V4SF, QI)
DEF_FUNCTION_TYPE (VOID, PV8DI, V8DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4DI, V4DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV2DI, V2DI, QI)
DEF_FUNCTION_TYPE (VOID, PV16SI, V16SI, HI)
DEF_FUNCTION_TYPE (VOID, PV16HI, V16SI, HI)
DEF_FUNCTION_TYPE (VOID, PV16QI, V16SI, HI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V8SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V4SI, QI)
DEF_FUNCTION_TYPE (VOID, PV16QI, V8DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V4DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V2DI, QI)
+DEF_FUNCTION_TYPE (VOID, PV8SI, V8SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV4SI, V4SI, QI)
+DEF_FUNCTION_TYPE (VOID, PV32HI, V32HI, SI)
+DEF_FUNCTION_TYPE (VOID, PV16HI, V16HI, HI)
+DEF_FUNCTION_TYPE (VOID, PV8HI, V8HI, QI)
+DEF_FUNCTION_TYPE (VOID, PV64QI, V64QI, DI)
+DEF_FUNCTION_TYPE (VOID, PV32QI, V32QI, SI)
+DEF_FUNCTION_TYPE (VOID, PV16QI, V16QI, HI)
DEF_FUNCTION_TYPE (VOID, PDOUBLE, V2DF, QI)
DEF_FUNCTION_TYPE (VOID, PFLOAT, V4SF, QI)
DEF_FUNCTION_TYPE (V16SI, V16SF, V16SI, HI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI, INT, QI)
+DEF_FUNCTION_TYPE (V8SI, V8SF, V8SI, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SF, V4SI, QI)
+DEF_FUNCTION_TYPE (V8DI, V8SF, V8DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4SF, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V4SF, V2DI, QI)
+DEF_FUNCTION_TYPE (V8SF, V8DI, V8SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V4DI, V4SF, QI)
+DEF_FUNCTION_TYPE (V4SF, V2DI, V4SF, QI)
+DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, QI)
+DEF_FUNCTION_TYPE (V4DF, V4DI, V4DF, QI)
+DEF_FUNCTION_TYPE (V2DF, V2DI, V2DF, QI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, INT, V32HI, SI)
+DEF_FUNCTION_TYPE (V32HI, V32HI, V8HI, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V16HI, INT, V16HI, HI)
+DEF_FUNCTION_TYPE (V16HI, V16HI, V8HI, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V8HI, INT, V8HI, QI)
+DEF_FUNCTION_TYPE (V32HI, V64QI, V64QI, INT, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V32QI, V32QI, INT, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V16QI, V16QI, INT, V8HI, QI)
+DEF_FUNCTION_TYPE (V64QI, V32HI, V32HI, V64QI, DI)
+DEF_FUNCTION_TYPE (V32QI, V16HI, V16HI, V32QI, SI)
+DEF_FUNCTION_TYPE (V16QI, V8HI, V8HI, V16QI, HI)
+DEF_FUNCTION_TYPE (V32HI, V16SI, V16SI, V32HI, SI)
+DEF_FUNCTION_TYPE (V16HI, V8SI, V8SI, V16HI, HI)
+DEF_FUNCTION_TYPE (V8HI, V4SI, V4SI, V8HI, QI)
+DEF_FUNCTION_TYPE (V8DI, V16SI, V16SI, V8DI, QI)
+DEF_FUNCTION_TYPE (V4DI, V8SI, V8SI, V4DI, QI)
+DEF_FUNCTION_TYPE (V2DI, V4SI, V4SI, V2DI, QI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI, INT, HI)
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI, INT, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V4DI, INT, QI)
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT, QI)
+DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, V2DI, INT, QI)
DEF_FUNCTION_TYPE (VOID, PCVOID, UNSIGNED, UNSIGNED)
DEF_FUNCTION_TYPE (VOID, PV2DF, V2DI, V2DF)
@@ -648,11 +1015,30 @@ DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF, V4DI)
DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SI)
DEF_FUNCTION_TYPE (V8DI, V8DI, V8DI, V8DI)
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI)
+DEF_FUNCTION_TYPE (V2DF, V2DF, V2DI, V2DF)
+DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI, V4DF)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DI, V8DF)
+DEF_FUNCTION_TYPE (V4SF, V4SF, V4SI, V4SF)
+DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI, V8SF)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SI, V16SF)
-DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, INT, V4SF, QI)
-DEF_FUNCTION_TYPE (V2DF, V2DF, V2DF, INT, V2DF, QI)
-DEF_FUNCTION_TYPE (V8DI, V16SI, V16SI, V8DI, QI)
+
+DEF_FUNCTION_TYPE (V8SI, V8SI, V4SI, V8SI, QI)
+DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI, V4DI, QI)
+
+DEF_FUNCTION_TYPE (QI, V8DF, INT)
+DEF_FUNCTION_TYPE (QI, V4DF, INT)
+DEF_FUNCTION_TYPE (QI, V4DF, V4DF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V2DF, INT)
+DEF_FUNCTION_TYPE (HI, V16SF, INT)
+DEF_FUNCTION_TYPE (QI, V8SF, INT)
+DEF_FUNCTION_TYPE (QI, V8SF, V8SF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V4SF, INT)
+DEF_FUNCTION_TYPE (QI, V8DF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V4DF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V2DF, INT, QI)
+DEF_FUNCTION_TYPE (HI, V16SF, INT, HI)
+DEF_FUNCTION_TYPE (QI, V8SF, INT, QI)
+DEF_FUNCTION_TYPE (QI, V4SF, INT, QI)
DEF_FUNCTION_TYPE (V2DI, V2DI, V2DI, UINT, UINT)
DEF_FUNCTION_TYPE (V4HI, HI, HI, HI, HI)
@@ -688,6 +1074,10 @@ DEF_FUNCTION_TYPE (V8SI, V8DF, V8SI, QI, INT)
DEF_FUNCTION_TYPE (V8SF, V8DF, V8SF, QI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, QI, INT)
DEF_FUNCTION_TYPE (V8DF, V8SF, V8DF, QI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8DF, V8DI, QI, INT)
+DEF_FUNCTION_TYPE (V8DI, V8SF, V8DI, QI, INT)
+DEF_FUNCTION_TYPE (V8DF, V8DI, V8DF, QI, INT)
+DEF_FUNCTION_TYPE (V8SF, V8DI, V8SF, QI, INT)
DEF_FUNCTION_TYPE (V16SF, V16SF, V16SF, V16SF, HI, INT)
DEF_FUNCTION_TYPE (V8DF, V8DF, V8DF, V8DF, QI, INT)
DEF_FUNCTION_TYPE (V4SF, V4SF, V4SF, V4SF, QI, INT)
@@ -736,16 +1126,53 @@ DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V8SI, QI, INT)
DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V16SI, QI, INT)
DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V8DI, QI, INT)
DEF_FUNCTION_TYPE (V8DI, V8DI, PCINT64, V8DI, QI, INT)
+DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V8SI, QI, INT)
+DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE, V2DI, QI, INT)
+DEF_FUNCTION_TYPE (V4DF, V4DF, PCDOUBLE, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V8SF, V8SF, PCFLOAT, V8SI, QI, INT)
+DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V2DI, QI, INT)
+DEF_FUNCTION_TYPE (V4SF, V4SF, PCFLOAT, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V8SF, V8SF, PCFLOAT, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V2DI, V2DI, PCINT64, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V8SI, QI, INT)
+DEF_FUNCTION_TYPE (V2DI, V2DI, PCINT64, V2DI, QI, INT)
+DEF_FUNCTION_TYPE (V4DI, V4DI, PCINT64, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V4SI, QI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V8SI, QI, INT)
+DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V2DI, QI, INT)
+DEF_FUNCTION_TYPE (V4SI, V4SI, PCINT, V4DI, QI, INT)
+DEF_FUNCTION_TYPE (V8SI, V8SI, PCINT, V4DI, QI, INT)
+
DEF_FUNCTION_TYPE (VOID, PFLOAT, HI, V16SI, V16SF, INT)
+DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V8SI, V8SF, INT)
+DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V4SI, V4SF, INT)
DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V8SI, V8DF, INT)
+DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4SI, V4DF, INT)
+DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4SI, V2DF, INT)
DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V8DI, V8SF, INT)
+DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V4DI, V4SF, INT)
+DEF_FUNCTION_TYPE (VOID, PFLOAT, QI, V2DI, V4SF, INT)
DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V8DI, V8DF, INT)
+DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V4DI, V4DF, INT)
+DEF_FUNCTION_TYPE (VOID, PDOUBLE, QI, V2DI, V2DF, INT)
DEF_FUNCTION_TYPE (VOID, PINT, HI, V16SI, V16SI, INT)
+DEF_FUNCTION_TYPE (VOID, PINT, QI, V8SI, V8SI, INT)
+DEF_FUNCTION_TYPE (VOID, PINT, QI, V4SI, V4SI, INT)
DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V8SI, V8DI, INT)
+DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4SI, V4DI, INT)
+DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4SI, V2DI, INT)
DEF_FUNCTION_TYPE (VOID, PINT, QI, V8DI, V8SI, INT)
+DEF_FUNCTION_TYPE (VOID, PINT, QI, V4DI, V4SI, INT)
+DEF_FUNCTION_TYPE (VOID, PINT, QI, V2DI, V4SI, INT)
DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V8DI, V8DI, INT)
DEF_FUNCTION_TYPE (VOID, QI, V8SI, PCINT64, INT, INT)
+DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V4DI, V4DI, INT)
+DEF_FUNCTION_TYPE (VOID, PLONGLONG, QI, V2DI, V2DI, INT)
DEF_FUNCTION_TYPE (VOID, HI, V16SI, PCINT, INT, INT)
DEF_FUNCTION_TYPE (VOID, QI, V8DI, PCINT64, INT, INT)
DEF_FUNCTION_TYPE (VOID, QI, V8DI, PCINT, INT, INT)
@@ -793,8 +1220,13 @@ DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_V2DI, COUNT)
DEF_FUNCTION_TYPE_ALIAS (V2DF_FTYPE_V2DF_V2DF, SWAP)
DEF_FUNCTION_TYPE_ALIAS (V4SF_FTYPE_V4SF_V4SF, SWAP)
+DEF_FUNCTION_TYPE_ALIAS (V8DI_FTYPE_V8DI_INT, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_INT, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V2DI_FTYPE_V2DI_INT, CONVERT)
+DEF_FUNCTION_TYPE_ALIAS (V8DI_FTYPE_V8DI_V8DI_INT, CONVERT)
+DEF_FUNCTION_TYPE_ALIAS (V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI, CONVERT)
+DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI, CONVERT)
+DEF_FUNCTION_TYPE_ALIAS (V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V4DI_FTYPE_V4DI_V4DI_INT, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V2DI_FTYPE_V2DI_V2DI_INT, CONVERT)
DEF_FUNCTION_TYPE_ALIAS (V1DI_FTYPE_V1DI_V1DI_INT, CONVERT)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index ec3e056..ca8094b 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -28650,6 +28650,995 @@ enum ix86_builtins
IX86_BUILTIN_KXOR16,
IX86_BUILTIN_KMOV16,
+ /* AVX512VL. */
+ IX86_BUILTIN_PMOVUSQD256_MEM,
+ IX86_BUILTIN_PMOVUSQD128_MEM,
+ IX86_BUILTIN_PMOVSQD256_MEM,
+ IX86_BUILTIN_PMOVSQD128_MEM,
+ IX86_BUILTIN_PMOVQD256_MEM,
+ IX86_BUILTIN_PMOVQD128_MEM,
+ IX86_BUILTIN_PMOVUSQW256_MEM,
+ IX86_BUILTIN_PMOVUSQW128_MEM,
+ IX86_BUILTIN_PMOVSQW256_MEM,
+ IX86_BUILTIN_PMOVSQW128_MEM,
+ IX86_BUILTIN_PMOVQW256_MEM,
+ IX86_BUILTIN_PMOVQW128_MEM,
+ IX86_BUILTIN_PMOVUSQB256_MEM,
+ IX86_BUILTIN_PMOVUSQB128_MEM,
+ IX86_BUILTIN_PMOVSQB256_MEM,
+ IX86_BUILTIN_PMOVSQB128_MEM,
+ IX86_BUILTIN_PMOVQB256_MEM,
+ IX86_BUILTIN_PMOVQB128_MEM,
+ IX86_BUILTIN_PMOVUSDW256_MEM,
+ IX86_BUILTIN_PMOVUSDW128_MEM,
+ IX86_BUILTIN_PMOVSDW256_MEM,
+ IX86_BUILTIN_PMOVSDW128_MEM,
+ IX86_BUILTIN_PMOVDW256_MEM,
+ IX86_BUILTIN_PMOVDW128_MEM,
+ IX86_BUILTIN_PMOVUSDB256_MEM,
+ IX86_BUILTIN_PMOVUSDB128_MEM,
+ IX86_BUILTIN_PMOVSDB256_MEM,
+ IX86_BUILTIN_PMOVSDB128_MEM,
+ IX86_BUILTIN_PMOVDB256_MEM,
+ IX86_BUILTIN_PMOVDB128_MEM,
+ IX86_BUILTIN_MOVDQA64LOAD256_MASK,
+ IX86_BUILTIN_MOVDQA64LOAD128_MASK,
+ IX86_BUILTIN_MOVDQA32LOAD256_MASK,
+ IX86_BUILTIN_MOVDQA32LOAD128_MASK,
+ IX86_BUILTIN_MOVDQA64STORE256_MASK,
+ IX86_BUILTIN_MOVDQA64STORE128_MASK,
+ IX86_BUILTIN_MOVDQA32STORE256_MASK,
+ IX86_BUILTIN_MOVDQA32STORE128_MASK,
+ IX86_BUILTIN_LOADAPD256_MASK,
+ IX86_BUILTIN_LOADAPD128_MASK,
+ IX86_BUILTIN_LOADAPS256_MASK,
+ IX86_BUILTIN_LOADAPS128_MASK,
+ IX86_BUILTIN_STOREAPD256_MASK,
+ IX86_BUILTIN_STOREAPD128_MASK,
+ IX86_BUILTIN_STOREAPS256_MASK,
+ IX86_BUILTIN_STOREAPS128_MASK,
+ IX86_BUILTIN_LOADUPD256_MASK,
+ IX86_BUILTIN_LOADUPD128_MASK,
+ IX86_BUILTIN_LOADUPS256_MASK,
+ IX86_BUILTIN_LOADUPS128_MASK,
+ IX86_BUILTIN_STOREUPD256_MASK,
+ IX86_BUILTIN_STOREUPD128_MASK,
+ IX86_BUILTIN_STOREUPS256_MASK,
+ IX86_BUILTIN_STOREUPS128_MASK,
+ IX86_BUILTIN_LOADDQUDI256_MASK,
+ IX86_BUILTIN_LOADDQUDI128_MASK,
+ IX86_BUILTIN_LOADDQUSI256_MASK,
+ IX86_BUILTIN_LOADDQUSI128_MASK,
+ IX86_BUILTIN_LOADDQUHI256_MASK,
+ IX86_BUILTIN_LOADDQUHI128_MASK,
+ IX86_BUILTIN_LOADDQUQI256_MASK,
+ IX86_BUILTIN_LOADDQUQI128_MASK,
+ IX86_BUILTIN_STOREDQUDI256_MASK,
+ IX86_BUILTIN_STOREDQUDI128_MASK,
+ IX86_BUILTIN_STOREDQUSI256_MASK,
+ IX86_BUILTIN_STOREDQUSI128_MASK,
+ IX86_BUILTIN_STOREDQUHI256_MASK,
+ IX86_BUILTIN_STOREDQUHI128_MASK,
+ IX86_BUILTIN_STOREDQUQI256_MASK,
+ IX86_BUILTIN_STOREDQUQI128_MASK,
+ IX86_BUILTIN_COMPRESSPDSTORE256,
+ IX86_BUILTIN_COMPRESSPDSTORE128,
+ IX86_BUILTIN_COMPRESSPSSTORE256,
+ IX86_BUILTIN_COMPRESSPSSTORE128,
+ IX86_BUILTIN_PCOMPRESSQSTORE256,
+ IX86_BUILTIN_PCOMPRESSQSTORE128,
+ IX86_BUILTIN_PCOMPRESSDSTORE256,
+ IX86_BUILTIN_PCOMPRESSDSTORE128,
+ IX86_BUILTIN_EXPANDPDLOAD256,
+ IX86_BUILTIN_EXPANDPDLOAD128,
+ IX86_BUILTIN_EXPANDPSLOAD256,
+ IX86_BUILTIN_EXPANDPSLOAD128,
+ IX86_BUILTIN_PEXPANDQLOAD256,
+ IX86_BUILTIN_PEXPANDQLOAD128,
+ IX86_BUILTIN_PEXPANDDLOAD256,
+ IX86_BUILTIN_PEXPANDDLOAD128,
+ IX86_BUILTIN_EXPANDPDLOAD256Z,
+ IX86_BUILTIN_EXPANDPDLOAD128Z,
+ IX86_BUILTIN_EXPANDPSLOAD256Z,
+ IX86_BUILTIN_EXPANDPSLOAD128Z,
+ IX86_BUILTIN_PEXPANDQLOAD256Z,
+ IX86_BUILTIN_PEXPANDQLOAD128Z,
+ IX86_BUILTIN_PEXPANDDLOAD256Z,
+ IX86_BUILTIN_PEXPANDDLOAD128Z,
+ IX86_BUILTIN_PALIGNR256_MASK,
+ IX86_BUILTIN_PALIGNR128_MASK,
+ IX86_BUILTIN_MOVDQA64_256_MASK,
+ IX86_BUILTIN_MOVDQA64_128_MASK,
+ IX86_BUILTIN_MOVDQA32_256_MASK,
+ IX86_BUILTIN_MOVDQA32_128_MASK,
+ IX86_BUILTIN_MOVAPD256_MASK,
+ IX86_BUILTIN_MOVAPD128_MASK,
+ IX86_BUILTIN_MOVAPS256_MASK,
+ IX86_BUILTIN_MOVAPS128_MASK,
+ IX86_BUILTIN_MOVDQUHI256_MASK,
+ IX86_BUILTIN_MOVDQUHI128_MASK,
+ IX86_BUILTIN_MOVDQUQI256_MASK,
+ IX86_BUILTIN_MOVDQUQI128_MASK,
+ IX86_BUILTIN_MINPS128_MASK,
+ IX86_BUILTIN_MAXPS128_MASK,
+ IX86_BUILTIN_MINPD128_MASK,
+ IX86_BUILTIN_MAXPD128_MASK,
+ IX86_BUILTIN_MAXPD256_MASK,
+ IX86_BUILTIN_MAXPS256_MASK,
+ IX86_BUILTIN_MINPD256_MASK,
+ IX86_BUILTIN_MINPS256_MASK,
+ IX86_BUILTIN_MULPS128_MASK,
+ IX86_BUILTIN_DIVPS128_MASK,
+ IX86_BUILTIN_MULPD128_MASK,
+ IX86_BUILTIN_DIVPD128_MASK,
+ IX86_BUILTIN_DIVPD256_MASK,
+ IX86_BUILTIN_DIVPS256_MASK,
+ IX86_BUILTIN_MULPD256_MASK,
+ IX86_BUILTIN_MULPS256_MASK,
+ IX86_BUILTIN_ADDPD128_MASK,
+ IX86_BUILTIN_ADDPD256_MASK,
+ IX86_BUILTIN_ADDPS128_MASK,
+ IX86_BUILTIN_ADDPS256_MASK,
+ IX86_BUILTIN_SUBPD128_MASK,
+ IX86_BUILTIN_SUBPD256_MASK,
+ IX86_BUILTIN_SUBPS128_MASK,
+ IX86_BUILTIN_SUBPS256_MASK,
+ IX86_BUILTIN_XORPD256_MASK,
+ IX86_BUILTIN_XORPD128_MASK,
+ IX86_BUILTIN_XORPS256_MASK,
+ IX86_BUILTIN_XORPS128_MASK,
+ IX86_BUILTIN_ORPD256_MASK,
+ IX86_BUILTIN_ORPD128_MASK,
+ IX86_BUILTIN_ORPS256_MASK,
+ IX86_BUILTIN_ORPS128_MASK,
+ IX86_BUILTIN_BROADCASTF32x2_256,
+ IX86_BUILTIN_BROADCASTI32x2_256,
+ IX86_BUILTIN_BROADCASTI32x2_128,
+ IX86_BUILTIN_BROADCASTF64X2_256,
+ IX86_BUILTIN_BROADCASTI64X2_256,
+ IX86_BUILTIN_BROADCASTF32X4_256,
+ IX86_BUILTIN_BROADCASTI32X4_256,
+ IX86_BUILTIN_EXTRACTF32X4_256,
+ IX86_BUILTIN_EXTRACTI32X4_256,
+ IX86_BUILTIN_DBPSADBW256,
+ IX86_BUILTIN_DBPSADBW128,
+ IX86_BUILTIN_CVTTPD2QQ256,
+ IX86_BUILTIN_CVTTPD2QQ128,
+ IX86_BUILTIN_CVTTPD2UQQ256,
+ IX86_BUILTIN_CVTTPD2UQQ128,
+ IX86_BUILTIN_CVTPD2QQ256,
+ IX86_BUILTIN_CVTPD2QQ128,
+ IX86_BUILTIN_CVTPD2UQQ256,
+ IX86_BUILTIN_CVTPD2UQQ128,
+ IX86_BUILTIN_CVTPD2UDQ256_MASK,
+ IX86_BUILTIN_CVTPD2UDQ128_MASK,
+ IX86_BUILTIN_CVTTPS2QQ256,
+ IX86_BUILTIN_CVTTPS2QQ128,
+ IX86_BUILTIN_CVTTPS2UQQ256,
+ IX86_BUILTIN_CVTTPS2UQQ128,
+ IX86_BUILTIN_CVTTPS2DQ256_MASK,
+ IX86_BUILTIN_CVTTPS2DQ128_MASK,
+ IX86_BUILTIN_CVTTPS2UDQ256,
+ IX86_BUILTIN_CVTTPS2UDQ128,
+ IX86_BUILTIN_CVTTPD2DQ256_MASK,
+ IX86_BUILTIN_CVTTPD2DQ128_MASK,
+ IX86_BUILTIN_CVTTPD2UDQ256_MASK,
+ IX86_BUILTIN_CVTTPD2UDQ128_MASK,
+ IX86_BUILTIN_CVTPD2DQ256_MASK,
+ IX86_BUILTIN_CVTPD2DQ128_MASK,
+ IX86_BUILTIN_CVTDQ2PD256_MASK,
+ IX86_BUILTIN_CVTDQ2PD128_MASK,
+ IX86_BUILTIN_CVTUDQ2PD256_MASK,
+ IX86_BUILTIN_CVTUDQ2PD128_MASK,
+ IX86_BUILTIN_CVTDQ2PS256_MASK,
+ IX86_BUILTIN_CVTDQ2PS128_MASK,
+ IX86_BUILTIN_CVTUDQ2PS256_MASK,
+ IX86_BUILTIN_CVTUDQ2PS128_MASK,
+ IX86_BUILTIN_CVTPS2PD256_MASK,
+ IX86_BUILTIN_CVTPS2PD128_MASK,
+ IX86_BUILTIN_PBROADCASTB256_MASK,
+ IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTB128_MASK,
+ IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTW256_MASK,
+ IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTW128_MASK,
+ IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTD256_MASK,
+ IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTD128_MASK,
+ IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTQ256_MASK,
+ IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTQ256_MEM_MASK,
+ IX86_BUILTIN_PBROADCASTQ128_MASK,
+ IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
+ IX86_BUILTIN_PBROADCASTQ128_MEM_MASK,
+ IX86_BUILTIN_BROADCASTSS256,
+ IX86_BUILTIN_BROADCASTSS128,
+ IX86_BUILTIN_BROADCASTSD256,
+ IX86_BUILTIN_EXTRACTF64X2_256,
+ IX86_BUILTIN_EXTRACTI64X2_256,
+ IX86_BUILTIN_INSERTF32X4_256,
+ IX86_BUILTIN_INSERTI32X4_256,
+ IX86_BUILTIN_PMOVSXBW256_MASK,
+ IX86_BUILTIN_PMOVSXBW128_MASK,
+ IX86_BUILTIN_PMOVSXBD256_MASK,
+ IX86_BUILTIN_PMOVSXBD128_MASK,
+ IX86_BUILTIN_PMOVSXBQ256_MASK,
+ IX86_BUILTIN_PMOVSXBQ128_MASK,
+ IX86_BUILTIN_PMOVSXWD256_MASK,
+ IX86_BUILTIN_PMOVSXWD128_MASK,
+ IX86_BUILTIN_PMOVSXWQ256_MASK,
+ IX86_BUILTIN_PMOVSXWQ128_MASK,
+ IX86_BUILTIN_PMOVSXDQ256_MASK,
+ IX86_BUILTIN_PMOVSXDQ128_MASK,
+ IX86_BUILTIN_PMOVZXBW256_MASK,
+ IX86_BUILTIN_PMOVZXBW128_MASK,
+ IX86_BUILTIN_PMOVZXBD256_MASK,
+ IX86_BUILTIN_PMOVZXBD128_MASK,
+ IX86_BUILTIN_PMOVZXBQ256_MASK,
+ IX86_BUILTIN_PMOVZXBQ128_MASK,
+ IX86_BUILTIN_PMOVZXWD256_MASK,
+ IX86_BUILTIN_PMOVZXWD128_MASK,
+ IX86_BUILTIN_PMOVZXWQ256_MASK,
+ IX86_BUILTIN_PMOVZXWQ128_MASK,
+ IX86_BUILTIN_PMOVZXDQ256_MASK,
+ IX86_BUILTIN_PMOVZXDQ128_MASK,
+ IX86_BUILTIN_REDUCEPD256_MASK,
+ IX86_BUILTIN_REDUCEPD128_MASK,
+ IX86_BUILTIN_REDUCEPS256_MASK,
+ IX86_BUILTIN_REDUCEPS128_MASK,
+ IX86_BUILTIN_REDUCESD_MASK,
+ IX86_BUILTIN_REDUCESS_MASK,
+ IX86_BUILTIN_VPERMVARHI256_MASK,
+ IX86_BUILTIN_VPERMVARHI128_MASK,
+ IX86_BUILTIN_VPERMT2VARHI256,
+ IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
+ IX86_BUILTIN_VPERMT2VARHI128,
+ IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
+ IX86_BUILTIN_VPERMI2VARHI256,
+ IX86_BUILTIN_VPERMI2VARHI128,
+ IX86_BUILTIN_RCP14PD256,
+ IX86_BUILTIN_RCP14PD128,
+ IX86_BUILTIN_RCP14PS256,
+ IX86_BUILTIN_RCP14PS128,
+ IX86_BUILTIN_RSQRT14PD256_MASK,
+ IX86_BUILTIN_RSQRT14PD128_MASK,
+ IX86_BUILTIN_RSQRT14PS256_MASK,
+ IX86_BUILTIN_RSQRT14PS128_MASK,
+ IX86_BUILTIN_SQRTPD256_MASK,
+ IX86_BUILTIN_SQRTPD128_MASK,
+ IX86_BUILTIN_SQRTPS256_MASK,
+ IX86_BUILTIN_SQRTPS128_MASK,
+ IX86_BUILTIN_PADDB128_MASK,
+ IX86_BUILTIN_PADDW128_MASK,
+ IX86_BUILTIN_PADDD128_MASK,
+ IX86_BUILTIN_PADDQ128_MASK,
+ IX86_BUILTIN_PSUBB128_MASK,
+ IX86_BUILTIN_PSUBW128_MASK,
+ IX86_BUILTIN_PSUBD128_MASK,
+ IX86_BUILTIN_PSUBQ128_MASK,
+ IX86_BUILTIN_PADDSB128_MASK,
+ IX86_BUILTIN_PADDSW128_MASK,
+ IX86_BUILTIN_PSUBSB128_MASK,
+ IX86_BUILTIN_PSUBSW128_MASK,
+ IX86_BUILTIN_PADDUSB128_MASK,
+ IX86_BUILTIN_PADDUSW128_MASK,
+ IX86_BUILTIN_PSUBUSB128_MASK,
+ IX86_BUILTIN_PSUBUSW128_MASK,
+ IX86_BUILTIN_PADDB256_MASK,
+ IX86_BUILTIN_PADDW256_MASK,
+ IX86_BUILTIN_PADDD256_MASK,
+ IX86_BUILTIN_PADDQ256_MASK,
+ IX86_BUILTIN_PADDSB256_MASK,
+ IX86_BUILTIN_PADDSW256_MASK,
+ IX86_BUILTIN_PADDUSB256_MASK,
+ IX86_BUILTIN_PADDUSW256_MASK,
+ IX86_BUILTIN_PSUBB256_MASK,
+ IX86_BUILTIN_PSUBW256_MASK,
+ IX86_BUILTIN_PSUBD256_MASK,
+ IX86_BUILTIN_PSUBQ256_MASK,
+ IX86_BUILTIN_PSUBSB256_MASK,
+ IX86_BUILTIN_PSUBSW256_MASK,
+ IX86_BUILTIN_PSUBUSB256_MASK,
+ IX86_BUILTIN_PSUBUSW256_MASK,
+ IX86_BUILTIN_SHUF_F64x2_256,
+ IX86_BUILTIN_SHUF_I64x2_256,
+ IX86_BUILTIN_SHUF_I32x4_256,
+ IX86_BUILTIN_SHUF_F32x4_256,
+ IX86_BUILTIN_PMOVWB128,
+ IX86_BUILTIN_PMOVWB256,
+ IX86_BUILTIN_PMOVSWB128,
+ IX86_BUILTIN_PMOVSWB256,
+ IX86_BUILTIN_PMOVUSWB128,
+ IX86_BUILTIN_PMOVUSWB256,
+ IX86_BUILTIN_PMOVDB128,
+ IX86_BUILTIN_PMOVDB256,
+ IX86_BUILTIN_PMOVSDB128,
+ IX86_BUILTIN_PMOVSDB256,
+ IX86_BUILTIN_PMOVUSDB128,
+ IX86_BUILTIN_PMOVUSDB256,
+ IX86_BUILTIN_PMOVDW128,
+ IX86_BUILTIN_PMOVDW256,
+ IX86_BUILTIN_PMOVSDW128,
+ IX86_BUILTIN_PMOVSDW256,
+ IX86_BUILTIN_PMOVUSDW128,
+ IX86_BUILTIN_PMOVUSDW256,
+ IX86_BUILTIN_PMOVQB128,
+ IX86_BUILTIN_PMOVQB256,
+ IX86_BUILTIN_PMOVSQB128,
+ IX86_BUILTIN_PMOVSQB256,
+ IX86_BUILTIN_PMOVUSQB128,
+ IX86_BUILTIN_PMOVUSQB256,
+ IX86_BUILTIN_PMOVQW128,
+ IX86_BUILTIN_PMOVQW256,
+ IX86_BUILTIN_PMOVSQW128,
+ IX86_BUILTIN_PMOVSQW256,
+ IX86_BUILTIN_PMOVUSQW128,
+ IX86_BUILTIN_PMOVUSQW256,
+ IX86_BUILTIN_PMOVQD128,
+ IX86_BUILTIN_PMOVQD256,
+ IX86_BUILTIN_PMOVSQD128,
+ IX86_BUILTIN_PMOVSQD256,
+ IX86_BUILTIN_PMOVUSQD128,
+ IX86_BUILTIN_PMOVUSQD256,
+ IX86_BUILTIN_RANGEPD256,
+ IX86_BUILTIN_RANGEPD128,
+ IX86_BUILTIN_RANGEPS256,
+ IX86_BUILTIN_RANGEPS128,
+ IX86_BUILTIN_GETEXPPS256,
+ IX86_BUILTIN_GETEXPPD256,
+ IX86_BUILTIN_GETEXPPS128,
+ IX86_BUILTIN_GETEXPPD128,
+ IX86_BUILTIN_FIXUPIMMPD256_MASK,
+ IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
+ IX86_BUILTIN_FIXUPIMMPS256_MASK,
+ IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
+ IX86_BUILTIN_FIXUPIMMPD128_MASK,
+ IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
+ IX86_BUILTIN_FIXUPIMMPS128_MASK,
+ IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
+ IX86_BUILTIN_PABSQ256,
+ IX86_BUILTIN_PABSQ128,
+ IX86_BUILTIN_PABSD256_MASK,
+ IX86_BUILTIN_PABSD128_MASK,
+ IX86_BUILTIN_PMULHRSW256_MASK,
+ IX86_BUILTIN_PMULHRSW128_MASK,
+ IX86_BUILTIN_PMULHUW128_MASK,
+ IX86_BUILTIN_PMULHUW256_MASK,
+ IX86_BUILTIN_PMULHW256_MASK,
+ IX86_BUILTIN_PMULHW128_MASK,
+ IX86_BUILTIN_PMULLW256_MASK,
+ IX86_BUILTIN_PMULLW128_MASK,
+ IX86_BUILTIN_PMULLQ256,
+ IX86_BUILTIN_PMULLQ128,
+ IX86_BUILTIN_ANDPD256_MASK,
+ IX86_BUILTIN_ANDPD128_MASK,
+ IX86_BUILTIN_ANDPS256_MASK,
+ IX86_BUILTIN_ANDPS128_MASK,
+ IX86_BUILTIN_ANDNPD256_MASK,
+ IX86_BUILTIN_ANDNPD128_MASK,
+ IX86_BUILTIN_ANDNPS256_MASK,
+ IX86_BUILTIN_ANDNPS128_MASK,
+ IX86_BUILTIN_PSLLWI128_MASK,
+ IX86_BUILTIN_PSLLDI128_MASK,
+ IX86_BUILTIN_PSLLQI128_MASK,
+ IX86_BUILTIN_PSLLW128_MASK,
+ IX86_BUILTIN_PSLLD128_MASK,
+ IX86_BUILTIN_PSLLQ128_MASK,
+ IX86_BUILTIN_PSLLWI256_MASK ,
+ IX86_BUILTIN_PSLLW256_MASK,
+ IX86_BUILTIN_PSLLDI256_MASK,
+ IX86_BUILTIN_PSLLD256_MASK,
+ IX86_BUILTIN_PSLLQI256_MASK,
+ IX86_BUILTIN_PSLLQ256_MASK,
+ IX86_BUILTIN_PSRADI128_MASK,
+ IX86_BUILTIN_PSRAD128_MASK,
+ IX86_BUILTIN_PSRADI256_MASK,
+ IX86_BUILTIN_PSRAD256_MASK,
+ IX86_BUILTIN_PSRAQI128_MASK,
+ IX86_BUILTIN_PSRAQ128_MASK,
+ IX86_BUILTIN_PSRAQI256_MASK,
+ IX86_BUILTIN_PSRAQ256_MASK,
+ IX86_BUILTIN_PANDD256,
+ IX86_BUILTIN_PANDD128,
+ IX86_BUILTIN_PSRLDI128_MASK,
+ IX86_BUILTIN_PSRLD128_MASK,
+ IX86_BUILTIN_PSRLDI256_MASK,
+ IX86_BUILTIN_PSRLD256_MASK,
+ IX86_BUILTIN_PSRLQI128_MASK,
+ IX86_BUILTIN_PSRLQ128_MASK,
+ IX86_BUILTIN_PSRLQI256_MASK,
+ IX86_BUILTIN_PSRLQ256_MASK,
+ IX86_BUILTIN_PANDQ256,
+ IX86_BUILTIN_PANDQ128,
+ IX86_BUILTIN_PANDND256,
+ IX86_BUILTIN_PANDND128,
+ IX86_BUILTIN_PANDNQ256,
+ IX86_BUILTIN_PANDNQ128,
+ IX86_BUILTIN_PORD256,
+ IX86_BUILTIN_PORD128,
+ IX86_BUILTIN_PORQ256,
+ IX86_BUILTIN_PORQ128,
+ IX86_BUILTIN_PXORD256,
+ IX86_BUILTIN_PXORD128,
+ IX86_BUILTIN_PXORQ256,
+ IX86_BUILTIN_PXORQ128,
+ IX86_BUILTIN_PACKSSWB256_MASK,
+ IX86_BUILTIN_PACKSSWB128_MASK,
+ IX86_BUILTIN_PACKUSWB256_MASK,
+ IX86_BUILTIN_PACKUSWB128_MASK,
+ IX86_BUILTIN_RNDSCALEPS256,
+ IX86_BUILTIN_RNDSCALEPD256,
+ IX86_BUILTIN_RNDSCALEPS128,
+ IX86_BUILTIN_RNDSCALEPD128,
+ IX86_BUILTIN_VTERNLOGQ256_MASK,
+ IX86_BUILTIN_VTERNLOGQ256_MASKZ,
+ IX86_BUILTIN_VTERNLOGD256_MASK,
+ IX86_BUILTIN_VTERNLOGD256_MASKZ,
+ IX86_BUILTIN_VTERNLOGQ128_MASK,
+ IX86_BUILTIN_VTERNLOGQ128_MASKZ,
+ IX86_BUILTIN_VTERNLOGD128_MASK,
+ IX86_BUILTIN_VTERNLOGD128_MASKZ,
+ IX86_BUILTIN_SCALEFPD256,
+ IX86_BUILTIN_SCALEFPS256,
+ IX86_BUILTIN_SCALEFPD128,
+ IX86_BUILTIN_SCALEFPS128,
+ IX86_BUILTIN_VFMADDPD256_MASK,
+ IX86_BUILTIN_VFMADDPD256_MASK3,
+ IX86_BUILTIN_VFMADDPD256_MASKZ,
+ IX86_BUILTIN_VFMADDPD128_MASK,
+ IX86_BUILTIN_VFMADDPD128_MASK3,
+ IX86_BUILTIN_VFMADDPD128_MASKZ,
+ IX86_BUILTIN_VFMADDPS256_MASK,
+ IX86_BUILTIN_VFMADDPS256_MASK3,
+ IX86_BUILTIN_VFMADDPS256_MASKZ,
+ IX86_BUILTIN_VFMADDPS128_MASK,
+ IX86_BUILTIN_VFMADDPS128_MASK3,
+ IX86_BUILTIN_VFMADDPS128_MASKZ,
+ IX86_BUILTIN_VFMSUBPD256_MASK3,
+ IX86_BUILTIN_VFMSUBPD128_MASK3,
+ IX86_BUILTIN_VFMSUBPS256_MASK3,
+ IX86_BUILTIN_VFMSUBPS128_MASK3,
+ IX86_BUILTIN_VFNMADDPD256_MASK,
+ IX86_BUILTIN_VFNMADDPD128_MASK,
+ IX86_BUILTIN_VFNMADDPS256_MASK,
+ IX86_BUILTIN_VFNMADDPS128_MASK,
+ IX86_BUILTIN_VFNMSUBPD256_MASK,
+ IX86_BUILTIN_VFNMSUBPD256_MASK3,
+ IX86_BUILTIN_VFNMSUBPD128_MASK,
+ IX86_BUILTIN_VFNMSUBPD128_MASK3,
+ IX86_BUILTIN_VFNMSUBPS256_MASK,
+ IX86_BUILTIN_VFNMSUBPS256_MASK3,
+ IX86_BUILTIN_VFNMSUBPS128_MASK,
+ IX86_BUILTIN_VFNMSUBPS128_MASK3,
+ IX86_BUILTIN_VFMADDSUBPD256_MASK,
+ IX86_BUILTIN_VFMADDSUBPD256_MASK3,
+ IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
+ IX86_BUILTIN_VFMADDSUBPD128_MASK,
+ IX86_BUILTIN_VFMADDSUBPD128_MASK3,
+ IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
+ IX86_BUILTIN_VFMADDSUBPS256_MASK,
+ IX86_BUILTIN_VFMADDSUBPS256_MASK3,
+ IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
+ IX86_BUILTIN_VFMADDSUBPS128_MASK,
+ IX86_BUILTIN_VFMADDSUBPS128_MASK3,
+ IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
+ IX86_BUILTIN_VFMSUBADDPD256_MASK3,
+ IX86_BUILTIN_VFMSUBADDPD128_MASK3,
+ IX86_BUILTIN_VFMSUBADDPS256_MASK3,
+ IX86_BUILTIN_VFMSUBADDPS128_MASK3,
+ IX86_BUILTIN_INSERTF64X2_256,
+ IX86_BUILTIN_INSERTI64X2_256,
+ IX86_BUILTIN_PSRAVV16HI,
+ IX86_BUILTIN_PSRAVV8HI,
+ IX86_BUILTIN_PMADDUBSW256_MASK,
+ IX86_BUILTIN_PMADDUBSW128_MASK,
+ IX86_BUILTIN_PMADDWD256_MASK,
+ IX86_BUILTIN_PMADDWD128_MASK,
+ IX86_BUILTIN_PSRLVV16HI,
+ IX86_BUILTIN_PSRLVV8HI,
+ IX86_BUILTIN_CVTPS2DQ256_MASK,
+ IX86_BUILTIN_CVTPS2DQ128_MASK,
+ IX86_BUILTIN_CVTPS2UDQ256,
+ IX86_BUILTIN_CVTPS2UDQ128,
+ IX86_BUILTIN_CVTPS2QQ256,
+ IX86_BUILTIN_CVTPS2QQ128,
+ IX86_BUILTIN_CVTPS2UQQ256,
+ IX86_BUILTIN_CVTPS2UQQ128,
+ IX86_BUILTIN_GETMANTPS256,
+ IX86_BUILTIN_GETMANTPS128,
+ IX86_BUILTIN_GETMANTPD256,
+ IX86_BUILTIN_GETMANTPD128,
+ IX86_BUILTIN_MOVDDUP256_MASK,
+ IX86_BUILTIN_MOVDDUP128_MASK,
+ IX86_BUILTIN_MOVSHDUP256_MASK,
+ IX86_BUILTIN_MOVSHDUP128_MASK,
+ IX86_BUILTIN_MOVSLDUP256_MASK,
+ IX86_BUILTIN_MOVSLDUP128_MASK,
+ IX86_BUILTIN_CVTQQ2PS256,
+ IX86_BUILTIN_CVTQQ2PS128,
+ IX86_BUILTIN_CVTUQQ2PS256,
+ IX86_BUILTIN_CVTUQQ2PS128,
+ IX86_BUILTIN_CVTQQ2PD256,
+ IX86_BUILTIN_CVTQQ2PD128,
+ IX86_BUILTIN_CVTUQQ2PD256,
+ IX86_BUILTIN_CVTUQQ2PD128,
+ IX86_BUILTIN_VPERMT2VARQ256,
+ IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
+ IX86_BUILTIN_VPERMT2VARD256,
+ IX86_BUILTIN_VPERMT2VARD256_MASKZ,
+ IX86_BUILTIN_VPERMI2VARQ256,
+ IX86_BUILTIN_VPERMI2VARD256,
+ IX86_BUILTIN_VPERMT2VARPD256,
+ IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
+ IX86_BUILTIN_VPERMT2VARPS256,
+ IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
+ IX86_BUILTIN_VPERMI2VARPD256,
+ IX86_BUILTIN_VPERMI2VARPS256,
+ IX86_BUILTIN_VPERMT2VARQ128,
+ IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
+ IX86_BUILTIN_VPERMT2VARD128,
+ IX86_BUILTIN_VPERMT2VARD128_MASKZ,
+ IX86_BUILTIN_VPERMI2VARQ128,
+ IX86_BUILTIN_VPERMI2VARD128,
+ IX86_BUILTIN_VPERMT2VARPD128,
+ IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
+ IX86_BUILTIN_VPERMT2VARPS128,
+ IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
+ IX86_BUILTIN_VPERMI2VARPD128,
+ IX86_BUILTIN_VPERMI2VARPS128,
+ IX86_BUILTIN_PSHUFB256_MASK,
+ IX86_BUILTIN_PSHUFB128_MASK,
+ IX86_BUILTIN_PSHUFHW256_MASK,
+ IX86_BUILTIN_PSHUFHW128_MASK,
+ IX86_BUILTIN_PSHUFLW256_MASK,
+ IX86_BUILTIN_PSHUFLW128_MASK,
+ IX86_BUILTIN_PSHUFD256_MASK,
+ IX86_BUILTIN_PSHUFD128_MASK,
+ IX86_BUILTIN_SHUFPD256_MASK,
+ IX86_BUILTIN_SHUFPD128_MASK,
+ IX86_BUILTIN_SHUFPS256_MASK,
+ IX86_BUILTIN_SHUFPS128_MASK,
+ IX86_BUILTIN_PROLVQ256,
+ IX86_BUILTIN_PROLVQ128,
+ IX86_BUILTIN_PROLQ256,
+ IX86_BUILTIN_PROLQ128,
+ IX86_BUILTIN_PRORVQ256,
+ IX86_BUILTIN_PRORVQ128,
+ IX86_BUILTIN_PRORQ256,
+ IX86_BUILTIN_PRORQ128,
+ IX86_BUILTIN_PSRAVQ128,
+ IX86_BUILTIN_PSRAVQ256,
+ IX86_BUILTIN_PSLLVV4DI_MASK,
+ IX86_BUILTIN_PSLLVV2DI_MASK,
+ IX86_BUILTIN_PSLLVV8SI_MASK,
+ IX86_BUILTIN_PSLLVV4SI_MASK,
+ IX86_BUILTIN_PSRAVV8SI_MASK,
+ IX86_BUILTIN_PSRAVV4SI_MASK,
+ IX86_BUILTIN_PSRLVV4DI_MASK,
+ IX86_BUILTIN_PSRLVV2DI_MASK,
+ IX86_BUILTIN_PSRLVV8SI_MASK,
+ IX86_BUILTIN_PSRLVV4SI_MASK,
+ IX86_BUILTIN_PSRAWI256_MASK,
+ IX86_BUILTIN_PSRAW256_MASK,
+ IX86_BUILTIN_PSRAWI128_MASK,
+ IX86_BUILTIN_PSRAW128_MASK,
+ IX86_BUILTIN_PSRLWI256_MASK,
+ IX86_BUILTIN_PSRLW256_MASK,
+ IX86_BUILTIN_PSRLWI128_MASK,
+ IX86_BUILTIN_PSRLW128_MASK,
+ IX86_BUILTIN_PRORVD256,
+ IX86_BUILTIN_PROLVD256,
+ IX86_BUILTIN_PRORD256,
+ IX86_BUILTIN_PROLD256,
+ IX86_BUILTIN_PRORVD128,
+ IX86_BUILTIN_PROLVD128,
+ IX86_BUILTIN_PRORD128,
+ IX86_BUILTIN_PROLD128,
+ IX86_BUILTIN_FPCLASSPD256,
+ IX86_BUILTIN_FPCLASSPD128,
+ IX86_BUILTIN_FPCLASSSD,
+ IX86_BUILTIN_FPCLASSPS256,
+ IX86_BUILTIN_FPCLASSPS128,
+ IX86_BUILTIN_FPCLASSSS,
+ IX86_BUILTIN_CVTB2MASK128,
+ IX86_BUILTIN_CVTB2MASK256,
+ IX86_BUILTIN_CVTW2MASK128,
+ IX86_BUILTIN_CVTW2MASK256,
+ IX86_BUILTIN_CVTD2MASK128,
+ IX86_BUILTIN_CVTD2MASK256,
+ IX86_BUILTIN_CVTQ2MASK128,
+ IX86_BUILTIN_CVTQ2MASK256,
+ IX86_BUILTIN_CVTMASK2B128,
+ IX86_BUILTIN_CVTMASK2B256,
+ IX86_BUILTIN_CVTMASK2W128,
+ IX86_BUILTIN_CVTMASK2W256,
+ IX86_BUILTIN_CVTMASK2D128,
+ IX86_BUILTIN_CVTMASK2D256,
+ IX86_BUILTIN_CVTMASK2Q128,
+ IX86_BUILTIN_CVTMASK2Q256,
+ IX86_BUILTIN_PCMPEQB128_MASK,
+ IX86_BUILTIN_PCMPEQB256_MASK,
+ IX86_BUILTIN_PCMPEQW128_MASK,
+ IX86_BUILTIN_PCMPEQW256_MASK,
+ IX86_BUILTIN_PCMPEQD128_MASK,
+ IX86_BUILTIN_PCMPEQD256_MASK,
+ IX86_BUILTIN_PCMPEQQ128_MASK,
+ IX86_BUILTIN_PCMPEQQ256_MASK,
+ IX86_BUILTIN_PCMPGTB128_MASK,
+ IX86_BUILTIN_PCMPGTB256_MASK,
+ IX86_BUILTIN_PCMPGTW128_MASK,
+ IX86_BUILTIN_PCMPGTW256_MASK,
+ IX86_BUILTIN_PCMPGTD128_MASK,
+ IX86_BUILTIN_PCMPGTD256_MASK,
+ IX86_BUILTIN_PCMPGTQ128_MASK,
+ IX86_BUILTIN_PCMPGTQ256_MASK,
+ IX86_BUILTIN_PTESTMB128,
+ IX86_BUILTIN_PTESTMB256,
+ IX86_BUILTIN_PTESTMW128,
+ IX86_BUILTIN_PTESTMW256,
+ IX86_BUILTIN_PTESTMD128,
+ IX86_BUILTIN_PTESTMD256,
+ IX86_BUILTIN_PTESTMQ128,
+ IX86_BUILTIN_PTESTMQ256,
+ IX86_BUILTIN_PTESTNMB128,
+ IX86_BUILTIN_PTESTNMB256,
+ IX86_BUILTIN_PTESTNMW128,
+ IX86_BUILTIN_PTESTNMW256,
+ IX86_BUILTIN_PTESTNMD128,
+ IX86_BUILTIN_PTESTNMD256,
+ IX86_BUILTIN_PTESTNMQ128,
+ IX86_BUILTIN_PTESTNMQ256,
+ IX86_BUILTIN_PBROADCASTMB128,
+ IX86_BUILTIN_PBROADCASTMB256,
+ IX86_BUILTIN_PBROADCASTMW128,
+ IX86_BUILTIN_PBROADCASTMW256,
+ IX86_BUILTIN_COMPRESSPD256,
+ IX86_BUILTIN_COMPRESSPD128,
+ IX86_BUILTIN_COMPRESSPS256,
+ IX86_BUILTIN_COMPRESSPS128,
+ IX86_BUILTIN_PCOMPRESSQ256,
+ IX86_BUILTIN_PCOMPRESSQ128,
+ IX86_BUILTIN_PCOMPRESSD256,
+ IX86_BUILTIN_PCOMPRESSD128,
+ IX86_BUILTIN_EXPANDPD256,
+ IX86_BUILTIN_EXPANDPD128,
+ IX86_BUILTIN_EXPANDPS256,
+ IX86_BUILTIN_EXPANDPS128,
+ IX86_BUILTIN_PEXPANDQ256,
+ IX86_BUILTIN_PEXPANDQ128,
+ IX86_BUILTIN_PEXPANDD256,
+ IX86_BUILTIN_PEXPANDD128,
+ IX86_BUILTIN_EXPANDPD256Z,
+ IX86_BUILTIN_EXPANDPD128Z,
+ IX86_BUILTIN_EXPANDPS256Z,
+ IX86_BUILTIN_EXPANDPS128Z,
+ IX86_BUILTIN_PEXPANDQ256Z,
+ IX86_BUILTIN_PEXPANDQ128Z,
+ IX86_BUILTIN_PEXPANDD256Z,
+ IX86_BUILTIN_PEXPANDD128Z,
+ IX86_BUILTIN_PMAXSD256_MASK,
+ IX86_BUILTIN_PMINSD256_MASK,
+ IX86_BUILTIN_PMAXUD256_MASK,
+ IX86_BUILTIN_PMINUD256_MASK,
+ IX86_BUILTIN_PMAXSD128_MASK,
+ IX86_BUILTIN_PMINSD128_MASK,
+ IX86_BUILTIN_PMAXUD128_MASK,
+ IX86_BUILTIN_PMINUD128_MASK,
+ IX86_BUILTIN_PMAXSQ256_MASK,
+ IX86_BUILTIN_PMINSQ256_MASK,
+ IX86_BUILTIN_PMAXUQ256_MASK,
+ IX86_BUILTIN_PMINUQ256_MASK,
+ IX86_BUILTIN_PMAXSQ128_MASK,
+ IX86_BUILTIN_PMINSQ128_MASK,
+ IX86_BUILTIN_PMAXUQ128_MASK,
+ IX86_BUILTIN_PMINUQ128_MASK,
+ IX86_BUILTIN_PMINSB256_MASK,
+ IX86_BUILTIN_PMINUB256_MASK,
+ IX86_BUILTIN_PMAXSB256_MASK,
+ IX86_BUILTIN_PMAXUB256_MASK,
+ IX86_BUILTIN_PMINSB128_MASK,
+ IX86_BUILTIN_PMINUB128_MASK,
+ IX86_BUILTIN_PMAXSB128_MASK,
+ IX86_BUILTIN_PMAXUB128_MASK,
+ IX86_BUILTIN_PMINSW256_MASK,
+ IX86_BUILTIN_PMINUW256_MASK,
+ IX86_BUILTIN_PMAXSW256_MASK,
+ IX86_BUILTIN_PMAXUW256_MASK,
+ IX86_BUILTIN_PMINSW128_MASK,
+ IX86_BUILTIN_PMINUW128_MASK,
+ IX86_BUILTIN_PMAXSW128_MASK,
+ IX86_BUILTIN_PMAXUW128_MASK,
+ IX86_BUILTIN_VPCONFLICTQ256,
+ IX86_BUILTIN_VPCONFLICTD256,
+ IX86_BUILTIN_VPCLZCNTQ256,
+ IX86_BUILTIN_VPCLZCNTD256,
+ IX86_BUILTIN_UNPCKHPD256_MASK,
+ IX86_BUILTIN_UNPCKHPD128_MASK,
+ IX86_BUILTIN_UNPCKHPS256_MASK,
+ IX86_BUILTIN_UNPCKHPS128_MASK,
+ IX86_BUILTIN_UNPCKLPD256_MASK,
+ IX86_BUILTIN_UNPCKLPD128_MASK,
+ IX86_BUILTIN_UNPCKLPS256_MASK,
+ IX86_BUILTIN_VPCONFLICTQ128,
+ IX86_BUILTIN_VPCONFLICTD128,
+ IX86_BUILTIN_VPCLZCNTQ128,
+ IX86_BUILTIN_VPCLZCNTD128,
+ IX86_BUILTIN_UNPCKLPS128_MASK,
+ IX86_BUILTIN_ALIGND256,
+ IX86_BUILTIN_ALIGNQ256,
+ IX86_BUILTIN_ALIGND128,
+ IX86_BUILTIN_ALIGNQ128,
+ IX86_BUILTIN_CVTPS2PH256_MASK,
+ IX86_BUILTIN_CVTPS2PH_MASK,
+ IX86_BUILTIN_CVTPH2PS_MASK,
+ IX86_BUILTIN_CVTPH2PS256_MASK,
+ IX86_BUILTIN_PUNPCKHDQ128_MASK,
+ IX86_BUILTIN_PUNPCKHDQ256_MASK,
+ IX86_BUILTIN_PUNPCKHQDQ128_MASK,
+ IX86_BUILTIN_PUNPCKHQDQ256_MASK,
+ IX86_BUILTIN_PUNPCKLDQ128_MASK,
+ IX86_BUILTIN_PUNPCKLDQ256_MASK,
+ IX86_BUILTIN_PUNPCKLQDQ128_MASK,
+ IX86_BUILTIN_PUNPCKLQDQ256_MASK,
+ IX86_BUILTIN_PUNPCKHBW128_MASK,
+ IX86_BUILTIN_PUNPCKHBW256_MASK,
+ IX86_BUILTIN_PUNPCKHWD128_MASK,
+ IX86_BUILTIN_PUNPCKHWD256_MASK,
+ IX86_BUILTIN_PUNPCKLBW128_MASK,
+ IX86_BUILTIN_PUNPCKLBW256_MASK,
+ IX86_BUILTIN_PUNPCKLWD128_MASK,
+ IX86_BUILTIN_PUNPCKLWD256_MASK,
+ IX86_BUILTIN_PSLLVV16HI,
+ IX86_BUILTIN_PSLLVV8HI,
+ IX86_BUILTIN_PACKSSDW256_MASK,
+ IX86_BUILTIN_PACKSSDW128_MASK,
+ IX86_BUILTIN_PACKUSDW256_MASK,
+ IX86_BUILTIN_PACKUSDW128_MASK,
+ IX86_BUILTIN_PAVGB256_MASK,
+ IX86_BUILTIN_PAVGW256_MASK,
+ IX86_BUILTIN_PAVGB128_MASK,
+ IX86_BUILTIN_PAVGW128_MASK,
+ IX86_BUILTIN_VPERMVARSF256_MASK,
+ IX86_BUILTIN_VPERMVARDF256_MASK,
+ IX86_BUILTIN_VPERMDF256_MASK,
+ IX86_BUILTIN_PABSB256_MASK,
+ IX86_BUILTIN_PABSB128_MASK,
+ IX86_BUILTIN_PABSW256_MASK,
+ IX86_BUILTIN_PABSW128_MASK,
+ IX86_BUILTIN_VPERMILVARPD_MASK,
+ IX86_BUILTIN_VPERMILVARPS_MASK,
+ IX86_BUILTIN_VPERMILVARPD256_MASK,
+ IX86_BUILTIN_VPERMILVARPS256_MASK,
+ IX86_BUILTIN_VPERMILPD_MASK,
+ IX86_BUILTIN_VPERMILPS_MASK,
+ IX86_BUILTIN_VPERMILPD256_MASK,
+ IX86_BUILTIN_VPERMILPS256_MASK,
+ IX86_BUILTIN_BLENDMQ256,
+ IX86_BUILTIN_BLENDMD256,
+ IX86_BUILTIN_BLENDMPD256,
+ IX86_BUILTIN_BLENDMPS256,
+ IX86_BUILTIN_BLENDMQ128,
+ IX86_BUILTIN_BLENDMD128,
+ IX86_BUILTIN_BLENDMPD128,
+ IX86_BUILTIN_BLENDMPS128,
+ IX86_BUILTIN_BLENDMW256,
+ IX86_BUILTIN_BLENDMB256,
+ IX86_BUILTIN_BLENDMW128,
+ IX86_BUILTIN_BLENDMB128,
+ IX86_BUILTIN_PMULLD256_MASK,
+ IX86_BUILTIN_PMULLD128_MASK,
+ IX86_BUILTIN_PMULUDQ256_MASK,
+ IX86_BUILTIN_PMULDQ256_MASK,
+ IX86_BUILTIN_PMULDQ128_MASK,
+ IX86_BUILTIN_PMULUDQ128_MASK,
+ IX86_BUILTIN_CVTPD2PS256_MASK,
+ IX86_BUILTIN_CVTPD2PS_MASK,
+ IX86_BUILTIN_VPERMVARSI256_MASK,
+ IX86_BUILTIN_VPERMVARDI256_MASK,
+ IX86_BUILTIN_VPERMDI256_MASK,
+ IX86_BUILTIN_CMPQ256,
+ IX86_BUILTIN_CMPD256,
+ IX86_BUILTIN_UCMPQ256,
+ IX86_BUILTIN_UCMPD256,
+ IX86_BUILTIN_CMPB256,
+ IX86_BUILTIN_CMPW256,
+ IX86_BUILTIN_UCMPB256,
+ IX86_BUILTIN_UCMPW256,
+ IX86_BUILTIN_CMPPD256_MASK,
+ IX86_BUILTIN_CMPPS256_MASK,
+ IX86_BUILTIN_CMPQ128,
+ IX86_BUILTIN_CMPD128,
+ IX86_BUILTIN_UCMPQ128,
+ IX86_BUILTIN_UCMPD128,
+ IX86_BUILTIN_CMPB128,
+ IX86_BUILTIN_CMPW128,
+ IX86_BUILTIN_UCMPB128,
+ IX86_BUILTIN_UCMPW128,
+ IX86_BUILTIN_CMPPD128_MASK,
+ IX86_BUILTIN_CMPPS128_MASK,
+
+ IX86_BUILTIN_GATHER3SIV8SF,
+ IX86_BUILTIN_GATHER3SIV4SF,
+ IX86_BUILTIN_GATHER3SIV4DF,
+ IX86_BUILTIN_GATHER3SIV2DF,
+ IX86_BUILTIN_GATHER3DIV8SF,
+ IX86_BUILTIN_GATHER3DIV4SF,
+ IX86_BUILTIN_GATHER3DIV4DF,
+ IX86_BUILTIN_GATHER3DIV2DF,
+ IX86_BUILTIN_GATHER3SIV8SI,
+ IX86_BUILTIN_GATHER3SIV4SI,
+ IX86_BUILTIN_GATHER3SIV4DI,
+ IX86_BUILTIN_GATHER3SIV2DI,
+ IX86_BUILTIN_GATHER3DIV8SI,
+ IX86_BUILTIN_GATHER3DIV4SI,
+ IX86_BUILTIN_GATHER3DIV4DI,
+ IX86_BUILTIN_GATHER3DIV2DI,
+ IX86_BUILTIN_SCATTERSIV8SF,
+ IX86_BUILTIN_SCATTERSIV4SF,
+ IX86_BUILTIN_SCATTERSIV4DF,
+ IX86_BUILTIN_SCATTERSIV2DF,
+ IX86_BUILTIN_SCATTERDIV8SF,
+ IX86_BUILTIN_SCATTERDIV4SF,
+ IX86_BUILTIN_SCATTERDIV4DF,
+ IX86_BUILTIN_SCATTERDIV2DF,
+ IX86_BUILTIN_SCATTERSIV8SI,
+ IX86_BUILTIN_SCATTERSIV4SI,
+ IX86_BUILTIN_SCATTERSIV4DI,
+ IX86_BUILTIN_SCATTERSIV2DI,
+ IX86_BUILTIN_SCATTERDIV8SI,
+ IX86_BUILTIN_SCATTERDIV4SI,
+ IX86_BUILTIN_SCATTERDIV4DI,
+ IX86_BUILTIN_SCATTERDIV2DI,
+
+ /* AVX512DQ. */
+ IX86_BUILTIN_RANGESD128,
+ IX86_BUILTIN_RANGESS128,
+ IX86_BUILTIN_KUNPCKWD,
+ IX86_BUILTIN_KUNPCKDQ,
+ IX86_BUILTIN_BROADCASTF32x2_512,
+ IX86_BUILTIN_BROADCASTI32x2_512,
+ IX86_BUILTIN_BROADCASTF64X2_512,
+ IX86_BUILTIN_BROADCASTI64X2_512,
+ IX86_BUILTIN_BROADCASTF32X8_512,
+ IX86_BUILTIN_BROADCASTI32X8_512,
+ IX86_BUILTIN_EXTRACTF64X2_512,
+ IX86_BUILTIN_EXTRACTF32X8,
+ IX86_BUILTIN_EXTRACTI64X2_512,
+ IX86_BUILTIN_EXTRACTI32X8,
+ IX86_BUILTIN_REDUCEPD512_MASK,
+ IX86_BUILTIN_REDUCEPS512_MASK,
+ IX86_BUILTIN_PMULLQ512,
+ IX86_BUILTIN_XORPD512,
+ IX86_BUILTIN_XORPS512,
+ IX86_BUILTIN_ORPD512,
+ IX86_BUILTIN_ORPS512,
+ IX86_BUILTIN_ANDPD512,
+ IX86_BUILTIN_ANDPS512,
+ IX86_BUILTIN_ANDNPD512,
+ IX86_BUILTIN_ANDNPS512,
+ IX86_BUILTIN_INSERTF32X8,
+ IX86_BUILTIN_INSERTI32X8,
+ IX86_BUILTIN_INSERTF64X2_512,
+ IX86_BUILTIN_INSERTI64X2_512,
+ IX86_BUILTIN_FPCLASSPD512,
+ IX86_BUILTIN_FPCLASSPS512,
+ IX86_BUILTIN_CVTD2MASK512,
+ IX86_BUILTIN_CVTQ2MASK512,
+ IX86_BUILTIN_CVTMASK2D512,
+ IX86_BUILTIN_CVTMASK2Q512,
+ IX86_BUILTIN_CVTPD2QQ512,
+ IX86_BUILTIN_CVTPS2QQ512,
+ IX86_BUILTIN_CVTPD2UQQ512,
+ IX86_BUILTIN_CVTPS2UQQ512,
+ IX86_BUILTIN_CVTQQ2PS512,
+ IX86_BUILTIN_CVTUQQ2PS512,
+ IX86_BUILTIN_CVTQQ2PD512,
+ IX86_BUILTIN_CVTUQQ2PD512,
+ IX86_BUILTIN_CVTTPS2QQ512,
+ IX86_BUILTIN_CVTTPS2UQQ512,
+ IX86_BUILTIN_CVTTPD2QQ512,
+ IX86_BUILTIN_CVTTPD2UQQ512,
+ IX86_BUILTIN_RANGEPS512,
+ IX86_BUILTIN_RANGEPD512,
+
+ /* AVX512BW. */
+ IX86_BUILTIN_PACKUSDW512,
+ IX86_BUILTIN_PACKSSDW512,
+ IX86_BUILTIN_LOADDQUHI512_MASK,
+ IX86_BUILTIN_LOADDQUQI512_MASK,
+ IX86_BUILTIN_PSLLDQ512,
+ IX86_BUILTIN_PSRLDQ512,
+ IX86_BUILTIN_STOREDQUHI512_MASK,
+ IX86_BUILTIN_STOREDQUQI512_MASK,
+ IX86_BUILTIN_PALIGNR512,
+ IX86_BUILTIN_PALIGNR512_MASK,
+ IX86_BUILTIN_MOVDQUHI512_MASK,
+ IX86_BUILTIN_MOVDQUQI512_MASK,
+ IX86_BUILTIN_PSADBW512,
+ IX86_BUILTIN_DBPSADBW512,
+ IX86_BUILTIN_PBROADCASTB512,
+ IX86_BUILTIN_PBROADCASTB512_GPR,
+ IX86_BUILTIN_PBROADCASTW512,
+ IX86_BUILTIN_PBROADCASTW512_GPR,
+ IX86_BUILTIN_PMOVSXBW512_MASK,
+ IX86_BUILTIN_PMOVZXBW512_MASK,
+ IX86_BUILTIN_VPERMVARHI512_MASK,
+ IX86_BUILTIN_VPERMT2VARHI512,
+ IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
+ IX86_BUILTIN_VPERMI2VARHI512,
+ IX86_BUILTIN_PAVGB512,
+ IX86_BUILTIN_PAVGW512,
+ IX86_BUILTIN_PADDB512,
+ IX86_BUILTIN_PSUBB512,
+ IX86_BUILTIN_PSUBSB512,
+ IX86_BUILTIN_PADDSB512,
+ IX86_BUILTIN_PSUBUSB512,
+ IX86_BUILTIN_PADDUSB512,
+ IX86_BUILTIN_PSUBW512,
+ IX86_BUILTIN_PADDW512,
+ IX86_BUILTIN_PSUBSW512,
+ IX86_BUILTIN_PADDSW512,
+ IX86_BUILTIN_PSUBUSW512,
+ IX86_BUILTIN_PADDUSW512,
+ IX86_BUILTIN_PMAXUW512,
+ IX86_BUILTIN_PMAXSW512,
+ IX86_BUILTIN_PMINUW512,
+ IX86_BUILTIN_PMINSW512,
+ IX86_BUILTIN_PMAXUB512,
+ IX86_BUILTIN_PMAXSB512,
+ IX86_BUILTIN_PMINUB512,
+ IX86_BUILTIN_PMINSB512,
+ IX86_BUILTIN_PMOVWB512,
+ IX86_BUILTIN_PMOVSWB512,
+ IX86_BUILTIN_PMOVUSWB512,
+ IX86_BUILTIN_PMULHRSW512_MASK,
+ IX86_BUILTIN_PMULHUW512_MASK,
+ IX86_BUILTIN_PMULHW512_MASK,
+ IX86_BUILTIN_PMULLW512_MASK,
+ IX86_BUILTIN_PSLLWI512_MASK,
+ IX86_BUILTIN_PSLLW512_MASK,
+ IX86_BUILTIN_PACKSSWB512,
+ IX86_BUILTIN_PACKUSWB512,
+ IX86_BUILTIN_PSRAVV32HI,
+ IX86_BUILTIN_PMADDUBSW512_MASK,
+ IX86_BUILTIN_PMADDWD512_MASK,
+ IX86_BUILTIN_PSRLVV32HI,
+ IX86_BUILTIN_PUNPCKHBW512,
+ IX86_BUILTIN_PUNPCKHWD512,
+ IX86_BUILTIN_PUNPCKLBW512,
+ IX86_BUILTIN_PUNPCKLWD512,
+ IX86_BUILTIN_PSHUFB512,
+ IX86_BUILTIN_PSHUFHW512,
+ IX86_BUILTIN_PSHUFLW512,
+ IX86_BUILTIN_PSRAWI512,
+ IX86_BUILTIN_PSRAW512,
+ IX86_BUILTIN_PSRLWI512,
+ IX86_BUILTIN_PSRLW512,
+ IX86_BUILTIN_CVTB2MASK512,
+ IX86_BUILTIN_CVTW2MASK512,
+ IX86_BUILTIN_CVTMASK2B512,
+ IX86_BUILTIN_CVTMASK2W512,
+ IX86_BUILTIN_PCMPEQB512_MASK,
+ IX86_BUILTIN_PCMPEQW512_MASK,
+ IX86_BUILTIN_PCMPGTB512_MASK,
+ IX86_BUILTIN_PCMPGTW512_MASK,
+ IX86_BUILTIN_PTESTMB512,
+ IX86_BUILTIN_PTESTMW512,
+ IX86_BUILTIN_PTESTNMB512,
+ IX86_BUILTIN_PTESTNMW512,
+ IX86_BUILTIN_PSLLVV32HI,
+ IX86_BUILTIN_PABSB512,
+ IX86_BUILTIN_PABSW512,
+ IX86_BUILTIN_BLENDMW512,
+ IX86_BUILTIN_BLENDMB512,
+ IX86_BUILTIN_CMPB512,
+ IX86_BUILTIN_CMPW512,
+ IX86_BUILTIN_UCMPB512,
+ IX86_BUILTIN_UCMPW512,
+
/* Alternate 4 and 8 element gather/scatter for the vectorizer
where all operands are 32-byte or 64-byte wide respectively. */
IX86_BUILTIN_GATHERALTSIV4DF,
@@ -29345,6 +30334,108 @@ static const struct builtin_description bdesc_special_args[] =
{ OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
{ OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
{ OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
+
+ /* AVX512BW */
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
+
+ /* AVX512VL */
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
};
/* Builtins with variable number of arguments. */
@@ -30404,6 +31495,848 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
{ OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
+
+ /* AVX512VL. */
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv4di_mask, "__builtin_ia32_pbroadcastq256_mem_mask", IX86_BUILTIN_PBROADCASTQ256_MEM_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512vl_vec_dup_memv2di_mask, "__builtin_ia32_pbroadcastq128_mem_mask", IX86_BUILTIN_PBROADCASTQ128_MEM_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
+ { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
+
+ /* AVX512DQ. */
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
+
+ /* AVX512BW. */
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
+ { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
};
/* Builtins with rounding support. */
@@ -30541,6 +32474,24 @@ static const struct builtin_description bdesc_round_args[] =
{ OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
{ OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
{ OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
+
+ /* AVX512DQ. */
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
+ { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
};
/* FMA4 and XOP. */
@@ -33818,6 +35769,28 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V4DI_FTYPE_V4SI:
case V4DI_FTYPE_V2DI:
case HI_FTYPE_HI:
+ case HI_FTYPE_V16QI:
+ case SI_FTYPE_V32QI:
+ case DI_FTYPE_V64QI:
+ case V16QI_FTYPE_HI:
+ case V32QI_FTYPE_SI:
+ case V64QI_FTYPE_DI:
+ case V8HI_FTYPE_QI:
+ case V16HI_FTYPE_HI:
+ case V32HI_FTYPE_SI:
+ case V4SI_FTYPE_QI:
+ case V8SI_FTYPE_QI:
+ case V4SI_FTYPE_HI:
+ case V8SI_FTYPE_HI:
+ case QI_FTYPE_V8HI:
+ case HI_FTYPE_V16HI:
+ case SI_FTYPE_V32HI:
+ case QI_FTYPE_V4SI:
+ case QI_FTYPE_V8SI:
+ case HI_FTYPE_V16SI:
+ case QI_FTYPE_V2DI:
+ case QI_FTYPE_V4DI:
+ case QI_FTYPE_V8DI:
case UINT_FTYPE_V2DF:
case UINT_FTYPE_V4SF:
case UINT64_FTYPE_V2DF:
@@ -33825,6 +35798,8 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V16QI_FTYPE_V8DI:
case V16HI_FTYPE_V16SI:
case V16SI_FTYPE_HI:
+ case V2DI_FTYPE_QI:
+ case V4DI_FTYPE_QI:
case V16SI_FTYPE_V16SI:
case V16SI_FTYPE_INT:
case V16SF_FTYPE_FLOAT:
@@ -33836,7 +35811,6 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V8HI_FTYPE_V8DI:
case V8UHI_FTYPE_V8UHI:
case V8SI_FTYPE_V8DI:
- case V8USI_FTYPE_V8USI:
case V8SF_FTYPE_V8DF:
case V8DI_FTYPE_QI:
case V8DI_FTYPE_INT64:
@@ -33917,6 +35891,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V4DI_FTYPE_V8SI_V8SI:
case V4UDI_FTYPE_V8USI_V8USI:
case QI_FTYPE_V8DI_V8DI:
+ case V8DI_FTYPE_V64QI_V64QI:
case HI_FTYPE_V16SI_V16SI:
if (comparison == UNKNOWN)
return ix86_expand_binop_builtin (icode, exp, target);
@@ -33956,6 +35931,8 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case UINT16_FTYPE_UINT16_INT:
case UINT8_FTYPE_UINT8_INT:
case HI_FTYPE_HI_HI:
+ case SI_FTYPE_SI_SI:
+ case DI_FTYPE_DI_DI:
case V16SI_FTYPE_V8DF_V8DF:
nargs = 2;
break;
@@ -33969,6 +35946,11 @@ ix86_expand_args_builtin (const struct builtin_description *d,
rmode = V2TImode;
nargs_constant = 1;
break;
+ case V8DI_FTYPE_V8DI_INT_CONVERT:
+ nargs = 2;
+ rmode = V4TImode;
+ nargs_constant = 1;
+ break;
case V8HI_FTYPE_V8HI_INT:
case V8HI_FTYPE_V8SF_INT:
case V16HI_FTYPE_V16SF_INT:
@@ -33994,6 +35976,8 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V2DI_FTYPE_V4DI_INT:
case V4DI_FTYPE_V8DI_INT:
case HI_FTYPE_HI_INT:
+ case QI_FTYPE_V4SF_INT:
+ case QI_FTYPE_V2DF_INT:
nargs = 2;
nargs_constant = 1;
break;
@@ -34018,20 +36002,118 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V16SI_FTYPE_V16HI_V16SI_HI:
case V16SI_FTYPE_V16QI_V16SI_HI:
case V16SI_FTYPE_V16SF_V16SI_HI:
+ case V8SF_FTYPE_V4SF_V8SF_QI:
+ case V4DF_FTYPE_V2DF_V4DF_QI:
+ case V8SI_FTYPE_V4SI_V8SI_QI:
+ case V8SI_FTYPE_SI_V8SI_QI:
+ case V4SI_FTYPE_V4SI_V4SI_QI:
+ case V4SI_FTYPE_SI_V4SI_QI:
+ case V4DI_FTYPE_V2DI_V4DI_QI:
+ case V4DI_FTYPE_DI_V4DI_QI:
+ case V2DI_FTYPE_V2DI_V2DI_QI:
+ case V2DI_FTYPE_DI_V2DI_QI:
+ case V64QI_FTYPE_V64QI_V64QI_DI:
+ case V64QI_FTYPE_V16QI_V64QI_DI:
+ case V64QI_FTYPE_QI_V64QI_DI:
+ case V32QI_FTYPE_V32QI_V32QI_SI:
+ case V32QI_FTYPE_V16QI_V32QI_SI:
+ case V32QI_FTYPE_QI_V32QI_SI:
+ case V16QI_FTYPE_V16QI_V16QI_HI:
+ case V16QI_FTYPE_QI_V16QI_HI:
+ case V32HI_FTYPE_V8HI_V32HI_SI:
+ case V32HI_FTYPE_HI_V32HI_SI:
+ case V16HI_FTYPE_V8HI_V16HI_HI:
+ case V16HI_FTYPE_HI_V16HI_HI:
+ case V8HI_FTYPE_V8HI_V8HI_QI:
+ case V8HI_FTYPE_HI_V8HI_QI:
+ case V8SF_FTYPE_V8HI_V8SF_QI:
+ case V4SF_FTYPE_V8HI_V4SF_QI:
+ case V8SI_FTYPE_V8SF_V8SI_QI:
+ case V4SI_FTYPE_V4SF_V4SI_QI:
+ case V8DI_FTYPE_V8SF_V8DI_QI:
+ case V4DI_FTYPE_V4SF_V4DI_QI:
+ case V2DI_FTYPE_V4SF_V2DI_QI:
+ case V8SF_FTYPE_V8DI_V8SF_QI:
+ case V4SF_FTYPE_V4DI_V4SF_QI:
+ case V4SF_FTYPE_V2DI_V4SF_QI:
+ case V8DF_FTYPE_V8DI_V8DF_QI:
+ case V4DF_FTYPE_V4DI_V4DF_QI:
+ case V2DF_FTYPE_V2DI_V2DF_QI:
+ case V16QI_FTYPE_V8HI_V16QI_QI:
+ case V16QI_FTYPE_V16HI_V16QI_HI:
+ case V16QI_FTYPE_V4SI_V16QI_QI:
+ case V16QI_FTYPE_V8SI_V16QI_QI:
+ case V8HI_FTYPE_V4SI_V8HI_QI:
+ case V8HI_FTYPE_V8SI_V8HI_QI:
+ case V16QI_FTYPE_V2DI_V16QI_QI:
+ case V16QI_FTYPE_V4DI_V16QI_QI:
+ case V8HI_FTYPE_V2DI_V8HI_QI:
+ case V8HI_FTYPE_V4DI_V8HI_QI:
+ case V4SI_FTYPE_V2DI_V4SI_QI:
+ case V4SI_FTYPE_V4DI_V4SI_QI:
+ case V32QI_FTYPE_V32HI_V32QI_SI:
+ case HI_FTYPE_V16QI_V16QI_HI:
+ case SI_FTYPE_V32QI_V32QI_SI:
+ case DI_FTYPE_V64QI_V64QI_DI:
+ case QI_FTYPE_V8HI_V8HI_QI:
+ case HI_FTYPE_V16HI_V16HI_HI:
+ case SI_FTYPE_V32HI_V32HI_SI:
+ case QI_FTYPE_V4SI_V4SI_QI:
+ case QI_FTYPE_V8SI_V8SI_QI:
+ case QI_FTYPE_V2DI_V2DI_QI:
+ case QI_FTYPE_V4DI_V4DI_QI:
+ case V4SF_FTYPE_V2DF_V4SF_QI:
+ case V4SF_FTYPE_V4DF_V4SF_QI:
+ nargs = 3;
case V16SI_FTYPE_V16SI_V16SI_HI:
case V16SI_FTYPE_V16SI_V16SI_V16SI:
case V16SI_FTYPE_V4SI_V16SI_HI:
case V2DI_FTYPE_V2DI_V2DI_V2DI:
+ case V2DI_FTYPE_V4SI_V2DI_QI:
+ case V2DI_FTYPE_V8HI_V2DI_QI:
+ case V2DI_FTYPE_V16QI_V2DI_QI:
+ case V4DI_FTYPE_V4DI_V4DI_QI:
+ case V4DI_FTYPE_V4SI_V4DI_QI:
+ case V4DI_FTYPE_V8HI_V4DI_QI:
+ case V4DI_FTYPE_V16QI_V4DI_QI:
+ case V8DI_FTYPE_V8DF_V8DI_QI:
+ case V4DI_FTYPE_V4DF_V4DI_QI:
+ case V2DI_FTYPE_V2DF_V2DI_QI:
+ case V4SI_FTYPE_V4DF_V4SI_QI:
+ case V4SI_FTYPE_V2DF_V4SI_QI:
+ case V4SI_FTYPE_V8HI_V4SI_QI:
+ case V4SI_FTYPE_V16QI_V4SI_QI:
+ case V8SI_FTYPE_V8SI_V8SI_V8SI:
case V4DI_FTYPE_V4DI_V4DI_V4DI:
case V8DF_FTYPE_V2DF_V8DF_QI:
case V8DF_FTYPE_V4DF_V8DF_QI:
case V8DF_FTYPE_V8DF_V8DF_QI:
case V8DF_FTYPE_V8DF_V8DF_V8DF:
+ case V8SF_FTYPE_V8SF_V8SF_QI:
+ case V8SF_FTYPE_V8SI_V8SF_QI:
+ case V4DF_FTYPE_V4DF_V4DF_QI:
+ case V4SF_FTYPE_V4SF_V4SF_QI:
+ case V2DF_FTYPE_V2DF_V2DF_QI:
+ case V2DF_FTYPE_V4SF_V2DF_QI:
+ case V2DF_FTYPE_V4SI_V2DF_QI:
+ case V4SF_FTYPE_V4SI_V4SF_QI:
+ case V4DF_FTYPE_V4SF_V4DF_QI:
+ case V4DF_FTYPE_V4SI_V4DF_QI:
+ case V8SI_FTYPE_V8SI_V8SI_QI:
+ case V8SI_FTYPE_V8HI_V8SI_QI:
+ case V8SI_FTYPE_V16QI_V8SI_QI:
case V8DF_FTYPE_V8DF_V8DI_V8DF:
case V8DF_FTYPE_V8DI_V8DF_V8DF:
case V8DF_FTYPE_V8SF_V8DF_QI:
case V8DF_FTYPE_V8SI_V8DF_QI:
case V8DI_FTYPE_DI_V8DI_QI:
+ case V16SF_FTYPE_V8SF_V16SF_HI:
+ case V16SI_FTYPE_V8SI_V16SI_HI:
+ case V16HI_FTYPE_V16HI_V16HI_HI:
+ case V8HI_FTYPE_V16QI_V8HI_QI:
+ case V16HI_FTYPE_V16QI_V16HI_HI:
+ case V32HI_FTYPE_V32HI_V32HI_SI:
+ case V32HI_FTYPE_V32QI_V32HI_SI:
case V8DI_FTYPE_V16QI_V8DI_QI:
case V8DI_FTYPE_V2DI_V8DI_QI:
case V8DI_FTYPE_V4DI_V8DI_QI:
@@ -34093,13 +36175,80 @@ ix86_expand_args_builtin (const struct builtin_description *d,
nargs = 3;
nargs_constant = 2;
break;
+ case V8DI_FTYPE_V8DI_V8DI_INT_CONVERT:
+ nargs = 3;
+ rmode = V8DImode;
+ nargs_constant = 1;
+ break;
+ case V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT:
+ nargs = 5;
+ rmode = V8DImode;
+ mask_pos = 2;
+ nargs_constant = 1;
+ break;
+ case QI_FTYPE_V8DF_INT_QI:
+ case QI_FTYPE_V4DF_INT_QI:
+ case QI_FTYPE_V2DF_INT_QI:
+ case HI_FTYPE_V16SF_INT_HI:
+ case QI_FTYPE_V8SF_INT_QI:
+ case QI_FTYPE_V4SF_INT_QI:
+ nargs = 3;
+ mask_pos = 1;
+ nargs_constant = 1;
+ break;
+ case V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT:
+ nargs = 5;
+ rmode = V4DImode;
+ mask_pos = 2;
+ nargs_constant = 1;
+ break;
+ case V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT:
+ nargs = 5;
+ rmode = V2DImode;
+ mask_pos = 2;
+ nargs_constant = 1;
+ break;
+ case V32QI_FTYPE_V32QI_V32QI_V32QI_SI:
+ case V32HI_FTYPE_V32HI_V32HI_V32HI_SI:
+ case V32HI_FTYPE_V64QI_V64QI_V32HI_SI:
+ case V16SI_FTYPE_V32HI_V32HI_V16SI_HI:
+ case V64QI_FTYPE_V64QI_V64QI_V64QI_DI:
+ case V32HI_FTYPE_V32HI_V8HI_V32HI_SI:
+ case V16HI_FTYPE_V16HI_V8HI_V16HI_HI:
+ case V8SI_FTYPE_V8SI_V4SI_V8SI_QI:
+ case V4DI_FTYPE_V4DI_V2DI_V4DI_QI:
+ case V64QI_FTYPE_V32HI_V32HI_V64QI_DI:
+ case V32QI_FTYPE_V16HI_V16HI_V32QI_SI:
+ case V16QI_FTYPE_V8HI_V8HI_V16QI_HI:
+ case V32HI_FTYPE_V16SI_V16SI_V32HI_SI:
+ case V16HI_FTYPE_V8SI_V8SI_V16HI_HI:
+ case V8HI_FTYPE_V4SI_V4SI_V8HI_QI:
+ case V4DF_FTYPE_V4DF_V4DI_V4DF_QI:
+ case V8SF_FTYPE_V8SF_V8SI_V8SF_QI:
+ case V4SF_FTYPE_V4SF_V4SI_V4SF_QI:
+ case V2DF_FTYPE_V2DF_V2DI_V2DF_QI:
+ case V2DI_FTYPE_V4SI_V4SI_V2DI_QI:
+ case V4DI_FTYPE_V8SI_V8SI_V4DI_QI:
+ case V4DF_FTYPE_V4DI_V4DF_V4DF_QI:
+ case V8SF_FTYPE_V8SI_V8SF_V8SF_QI:
+ case V2DF_FTYPE_V2DI_V2DF_V2DF_QI:
+ case V4SF_FTYPE_V4SI_V4SF_V4SF_QI:
case V16SF_FTYPE_V16SF_V16SF_V16SF_HI:
case V16SF_FTYPE_V16SF_V16SI_V16SF_HI:
case V16SF_FTYPE_V16SI_V16SF_V16SF_HI:
case V16SI_FTYPE_V16SI_V16SI_V16SI_HI:
case V16SI_FTYPE_V16SI_V4SI_V16SI_HI:
+ case V8HI_FTYPE_V8HI_V8HI_V8HI_QI:
+ case V8SI_FTYPE_V8SI_V8SI_V8SI_QI:
+ case V4SI_FTYPE_V4SI_V4SI_V4SI_QI:
+ case V8SF_FTYPE_V8SF_V8SF_V8SF_QI:
+ case V16QI_FTYPE_V16QI_V16QI_V16QI_HI:
+ case V16HI_FTYPE_V16HI_V16HI_V16HI_HI:
+ case V2DI_FTYPE_V2DI_V2DI_V2DI_QI:
case V2DF_FTYPE_V2DF_V2DF_V2DF_QI:
case V2DF_FTYPE_V2DF_V4SF_V2DF_QI:
+ case V4DI_FTYPE_V4DI_V4DI_V4DI_QI:
+ case V4DF_FTYPE_V4DF_V4DF_V4DF_QI:
case V4SF_FTYPE_V4SF_V2DF_V4SF_QI:
case V4SF_FTYPE_V4SF_V4SF_V4SF_QI:
case V8DF_FTYPE_V8DF_V8DF_V8DF_QI:
@@ -34109,6 +36258,10 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V8DI_FTYPE_V8DI_SI_V8DI_V8DI:
case V8DI_FTYPE_V8DI_V2DI_V8DI_QI:
case V8DI_FTYPE_V8DI_V8DI_V8DI_QI:
+ case V8HI_FTYPE_V16QI_V16QI_V8HI_QI:
+ case V16HI_FTYPE_V32QI_V32QI_V16HI_HI:
+ case V8SI_FTYPE_V16HI_V16HI_V8SI_QI:
+ case V4SI_FTYPE_V8HI_V8HI_V4SI_QI:
nargs = 4;
break;
case V2DF_FTYPE_V2DF_V2DF_V2DI_INT:
@@ -34119,8 +36272,20 @@ ix86_expand_args_builtin (const struct builtin_description *d,
nargs = 4;
nargs_constant = 1;
break;
+ case QI_FTYPE_V4DI_V4DI_INT_QI:
+ case QI_FTYPE_V8SI_V8SI_INT_QI:
+ case QI_FTYPE_V4DF_V4DF_INT_QI:
+ case QI_FTYPE_V8SF_V8SF_INT_QI:
+ case QI_FTYPE_V2DI_V2DI_INT_QI:
+ case QI_FTYPE_V4SI_V4SI_INT_QI:
case QI_FTYPE_V2DF_V2DF_INT_QI:
case QI_FTYPE_V4SF_V4SF_INT_QI:
+ case DI_FTYPE_V64QI_V64QI_INT_DI:
+ case SI_FTYPE_V32QI_V32QI_INT_SI:
+ case HI_FTYPE_V16QI_V16QI_INT_HI:
+ case SI_FTYPE_V32HI_V32HI_INT_SI:
+ case HI_FTYPE_V16HI_V16HI_INT_HI:
+ case QI_FTYPE_V8HI_V8HI_INT_QI:
nargs = 4;
mask_pos = 1;
nargs_constant = 1;
@@ -34141,6 +36306,27 @@ ix86_expand_args_builtin (const struct builtin_description *d,
nargs = 4;
nargs_constant = 1;
break;
+ case V8SF_FTYPE_V8SF_INT_V8SF_QI:
+ case V4SF_FTYPE_V4SF_INT_V4SF_QI:
+ case V2DF_FTYPE_V4DF_INT_V2DF_QI:
+ case V2DI_FTYPE_V4DI_INT_V2DI_QI:
+ case V8SF_FTYPE_V16SF_INT_V8SF_QI:
+ case V8SI_FTYPE_V16SI_INT_V8SI_QI:
+ case V2DF_FTYPE_V8DF_INT_V2DF_QI:
+ case V2DI_FTYPE_V8DI_INT_V2DI_QI:
+ case V4SF_FTYPE_V8SF_INT_V4SF_QI:
+ case V4SI_FTYPE_V8SI_INT_V4SI_QI:
+ case V8HI_FTYPE_V8SF_INT_V8HI_QI:
+ case V8HI_FTYPE_V4SF_INT_V8HI_QI:
+ case V32HI_FTYPE_V32HI_INT_V32HI_SI:
+ case V16HI_FTYPE_V16HI_INT_V16HI_HI:
+ case V8HI_FTYPE_V8HI_INT_V8HI_QI:
+ case V4DI_FTYPE_V4DI_INT_V4DI_QI:
+ case V2DI_FTYPE_V2DI_INT_V2DI_QI:
+ case V8SI_FTYPE_V8SI_INT_V8SI_QI:
+ case V4SI_FTYPE_V4SI_INT_V4SI_QI:
+ case V4DF_FTYPE_V4DF_INT_V4DF_QI:
+ case V2DF_FTYPE_V2DF_INT_V2DF_QI:
case V8DF_FTYPE_V8DF_INT_V8DF_QI:
case V16SF_FTYPE_V16SF_INT_V16SF_HI:
case V16HI_FTYPE_V16SF_INT_V16HI_HI:
@@ -34164,6 +36350,23 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI:
case V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI:
case V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI:
+ case V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI:
+ case V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI:
+ case V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI:
+ case V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI:
+ case V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI:
+ case V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI:
+ case V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI:
+ case V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI:
+ case V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI:
+ case V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI:
+ case V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI:
+ case V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI:
+ case V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI:
+ case V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI:
+ case V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI:
+ case V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI:
+ case V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI:
nargs = 5;
mask_pos = 2;
nargs_constant = 1;
@@ -34173,6 +36376,13 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI:
case V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI:
case V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI:
+ case V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI:
+ case V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI:
+ case V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI:
+ case V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI:
+ case V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI:
+ case V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI:
+ nargs = 5;
nargs = 5;
mask_pos = 1;
nargs_constant = 1;
@@ -34621,7 +36831,11 @@ ix86_expand_round_builtin (const struct builtin_description *d,
case V8SF_FTYPE_V8DF_V8SF_QI_INT:
case V8DF_FTYPE_V8DF_V8DF_QI_INT:
case V8SI_FTYPE_V8DF_V8SI_QI_INT:
+ case V8DI_FTYPE_V8DF_V8DI_QI_INT:
+ case V8SF_FTYPE_V8DI_V8SF_QI_INT:
+ case V8DF_FTYPE_V8DI_V8DF_QI_INT:
case V16SF_FTYPE_V16SF_V16SF_HI_INT:
+ case V8DI_FTYPE_V8SF_V8DI_QI_INT:
case V16SF_FTYPE_V16SI_V16SF_HI_INT:
case V16SI_FTYPE_V16SF_V16SI_HI_INT:
case V8DF_FTYPE_V8SF_V8DF_QI_INT:
@@ -34658,6 +36872,8 @@ ix86_expand_round_builtin (const struct builtin_description *d,
nargs_constant = 3;
nargs = 5;
break;
+ case V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT:
+ case V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT:
case V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI_INT:
case V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI_INT:
nargs = 6;
@@ -34920,7 +37136,11 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
case VOID_FTYPE_PV8DF_V8DF_QI:
case VOID_FTYPE_PV16SF_V16SF_HI:
case VOID_FTYPE_PV8DI_V8DI_QI:
+ case VOID_FTYPE_PV4DI_V4DI_QI:
+ case VOID_FTYPE_PV2DI_V2DI_QI:
case VOID_FTYPE_PV16SI_V16SI_HI:
+ case VOID_FTYPE_PV8SI_V8SI_QI:
+ case VOID_FTYPE_PV4SI_V4SI_QI:
switch (icode)
{
/* These builtins and instructions require the memory
@@ -34958,17 +37178,51 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
case VOID_FTYPE_PV16HI_V16SI_HI:
case VOID_FTYPE_PV16QI_V8DI_QI:
case VOID_FTYPE_PV16QI_V16SI_HI:
+ case VOID_FTYPE_PV4SI_V4DI_QI:
+ case VOID_FTYPE_PV4SI_V2DI_QI:
+ case VOID_FTYPE_PV8HI_V4DI_QI:
+ case VOID_FTYPE_PV8HI_V2DI_QI:
+ case VOID_FTYPE_PV8HI_V8SI_QI:
+ case VOID_FTYPE_PV8HI_V4SI_QI:
+ case VOID_FTYPE_PV16QI_V4DI_QI:
+ case VOID_FTYPE_PV16QI_V2DI_QI:
+ case VOID_FTYPE_PV16QI_V8SI_QI:
+ case VOID_FTYPE_PV16QI_V4SI_QI:
+ case VOID_FTYPE_PV8HI_V8HI_QI:
+ case VOID_FTYPE_PV16HI_V16HI_HI:
+ case VOID_FTYPE_PV32HI_V32HI_SI:
+ case VOID_FTYPE_PV16QI_V16QI_HI:
+ case VOID_FTYPE_PV32QI_V32QI_SI:
+ case VOID_FTYPE_PV64QI_V64QI_DI:
+ case VOID_FTYPE_PV4DF_V4DF_QI:
+ case VOID_FTYPE_PV2DF_V2DF_QI:
+ case VOID_FTYPE_PV8SF_V8SF_QI:
+ case VOID_FTYPE_PV4SF_V4SF_QI:
nargs = 2;
klass = store;
/* Reserve memory operand for target. */
memory = ARRAY_SIZE (args);
break;
+ case V4SF_FTYPE_PCV4SF_V4SF_QI:
+ case V8SF_FTYPE_PCV8SF_V8SF_QI:
case V16SF_FTYPE_PCV16SF_V16SF_HI:
+ case V4SI_FTYPE_PCV4SI_V4SI_QI:
+ case V8SI_FTYPE_PCV8SI_V8SI_QI:
case V16SI_FTYPE_PCV16SI_V16SI_HI:
+ case V2DF_FTYPE_PCV2DF_V2DF_QI:
+ case V4DF_FTYPE_PCV4DF_V4DF_QI:
case V8DF_FTYPE_PCV8DF_V8DF_QI:
+ case V2DI_FTYPE_PCV2DI_V2DI_QI:
+ case V4DI_FTYPE_PCV4DI_V4DI_QI:
case V8DI_FTYPE_PCV8DI_V8DI_QI:
case V2DF_FTYPE_PCDOUBLE_V2DF_QI:
case V4SF_FTYPE_PCFLOAT_V4SF_QI:
+ case V8HI_FTYPE_PCV8HI_V8HI_QI:
+ case V16HI_FTYPE_PCV16HI_V16HI_HI:
+ case V32HI_FTYPE_PCV32HI_V32HI_SI:
+ case V16QI_FTYPE_PCV16QI_V16QI_HI:
+ case V32QI_FTYPE_PCV32QI_V32QI_SI:
+ case V64QI_FTYPE_PCV64QI_V64QI_DI:
nargs = 3;
klass = load;
memory = 0;
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH i386 AVX512] [81.2/n] Add new built-ins.
2014-10-23 12:58 ` [PATCH i386 AVX512] [81.2/n] " Kirill Yukhin
@ 2014-10-23 13:46 ` Uros Bizjak
0 siblings, 0 replies; 16+ messages in thread
From: Uros Bizjak @ 2014-10-23 13:46 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Jakub Jelinek, Richard Henderson, GCC Patches
On Thu, Oct 23, 2014 at 2:50 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Hello Uroš,
> On 20 Oct 17:41, Kirill Yukhin wrote:
>> This patch adds (almost) all built-ins
> This is second, target dependent, part of the initial patch.
>
> ChangeLog is the same as in intial mail - tree* changes.
>
> Is it ok for trunk?
OK.
(I was not able to review this huge patch in detail, but the approach
is OK and these are fairly mechanical additions).
Thanks,
Uros.
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2014-10-23 13:24 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-10-20 13:50 [PATCH i386 AVX512] [81/n] Add new built-ins Kirill Yukhin
2014-10-20 13:56 ` Jakub Jelinek
2014-10-21 9:19 ` Richard Biener
2014-10-21 14:19 ` Kirill Yukhin
2014-10-21 14:09 ` Kirill Yukhin
2014-10-21 14:21 ` Jakub Jelinek
2014-10-21 14:52 ` Kirill Yukhin
2014-10-21 15:13 ` Kirill Yukhin
2014-10-22 8:18 ` Richard Biener
2014-10-22 11:40 ` Kirill Yukhin
2014-10-22 11:43 ` Jakub Jelinek
2014-10-22 7:57 ` [PATCH AVX512] [81.1/n] Extend `function_code' field in `tree_var_decl' structure Kirill Yukhin
2014-10-23 11:10 ` Jakub Jelinek
2014-10-21 14:24 ` [PATCH i386 AVX512] [81/n] Add new built-ins Richard Biener
2014-10-23 12:58 ` [PATCH i386 AVX512] [81.2/n] " Kirill Yukhin
2014-10-23 13:46 ` Uros Bizjak
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