From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 60502 invoked by alias); 10 Apr 2015 08:57:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 60467 invoked by uid 89); 10 Apr 2015 08:57:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Fri, 10 Apr 2015 08:57:30 +0000 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id t3A8vP1W028645 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 10 Apr 2015 04:57:25 -0400 Received: from tucnak.zalov.cz (ovpn-116-24.ams2.redhat.com [10.36.116.24]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t3A8vNW4018827 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 10 Apr 2015 04:57:24 -0400 Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.14.9/8.14.9) with ESMTP id t3A8vLuB008065; Fri, 10 Apr 2015 10:57:22 +0200 Received: (from jakub@localhost) by tucnak.zalov.cz (8.14.9/8.14.9/Submit) id t3A8vKEw008064; Fri, 10 Apr 2015 10:57:20 +0200 Date: Fri, 10 Apr 2015 08:57:00 -0000 From: Jakub Jelinek To: Kyrill Tkachov Cc: GCC Patches , Ramana Radhakrishnan , Richard Earnshaw Subject: Re: [PATCH][ARM] PR 65694: Properly sign-extend large numbers before passing to GEN_INT in arm_canonicalize_comparison Message-ID: <20150410085720.GS19273@tucnak.redhat.com> Reply-To: Jakub Jelinek References: <55278AC7.9070807@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <55278AC7.9070807@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes X-SW-Source: 2015-04/txt/msg00440.txt.bz2 On Fri, Apr 10, 2015 at 09:33:11AM +0100, Kyrill Tkachov wrote: > 2015-04-09 Kyrylo Tkachov > Missing PR target/65694 line here. > * config/arm/arm.c (arm_canonicalize_comparison): Use ARM_SIGN_EXTEND > when creating +1 values for SImode and trunc_int_for_mode for similar > DImode operations. > > 2015-04-09 Kyrylo Tkachov > Ditto. > * g++.dg/torture/pr65694.C: New test. > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index 369cb67..5342b33 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -4984,7 +4984,7 @@ arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1, > if (i != maxval > && arm_const_double_by_immediates (GEN_INT (i + 1))) > { > - *op1 = GEN_INT (i + 1); > + *op1 = GEN_INT (trunc_int_for_mode (i + 1, DImode)); > *code = *code == GT ? GE : LT; > return; > } > @@ -4994,7 +4994,7 @@ arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1, > if (i != ~((unsigned HOST_WIDE_INT) 0) > && arm_const_double_by_immediates (GEN_INT (i + 1))) > { > - *op1 = GEN_INT (i + 1); > + *op1 = GEN_INT (trunc_int_for_mode (i + 1, DImode)); The above two aren't strictly necessary, HOST_WIDE_INT is always 64-bit, so is DImode, and GEN_INT takes HOST_WIDE_INT. You haven't changed it in the GEN_INT (i + 1) calls passed to arm_const_double_by_immediates anyway. I'd think you can leave those changes to cleanup in stage1 if desirable. > @@ -5047,7 +5047,7 @@ arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1, > if (i != maxval > && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) > { > - *op1 = GEN_INT (i + 1); > + *op1 = GEN_INT (ARM_SIGN_EXTEND (i + 1)); > *code = *code == GT ? GE : LT; > return; > } > @@ -5069,7 +5069,7 @@ arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1, > if (i != ~((unsigned HOST_WIDE_INT) 0) > && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) > { > - *op1 = GEN_INT (i + 1); > + *op1 = GEN_INT (ARM_SIGN_EXTEND (i + 1)); > *code = *code == GTU ? GEU : LTU; > return; > } This looks ok to me, but I'll defer the final word to ARM maintainers. That said, the ARM_SIGN_EXTEND macro could very well use some cleanup too now that HOST_WIDE_INT is always 64-bit and one can e.g. use HOST_WIDE_INT_{U,}C macros to build large constants. Jakub