From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 80067 invoked by alias); 23 Apr 2015 01:55:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 79806 invoked by uid 89); 23 Apr 2015 01:55:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gate.crashing.org Received: from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Thu, 23 Apr 2015 01:55:39 +0000 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id t3N1tZl6015586; Wed, 22 Apr 2015 20:55:35 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id t3N1tYw7015585; Wed, 22 Apr 2015 20:55:34 -0500 Date: Thu, 23 Apr 2015 01:55:00 -0000 From: Segher Boessenkool To: Peter Bergner Cc: GCC Patches , David Edelsohn , Michael Meissner , Bill Schmidt Subject: Re: [PATCH, rs6000, testsuite] Fix PR target/64579, __TM_end __builtin_tend failed to return transactional state Message-ID: <20150423015534.GB29172@gate.crashing.org> References: <1426879660.13627.71.camel@otta> <20150320205200.GA32613@gate.crashing.org> <1426891319.13627.101.camel@otta> <1429649778.21947.25.camel@otta> <20150422021759.GC23315@gate.crashing.org> <1429710190.21947.48.camel@otta> <20150422221633.GA29172@gate.crashing.org> <1429744106.21947.56.camel@otta> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1429744106.21947.56.camel@otta> User-Agent: Mutt/1.4.2.3i X-IsSubscribed: yes X-SW-Source: 2015-04/txt/msg01377.txt.bz2 On Wed, Apr 22, 2015 at 06:08:26PM -0500, Peter Bergner wrote: > > > > > + case HTM_BUILTIN_TTEST: /* Alias for: tabortwci. 0,r0,0 */ > > > > > + op[nopnds++] = GEN_INT (0); > > > > > + op[nopnds++] = gen_rtx_REG (SImode, 0); > > > > > + op[nopnds++] = GEN_INT (0); > > > > > > > > Is that really r0, isn't that (0|rA)? [Too lazy to read the docs myself > > > > right now, sorry.] > > > > > > The ISA doc shows: > > > > [snip] > > > > Thanks for looking it up! > > > > I'm still a bit worried about putting a reg in the RTL (while the instruction > > doesn't actually use one), but perhaps it's harmless. > > I'm not sure what you mean by the "instruction doesn't use one". > The hardware instruction does use a register for its second > operand (even though its contents are ignored due to TO == 0) > and the pattern requires us to pass in a reg rtx, so I'm not > sure what you're referring to. I mean the instruction doesn't actually use the value in the register (if it did, you couldn't just pass in a non-fixed hard register in RTL). Using a hard reg in the RTL like this has a few problems: a) It might hinder register allocation. Maybe it doesn't, not sure; b) It does hinder scheduling; c) It can make things ICE, maybe with register asm. I no longer think c) will happen in this case. The alternative is to write a separate define_insn for ttest, one without inputs; the generated assembler can still be the same of course. Cheers, Segher