* [PATCH] PR target/65849 -- Add additional options to powerpc #pragma/attribute target support
@ 2015-04-23 19:25 Michael Meissner
2015-04-24 13:51 ` David Edelsohn
0 siblings, 1 reply; 2+ messages in thread
From: Michael Meissner @ 2015-04-23 19:25 UTC (permalink / raw)
To: gcc-patches, dje.gcc; +Cc: sjmunroe
[-- Attachment #1: Type: text/plain, Size: 1761 bytes --]
Steve Munroe was tuning an application on PowerPC, and needed to set the
-msave-toc-indirect option for only one function, and it wasn't available via
the #praga/attribute target options. This patch adds support for the
additional options that don't involve an ABI change to the list of options that
can be set via the #pragma GCC target or attribute((target(...))) support.
I have bootstrapped the compiler on a power7 (big endian) and power8 (little
endian) with no regressions. Is this patch ok to install? I would like to
backport this patch to the current branches (5.x, 4.9, 4.8, maybe 4.7). Is
this ok?
[gcc]
2015-04-23 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/65849
* config/rs6000/rs6000.opt (-mvsx-align-128): Make options that
save to independent variables use the Save attribute. This will
allow these options to be modified with the #pragma/attribute
target support.
(-mallow-movmisalign): Likewise.
(-mallow-df-permute): Likewise.
(-msched-groups): Likewise.
(-malways-hint): Likewise.
(-malign-branch-targets): Likewise.
(-mvectorize-builtins): Likewise.
(-msave-toc-indirect): Likewise.
* config/rs6000/rs6000.c (rs6000_opt_masks): Add more options that
can be set via the #pragma/attribute target support.
(rs6000_opt_vars): Likewise.
(rs6000_inner_target_options): If VSX was set, also set
-mno-avoid-indexed-addresses.
[gcc/testsuite]
2015-04-23 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/65849
* gcc.target/powerpc/pr65849-1.c: New test to verify being able to
set new options.
* gcc.target/powerpc/pr65849-2.c: Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
[-- Attachment #2: pr65849.patch01b --]
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Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- gcc/config/rs6000/rs6000.opt (revision 222333)
+++ gcc/config/rs6000/rs6000.opt (working copy)
@@ -204,31 +204,31 @@ mvsx-scalar-memory
Target Undocumented Report Alias(mupper-regs-df)
mvsx-align-128
-Target Undocumented Report Var(TARGET_VSX_ALIGN_128)
+Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
; If -mvsx, set alignment to 128 bits instead of 32/64
mallow-movmisalign
-Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1)
+Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
; Allow/disallow the movmisalign in DF/DI vectors
mallow-df-permute
-Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE)
+Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) Save
; Allow/disallow permutation of DF/DI vectors
msched-groups
-Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1)
+Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save
; Explicitly set/unset whether rs6000_sched_groups is set
malways-hint
-Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1)
+Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save
; Explicitly set/unset whether rs6000_always_hint is set
malign-branch-targets
-Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1)
+Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
; Explicitly set/unset whether rs6000_align_branch_targets is set
mvectorize-builtins
-Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1)
+Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) Save
; Explicitly control whether we vectorize the builtins or not.
mno-update
@@ -538,7 +538,7 @@ Target Report Var(TARGET_POINTERS_TO_NES
Use/do not use r11 to hold the static link in calls to functions via pointers.
msave-toc-indirect
-Target Report Var(TARGET_SAVE_TOC_INDIRECT) Save
+Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
Control whether we save the TOC in the prologue for indirect calls or generate the save inline
mvsx-timode
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 222333)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -32194,10 +32194,11 @@ static struct rs6000_opt_mask const rs60
{ "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
{ "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
{ "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
+ { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
{ "string", OPTION_MASK_STRING, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
- { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF, false, false },
- { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF, false, false },
+ { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF, false, true },
+ { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF, false, true },
{ "vsx", OPTION_MASK_VSX, false, true },
{ "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true },
#ifdef OPTION_MASK_64BIT
@@ -32270,6 +32271,42 @@ static struct rs6000_opt_var const rs600
{ "longcall",
offsetof (struct gcc_options, x_rs6000_default_long_calls),
offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
+ { "optimize-swaps",
+ offsetof (struct gcc_options, x_rs6000_optimize_swaps),
+ offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
+ { "allow-movmisalign",
+ offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
+ offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
+ { "allow-df-permute",
+ offsetof (struct gcc_options, x_TARGET_ALLOW_DF_PERMUTE),
+ offsetof (struct cl_target_option, x_TARGET_ALLOW_DF_PERMUTE), },
+ { "sched-groups",
+ offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
+ offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
+ { "always-hint",
+ offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
+ offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
+ { "align-branch-targets",
+ offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
+ offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
+ { "vectorize-builtins",
+ offsetof (struct gcc_options, x_TARGET_VECTORIZE_BUILTINS),
+ offsetof (struct cl_target_option, x_TARGET_VECTORIZE_BUILTINS), },
+ { "tls-markers",
+ offsetof (struct gcc_options, x_tls_markers),
+ offsetof (struct cl_target_option, x_tls_markers), },
+ { "sched-prolog",
+ offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
+ offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
+ { "sched-epilog",
+ offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
+ offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
+ { "gen-cell-microcode",
+ offsetof (struct gcc_options, x_rs6000_gen_cell_microcode),
+ offsetof (struct cl_target_option, x_rs6000_gen_cell_microcode), },
+ { "warn-cell-microcode",
+ offsetof (struct gcc_options, x_rs6000_warn_cell_microcode),
+ offsetof (struct cl_target_option, x_rs6000_warn_cell_microcode), },
};
/* Inner function to handle attribute((target("..."))) and #pragma GCC target
@@ -32343,9 +32380,15 @@ rs6000_inner_target_options (tree args,
rs6000_isa_flags_explicit |= mask;
/* VSX needs altivec, so -mvsx automagically sets
- altivec. */
- if (mask == OPTION_MASK_VSX && !invert)
- mask |= OPTION_MASK_ALTIVEC;
+ altivec and disables -mavoid-indexed-addresses. */
+ if (!invert)
+ {
+ if (mask == OPTION_MASK_VSX)
+ {
+ mask |= OPTION_MASK_ALTIVEC;
+ TARGET_AVOID_XFORM = 0;
+ }
+ }
if (rs6000_opt_masks[i].invert)
invert = !invert;
@@ -32366,6 +32409,7 @@ rs6000_inner_target_options (tree args,
size_t j = rs6000_opt_vars[i].global_offset;
*((int *) ((char *)&global_options + j)) = !invert;
error_p = false;
+ not_valid_p = false;
break;
}
}
Index: gcc/testsuite/gcc.target/powerpc/pr65849-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr65849-1.c (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr65849-1.c (revision 0)
@@ -0,0 +1,728 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+/* { dg-options "-mcpu=power7 -O2 -mno-upper-regs-df" } */
+
+/* Test whether we can enable the -mupper-regs-df with target pragmas. Make
+ sure double values are allocated to the Altivec registers as well as the
+ traditional FPR registers. */
+
+#ifndef TYPE
+#define TYPE double
+#endif
+
+#ifndef MASK_TYPE
+#define MASK_TYPE unsigned long long
+#endif
+
+#define MASK_ONE ((MASK_TYPE)1)
+#define ZERO ((TYPE) 0.0)
+
+#pragma GCC target ("upper-regs-df")
+TYPE
+test_add (const MASK_TYPE *add_mask, const TYPE *add_values,
+ const MASK_TYPE *sub_mask, const TYPE *sub_values,
+ const MASK_TYPE *mul_mask, const TYPE *mul_values,
+ const MASK_TYPE *div_mask, const TYPE *div_values,
+ const MASK_TYPE *eq0_mask, int *eq0_ptr)
+{
+ TYPE value;
+ TYPE value00 = ZERO;
+ TYPE value01 = ZERO;
+ TYPE value02 = ZERO;
+ TYPE value03 = ZERO;
+ TYPE value04 = ZERO;
+ TYPE value05 = ZERO;
+ TYPE value06 = ZERO;
+ TYPE value07 = ZERO;
+ TYPE value08 = ZERO;
+ TYPE value09 = ZERO;
+ TYPE value10 = ZERO;
+ TYPE value11 = ZERO;
+ TYPE value12 = ZERO;
+ TYPE value13 = ZERO;
+ TYPE value14 = ZERO;
+ TYPE value15 = ZERO;
+ TYPE value16 = ZERO;
+ TYPE value17 = ZERO;
+ TYPE value18 = ZERO;
+ TYPE value19 = ZERO;
+ TYPE value20 = ZERO;
+ TYPE value21 = ZERO;
+ TYPE value22 = ZERO;
+ TYPE value23 = ZERO;
+ TYPE value24 = ZERO;
+ TYPE value25 = ZERO;
+ TYPE value26 = ZERO;
+ TYPE value27 = ZERO;
+ TYPE value28 = ZERO;
+ TYPE value29 = ZERO;
+ TYPE value30 = ZERO;
+ TYPE value31 = ZERO;
+ TYPE value32 = ZERO;
+ TYPE value33 = ZERO;
+ TYPE value34 = ZERO;
+ TYPE value35 = ZERO;
+ TYPE value36 = ZERO;
+ TYPE value37 = ZERO;
+ TYPE value38 = ZERO;
+ TYPE value39 = ZERO;
+ MASK_TYPE mask;
+ int eq0;
+
+ while ((mask = *add_mask++) != 0)
+ {
+ value = *add_values++;
+
+ __asm__ (" #reg %0" : "+d" (value));
+
+ if ((mask & (MASK_ONE << 0)) != 0)
+ value00 += value;
+
+ if ((mask & (MASK_ONE << 1)) != 0)
+ value01 += value;
+
+ if ((mask & (MASK_ONE << 2)) != 0)
+ value02 += value;
+
+ if ((mask & (MASK_ONE << 3)) != 0)
+ value03 += value;
+
+ if ((mask & (MASK_ONE << 4)) != 0)
+ value04 += value;
+
+ if ((mask & (MASK_ONE << 5)) != 0)
+ value05 += value;
+
+ if ((mask & (MASK_ONE << 6)) != 0)
+ value06 += value;
+
+ if ((mask & (MASK_ONE << 7)) != 0)
+ value07 += value;
+
+ if ((mask & (MASK_ONE << 8)) != 0)
+ value08 += value;
+
+ if ((mask & (MASK_ONE << 9)) != 0)
+ value09 += value;
+
+ if ((mask & (MASK_ONE << 10)) != 0)
+ value10 += value;
+
+ if ((mask & (MASK_ONE << 11)) != 0)
+ value11 += value;
+
+ if ((mask & (MASK_ONE << 12)) != 0)
+ value12 += value;
+
+ if ((mask & (MASK_ONE << 13)) != 0)
+ value13 += value;
+
+ if ((mask & (MASK_ONE << 14)) != 0)
+ value14 += value;
+
+ if ((mask & (MASK_ONE << 15)) != 0)
+ value15 += value;
+
+ if ((mask & (MASK_ONE << 16)) != 0)
+ value16 += value;
+
+ if ((mask & (MASK_ONE << 17)) != 0)
+ value17 += value;
+
+ if ((mask & (MASK_ONE << 18)) != 0)
+ value18 += value;
+
+ if ((mask & (MASK_ONE << 19)) != 0)
+ value19 += value;
+
+ if ((mask & (MASK_ONE << 20)) != 0)
+ value20 += value;
+
+ if ((mask & (MASK_ONE << 21)) != 0)
+ value21 += value;
+
+ if ((mask & (MASK_ONE << 22)) != 0)
+ value22 += value;
+
+ if ((mask & (MASK_ONE << 23)) != 0)
+ value23 += value;
+
+ if ((mask & (MASK_ONE << 24)) != 0)
+ value24 += value;
+
+ if ((mask & (MASK_ONE << 25)) != 0)
+ value25 += value;
+
+ if ((mask & (MASK_ONE << 26)) != 0)
+ value26 += value;
+
+ if ((mask & (MASK_ONE << 27)) != 0)
+ value27 += value;
+
+ if ((mask & (MASK_ONE << 28)) != 0)
+ value28 += value;
+
+ if ((mask & (MASK_ONE << 29)) != 0)
+ value29 += value;
+
+ if ((mask & (MASK_ONE << 30)) != 0)
+ value30 += value;
+
+ if ((mask & (MASK_ONE << 31)) != 0)
+ value31 += value;
+
+ if ((mask & (MASK_ONE << 32)) != 0)
+ value32 += value;
+
+ if ((mask & (MASK_ONE << 33)) != 0)
+ value33 += value;
+
+ if ((mask & (MASK_ONE << 34)) != 0)
+ value34 += value;
+
+ if ((mask & (MASK_ONE << 35)) != 0)
+ value35 += value;
+
+ if ((mask & (MASK_ONE << 36)) != 0)
+ value36 += value;
+
+ if ((mask & (MASK_ONE << 37)) != 0)
+ value37 += value;
+
+ if ((mask & (MASK_ONE << 38)) != 0)
+ value38 += value;
+
+ if ((mask & (MASK_ONE << 39)) != 0)
+ value39 += value;
+ }
+
+ while ((mask = *sub_mask++) != 0)
+ {
+ value = *sub_values++;
+
+ __asm__ (" #reg %0" : "+d" (value));
+
+ if ((mask & (MASK_ONE << 0)) != 0)
+ value00 -= value;
+
+ if ((mask & (MASK_ONE << 1)) != 0)
+ value01 -= value;
+
+ if ((mask & (MASK_ONE << 2)) != 0)
+ value02 -= value;
+
+ if ((mask & (MASK_ONE << 3)) != 0)
+ value03 -= value;
+
+ if ((mask & (MASK_ONE << 4)) != 0)
+ value04 -= value;
+
+ if ((mask & (MASK_ONE << 5)) != 0)
+ value05 -= value;
+
+ if ((mask & (MASK_ONE << 6)) != 0)
+ value06 -= value;
+
+ if ((mask & (MASK_ONE << 7)) != 0)
+ value07 -= value;
+
+ if ((mask & (MASK_ONE << 8)) != 0)
+ value08 -= value;
+
+ if ((mask & (MASK_ONE << 9)) != 0)
+ value09 -= value;
+
+ if ((mask & (MASK_ONE << 10)) != 0)
+ value10 -= value;
+
+ if ((mask & (MASK_ONE << 11)) != 0)
+ value11 -= value;
+
+ if ((mask & (MASK_ONE << 12)) != 0)
+ value12 -= value;
+
+ if ((mask & (MASK_ONE << 13)) != 0)
+ value13 -= value;
+
+ if ((mask & (MASK_ONE << 14)) != 0)
+ value14 -= value;
+
+ if ((mask & (MASK_ONE << 15)) != 0)
+ value15 -= value;
+
+ if ((mask & (MASK_ONE << 16)) != 0)
+ value16 -= value;
+
+ if ((mask & (MASK_ONE << 17)) != 0)
+ value17 -= value;
+
+ if ((mask & (MASK_ONE << 18)) != 0)
+ value18 -= value;
+
+ if ((mask & (MASK_ONE << 19)) != 0)
+ value19 -= value;
+
+ if ((mask & (MASK_ONE << 20)) != 0)
+ value20 -= value;
+
+ if ((mask & (MASK_ONE << 21)) != 0)
+ value21 -= value;
+
+ if ((mask & (MASK_ONE << 22)) != 0)
+ value22 -= value;
+
+ if ((mask & (MASK_ONE << 23)) != 0)
+ value23 -= value;
+
+ if ((mask & (MASK_ONE << 24)) != 0)
+ value24 -= value;
+
+ if ((mask & (MASK_ONE << 25)) != 0)
+ value25 -= value;
+
+ if ((mask & (MASK_ONE << 26)) != 0)
+ value26 -= value;
+
+ if ((mask & (MASK_ONE << 27)) != 0)
+ value27 -= value;
+
+ if ((mask & (MASK_ONE << 28)) != 0)
+ value28 -= value;
+
+ if ((mask & (MASK_ONE << 29)) != 0)
+ value29 -= value;
+
+ if ((mask & (MASK_ONE << 30)) != 0)
+ value30 -= value;
+
+ if ((mask & (MASK_ONE << 31)) != 0)
+ value31 -= value;
+
+ if ((mask & (MASK_ONE << 32)) != 0)
+ value32 -= value;
+
+ if ((mask & (MASK_ONE << 33)) != 0)
+ value33 -= value;
+
+ if ((mask & (MASK_ONE << 34)) != 0)
+ value34 -= value;
+
+ if ((mask & (MASK_ONE << 35)) != 0)
+ value35 -= value;
+
+ if ((mask & (MASK_ONE << 36)) != 0)
+ value36 -= value;
+
+ if ((mask & (MASK_ONE << 37)) != 0)
+ value37 -= value;
+
+ if ((mask & (MASK_ONE << 38)) != 0)
+ value38 -= value;
+
+ if ((mask & (MASK_ONE << 39)) != 0)
+ value39 -= value;
+ }
+
+ while ((mask = *mul_mask++) != 0)
+ {
+ value = *mul_values++;
+
+ __asm__ (" #reg %0" : "+d" (value));
+
+ if ((mask & (MASK_ONE << 0)) != 0)
+ value00 *= value;
+
+ if ((mask & (MASK_ONE << 1)) != 0)
+ value01 *= value;
+
+ if ((mask & (MASK_ONE << 2)) != 0)
+ value02 *= value;
+
+ if ((mask & (MASK_ONE << 3)) != 0)
+ value03 *= value;
+
+ if ((mask & (MASK_ONE << 4)) != 0)
+ value04 *= value;
+
+ if ((mask & (MASK_ONE << 5)) != 0)
+ value05 *= value;
+
+ if ((mask & (MASK_ONE << 6)) != 0)
+ value06 *= value;
+
+ if ((mask & (MASK_ONE << 7)) != 0)
+ value07 *= value;
+
+ if ((mask & (MASK_ONE << 8)) != 0)
+ value08 *= value;
+
+ if ((mask & (MASK_ONE << 9)) != 0)
+ value09 *= value;
+
+ if ((mask & (MASK_ONE << 10)) != 0)
+ value10 *= value;
+
+ if ((mask & (MASK_ONE << 11)) != 0)
+ value11 *= value;
+
+ if ((mask & (MASK_ONE << 12)) != 0)
+ value12 *= value;
+
+ if ((mask & (MASK_ONE << 13)) != 0)
+ value13 *= value;
+
+ if ((mask & (MASK_ONE << 14)) != 0)
+ value14 *= value;
+
+ if ((mask & (MASK_ONE << 15)) != 0)
+ value15 *= value;
+
+ if ((mask & (MASK_ONE << 16)) != 0)
+ value16 *= value;
+
+ if ((mask & (MASK_ONE << 17)) != 0)
+ value17 *= value;
+
+ if ((mask & (MASK_ONE << 18)) != 0)
+ value18 *= value;
+
+ if ((mask & (MASK_ONE << 19)) != 0)
+ value19 *= value;
+
+ if ((mask & (MASK_ONE << 20)) != 0)
+ value20 *= value;
+
+ if ((mask & (MASK_ONE << 21)) != 0)
+ value21 *= value;
+
+ if ((mask & (MASK_ONE << 22)) != 0)
+ value22 *= value;
+
+ if ((mask & (MASK_ONE << 23)) != 0)
+ value23 *= value;
+
+ if ((mask & (MASK_ONE << 24)) != 0)
+ value24 *= value;
+
+ if ((mask & (MASK_ONE << 25)) != 0)
+ value25 *= value;
+
+ if ((mask & (MASK_ONE << 26)) != 0)
+ value26 *= value;
+
+ if ((mask & (MASK_ONE << 27)) != 0)
+ value27 *= value;
+
+ if ((mask & (MASK_ONE << 28)) != 0)
+ value28 *= value;
+
+ if ((mask & (MASK_ONE << 29)) != 0)
+ value29 *= value;
+
+ if ((mask & (MASK_ONE << 30)) != 0)
+ value30 *= value;
+
+ if ((mask & (MASK_ONE << 31)) != 0)
+ value31 *= value;
+
+ if ((mask & (MASK_ONE << 32)) != 0)
+ value32 *= value;
+
+ if ((mask & (MASK_ONE << 33)) != 0)
+ value33 *= value;
+
+ if ((mask & (MASK_ONE << 34)) != 0)
+ value34 *= value;
+
+ if ((mask & (MASK_ONE << 35)) != 0)
+ value35 *= value;
+
+ if ((mask & (MASK_ONE << 36)) != 0)
+ value36 *= value;
+
+ if ((mask & (MASK_ONE << 37)) != 0)
+ value37 *= value;
+
+ if ((mask & (MASK_ONE << 38)) != 0)
+ value38 *= value;
+
+ if ((mask & (MASK_ONE << 39)) != 0)
+ value39 *= value;
+ }
+
+ while ((mask = *div_mask++) != 0)
+ {
+ value = *div_values++;
+
+ __asm__ (" #reg %0" : "+d" (value));
+
+ if ((mask & (MASK_ONE << 0)) != 0)
+ value00 /= value;
+
+ if ((mask & (MASK_ONE << 1)) != 0)
+ value01 /= value;
+
+ if ((mask & (MASK_ONE << 2)) != 0)
+ value02 /= value;
+
+ if ((mask & (MASK_ONE << 3)) != 0)
+ value03 /= value;
+
+ if ((mask & (MASK_ONE << 4)) != 0)
+ value04 /= value;
+
+ if ((mask & (MASK_ONE << 5)) != 0)
+ value05 /= value;
+
+ if ((mask & (MASK_ONE << 6)) != 0)
+ value06 /= value;
+
+ if ((mask & (MASK_ONE << 7)) != 0)
+ value07 /= value;
+
+ if ((mask & (MASK_ONE << 8)) != 0)
+ value08 /= value;
+
+ if ((mask & (MASK_ONE << 9)) != 0)
+ value09 /= value;
+
+ if ((mask & (MASK_ONE << 10)) != 0)
+ value10 /= value;
+
+ if ((mask & (MASK_ONE << 11)) != 0)
+ value11 /= value;
+
+ if ((mask & (MASK_ONE << 12)) != 0)
+ value12 /= value;
+
+ if ((mask & (MASK_ONE << 13)) != 0)
+ value13 /= value;
+
+ if ((mask & (MASK_ONE << 14)) != 0)
+ value14 /= value;
+
+ if ((mask & (MASK_ONE << 15)) != 0)
+ value15 /= value;
+
+ if ((mask & (MASK_ONE << 16)) != 0)
+ value16 /= value;
+
+ if ((mask & (MASK_ONE << 17)) != 0)
+ value17 /= value;
+
+ if ((mask & (MASK_ONE << 18)) != 0)
+ value18 /= value;
+
+ if ((mask & (MASK_ONE << 19)) != 0)
+ value19 /= value;
+
+ if ((mask & (MASK_ONE << 20)) != 0)
+ value20 /= value;
+
+ if ((mask & (MASK_ONE << 21)) != 0)
+ value21 /= value;
+
+ if ((mask & (MASK_ONE << 22)) != 0)
+ value22 /= value;
+
+ if ((mask & (MASK_ONE << 23)) != 0)
+ value23 /= value;
+
+ if ((mask & (MASK_ONE << 24)) != 0)
+ value24 /= value;
+
+ if ((mask & (MASK_ONE << 25)) != 0)
+ value25 /= value;
+
+ if ((mask & (MASK_ONE << 26)) != 0)
+ value26 /= value;
+
+ if ((mask & (MASK_ONE << 27)) != 0)
+ value27 /= value;
+
+ if ((mask & (MASK_ONE << 28)) != 0)
+ value28 /= value;
+
+ if ((mask & (MASK_ONE << 29)) != 0)
+ value29 /= value;
+
+ if ((mask & (MASK_ONE << 30)) != 0)
+ value30 /= value;
+
+ if ((mask & (MASK_ONE << 31)) != 0)
+ value31 /= value;
+
+ if ((mask & (MASK_ONE << 32)) != 0)
+ value32 /= value;
+
+ if ((mask & (MASK_ONE << 33)) != 0)
+ value33 /= value;
+
+ if ((mask & (MASK_ONE << 34)) != 0)
+ value34 /= value;
+
+ if ((mask & (MASK_ONE << 35)) != 0)
+ value35 /= value;
+
+ if ((mask & (MASK_ONE << 36)) != 0)
+ value36 /= value;
+
+ if ((mask & (MASK_ONE << 37)) != 0)
+ value37 /= value;
+
+ if ((mask & (MASK_ONE << 38)) != 0)
+ value38 /= value;
+
+ if ((mask & (MASK_ONE << 39)) != 0)
+ value39 /= value;
+ }
+
+ while ((mask = *eq0_mask++) != 0)
+ {
+ eq0 = 0;
+
+ if ((mask & (MASK_ONE << 0)) != 0)
+ eq0 |= (value00 == ZERO);
+
+ if ((mask & (MASK_ONE << 1)) != 0)
+ eq0 |= (value01 == ZERO);
+
+ if ((mask & (MASK_ONE << 2)) != 0)
+ eq0 |= (value02 == ZERO);
+
+ if ((mask & (MASK_ONE << 3)) != 0)
+ eq0 |= (value03 == ZERO);
+
+ if ((mask & (MASK_ONE << 4)) != 0)
+ eq0 |= (value04 == ZERO);
+
+ if ((mask & (MASK_ONE << 5)) != 0)
+ eq0 |= (value05 == ZERO);
+
+ if ((mask & (MASK_ONE << 6)) != 0)
+ eq0 |= (value06 == ZERO);
+
+ if ((mask & (MASK_ONE << 7)) != 0)
+ eq0 |= (value07 == ZERO);
+
+ if ((mask & (MASK_ONE << 8)) != 0)
+ eq0 |= (value08 == ZERO);
+
+ if ((mask & (MASK_ONE << 9)) != 0)
+ eq0 |= (value09 == ZERO);
+
+ if ((mask & (MASK_ONE << 10)) != 0)
+ eq0 |= (value10 == ZERO);
+
+ if ((mask & (MASK_ONE << 11)) != 0)
+ eq0 |= (value11 == ZERO);
+
+ if ((mask & (MASK_ONE << 12)) != 0)
+ eq0 |= (value12 == ZERO);
+
+ if ((mask & (MASK_ONE << 13)) != 0)
+ eq0 |= (value13 == ZERO);
+
+ if ((mask & (MASK_ONE << 14)) != 0)
+ eq0 |= (value14 == ZERO);
+
+ if ((mask & (MASK_ONE << 15)) != 0)
+ eq0 |= (value15 == ZERO);
+
+ if ((mask & (MASK_ONE << 16)) != 0)
+ eq0 |= (value16 == ZERO);
+
+ if ((mask & (MASK_ONE << 17)) != 0)
+ eq0 |= (value17 == ZERO);
+
+ if ((mask & (MASK_ONE << 18)) != 0)
+ eq0 |= (value18 == ZERO);
+
+ if ((mask & (MASK_ONE << 19)) != 0)
+ eq0 |= (value19 == ZERO);
+
+ if ((mask & (MASK_ONE << 20)) != 0)
+ eq0 |= (value20 == ZERO);
+
+ if ((mask & (MASK_ONE << 21)) != 0)
+ eq0 |= (value21 == ZERO);
+
+ if ((mask & (MASK_ONE << 22)) != 0)
+ eq0 |= (value22 == ZERO);
+
+ if ((mask & (MASK_ONE << 23)) != 0)
+ eq0 |= (value23 == ZERO);
+
+ if ((mask & (MASK_ONE << 24)) != 0)
+ eq0 |= (value24 == ZERO);
+
+ if ((mask & (MASK_ONE << 25)) != 0)
+ eq0 |= (value25 == ZERO);
+
+ if ((mask & (MASK_ONE << 26)) != 0)
+ eq0 |= (value26 == ZERO);
+
+ if ((mask & (MASK_ONE << 27)) != 0)
+ eq0 |= (value27 == ZERO);
+
+ if ((mask & (MASK_ONE << 28)) != 0)
+ eq0 |= (value28 == ZERO);
+
+ if ((mask & (MASK_ONE << 29)) != 0)
+ eq0 |= (value29 == ZERO);
+
+ if ((mask & (MASK_ONE << 30)) != 0)
+ eq0 |= (value30 == ZERO);
+
+ if ((mask & (MASK_ONE << 31)) != 0)
+ eq0 |= (value31 == ZERO);
+
+ if ((mask & (MASK_ONE << 32)) != 0)
+ eq0 |= (value32 == ZERO);
+
+ if ((mask & (MASK_ONE << 33)) != 0)
+ eq0 |= (value33 == ZERO);
+
+ if ((mask & (MASK_ONE << 34)) != 0)
+ eq0 |= (value34 == ZERO);
+
+ if ((mask & (MASK_ONE << 35)) != 0)
+ eq0 |= (value35 == ZERO);
+
+ if ((mask & (MASK_ONE << 36)) != 0)
+ eq0 |= (value36 == ZERO);
+
+ if ((mask & (MASK_ONE << 37)) != 0)
+ eq0 |= (value37 == ZERO);
+
+ if ((mask & (MASK_ONE << 38)) != 0)
+ eq0 |= (value38 == ZERO);
+
+ if ((mask & (MASK_ONE << 39)) != 0)
+ eq0 |= (value39 == ZERO);
+
+ *eq0_ptr++ = eq0;
+ }
+
+ return ( value00 + value01 + value02 + value03 + value04
+ + value05 + value06 + value07 + value08 + value09
+ + value10 + value11 + value12 + value13 + value14
+ + value15 + value16 + value17 + value18 + value19
+ + value20 + value21 + value22 + value23 + value24
+ + value25 + value26 + value27 + value28 + value29
+ + value30 + value31 + value32 + value33 + value34
+ + value35 + value36 + value37 + value38 + value39);
+}
+
+/* { dg-final { scan-assembler "fadd" } } */
+/* { dg-final { scan-assembler "fsub" } } */
+/* { dg-final { scan-assembler "fmul" } } */
+/* { dg-final { scan-assembler "fdiv" } } */
+/* { dg-final { scan-assembler "fcmpu" } } */
+/* { dg-final { scan-assembler "xsadddp" } } */
+/* { dg-final { scan-assembler "xssubdp" } } */
+/* { dg-final { scan-assembler "xsmuldp" } } */
+/* { dg-final { scan-assembler "xsdivdp" } } */
+/* { dg-final { scan-assembler "xscmpudp" } } */
Index: gcc/testsuite/gcc.target/powerpc/pr65849-2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr65849-2.c (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr65849-2.c (revision 0)
@@ -0,0 +1,728 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */
+
+/* Test whether we can enable the -mupper-regs-sf with target pragmas. Make
+ sure float values are allocated to the Altivec registers as well as the
+ traditional FPR registers. */
+
+#ifndef TYPE
+#define TYPE float
+#endif
+
+#ifndef MASK_TYPE
+#define MASK_TYPE unsigned long long
+#endif
+
+#define MASK_ONE ((MASK_TYPE)1)
+#define ZERO ((TYPE) 0.0)
+
+#pragma GCC target ("upper-regs-sf")
+TYPE
+test_add (const MASK_TYPE *add_mask, const TYPE *add_values,
+ const MASK_TYPE *sub_mask, const TYPE *sub_values,
+ const MASK_TYPE *mul_mask, const TYPE *mul_values,
+ const MASK_TYPE *div_mask, const TYPE *div_values,
+ const MASK_TYPE *eq0_mask, int *eq0_ptr)
+{
+ TYPE value;
+ TYPE value00 = ZERO;
+ TYPE value01 = ZERO;
+ TYPE value02 = ZERO;
+ TYPE value03 = ZERO;
+ TYPE value04 = ZERO;
+ TYPE value05 = ZERO;
+ TYPE value06 = ZERO;
+ TYPE value07 = ZERO;
+ TYPE value08 = ZERO;
+ TYPE value09 = ZERO;
+ TYPE value10 = ZERO;
+ TYPE value11 = ZERO;
+ TYPE value12 = ZERO;
+ TYPE value13 = ZERO;
+ TYPE value14 = ZERO;
+ TYPE value15 = ZERO;
+ TYPE value16 = ZERO;
+ TYPE value17 = ZERO;
+ TYPE value18 = ZERO;
+ TYPE value19 = ZERO;
+ TYPE value20 = ZERO;
+ TYPE value21 = ZERO;
+ TYPE value22 = ZERO;
+ TYPE value23 = ZERO;
+ TYPE value24 = ZERO;
+ TYPE value25 = ZERO;
+ TYPE value26 = ZERO;
+ TYPE value27 = ZERO;
+ TYPE value28 = ZERO;
+ TYPE value29 = ZERO;
+ TYPE value30 = ZERO;
+ TYPE value31 = ZERO;
+ TYPE value32 = ZERO;
+ TYPE value33 = ZERO;
+ TYPE value34 = ZERO;
+ TYPE value35 = ZERO;
+ TYPE value36 = ZERO;
+ TYPE value37 = ZERO;
+ TYPE value38 = ZERO;
+ TYPE value39 = ZERO;
+ MASK_TYPE mask;
+ int eq0;
+
+ while ((mask = *add_mask++) != 0)
+ {
+ value = *add_values++;
+
+ __asm__ (" #reg %0" : "+d" (value));
+
+ if ((mask & (MASK_ONE << 0)) != 0)
+ value00 += value;
+
+ if ((mask & (MASK_ONE << 1)) != 0)
+ value01 += value;
+
+ if ((mask & (MASK_ONE << 2)) != 0)
+ value02 += value;
+
+ if ((mask & (MASK_ONE << 3)) != 0)
+ value03 += value;
+
+ if ((mask & (MASK_ONE << 4)) != 0)
+ value04 += value;
+
+ if ((mask & (MASK_ONE << 5)) != 0)
+ value05 += value;
+
+ if ((mask & (MASK_ONE << 6)) != 0)
+ value06 += value;
+
+ if ((mask & (MASK_ONE << 7)) != 0)
+ value07 += value;
+
+ if ((mask & (MASK_ONE << 8)) != 0)
+ value08 += value;
+
+ if ((mask & (MASK_ONE << 9)) != 0)
+ value09 += value;
+
+ if ((mask & (MASK_ONE << 10)) != 0)
+ value10 += value;
+
+ if ((mask & (MASK_ONE << 11)) != 0)
+ value11 += value;
+
+ if ((mask & (MASK_ONE << 12)) != 0)
+ value12 += value;
+
+ if ((mask & (MASK_ONE << 13)) != 0)
+ value13 += value;
+
+ if ((mask & (MASK_ONE << 14)) != 0)
+ value14 += value;
+
+ if ((mask & (MASK_ONE << 15)) != 0)
+ value15 += value;
+
+ if ((mask & (MASK_ONE << 16)) != 0)
+ value16 += value;
+
+ if ((mask & (MASK_ONE << 17)) != 0)
+ value17 += value;
+
+ if ((mask & (MASK_ONE << 18)) != 0)
+ value18 += value;
+
+ if ((mask & (MASK_ONE << 19)) != 0)
+ value19 += value;
+
+ if ((mask & (MASK_ONE << 20)) != 0)
+ value20 += value;
+
+ if ((mask & (MASK_ONE << 21)) != 0)
+ value21 += value;
+
+ if ((mask & (MASK_ONE << 22)) != 0)
+ value22 += value;
+
+ if ((mask & (MASK_ONE << 23)) != 0)
+ value23 += value;
+
+ if ((mask & (MASK_ONE << 24)) != 0)
+ value24 += value;
+
+ if ((mask & (MASK_ONE << 25)) != 0)
+ value25 += value;
+
+ if ((mask & (MASK_ONE << 26)) != 0)
+ value26 += value;
+
+ if ((mask & (MASK_ONE << 27)) != 0)
+ value27 += value;
+
+ if ((mask & (MASK_ONE << 28)) != 0)
+ value28 += value;
+
+ if ((mask & (MASK_ONE << 29)) != 0)
+ value29 += value;
+
+ if ((mask & (MASK_ONE << 30)) != 0)
+ value30 += value;
+
+ if ((mask & (MASK_ONE << 31)) != 0)
+ value31 += value;
+
+ if ((mask & (MASK_ONE << 32)) != 0)
+ value32 += value;
+
+ if ((mask & (MASK_ONE << 33)) != 0)
+ value33 += value;
+
+ if ((mask & (MASK_ONE << 34)) != 0)
+ value34 += value;
+
+ if ((mask & (MASK_ONE << 35)) != 0)
+ value35 += value;
+
+ if ((mask & (MASK_ONE << 36)) != 0)
+ value36 += value;
+
+ if ((mask & (MASK_ONE << 37)) != 0)
+ value37 += value;
+
+ if ((mask & (MASK_ONE << 38)) != 0)
+ value38 += value;
+
+ if ((mask & (MASK_ONE << 39)) != 0)
+ value39 += value;
+ }
+
+ while ((mask = *sub_mask++) != 0)
+ {
+ value = *sub_values++;
+
+ __asm__ (" #reg %0" : "+d" (value));
+
+ if ((mask & (MASK_ONE << 0)) != 0)
+ value00 -= value;
+
+ if ((mask & (MASK_ONE << 1)) != 0)
+ value01 -= value;
+
+ if ((mask & (MASK_ONE << 2)) != 0)
+ value02 -= value;
+
+ if ((mask & (MASK_ONE << 3)) != 0)
+ value03 -= value;
+
+ if ((mask & (MASK_ONE << 4)) != 0)
+ value04 -= value;
+
+ if ((mask & (MASK_ONE << 5)) != 0)
+ value05 -= value;
+
+ if ((mask & (MASK_ONE << 6)) != 0)
+ value06 -= value;
+
+ if ((mask & (MASK_ONE << 7)) != 0)
+ value07 -= value;
+
+ if ((mask & (MASK_ONE << 8)) != 0)
+ value08 -= value;
+
+ if ((mask & (MASK_ONE << 9)) != 0)
+ value09 -= value;
+
+ if ((mask & (MASK_ONE << 10)) != 0)
+ value10 -= value;
+
+ if ((mask & (MASK_ONE << 11)) != 0)
+ value11 -= value;
+
+ if ((mask & (MASK_ONE << 12)) != 0)
+ value12 -= value;
+
+ if ((mask & (MASK_ONE << 13)) != 0)
+ value13 -= value;
+
+ if ((mask & (MASK_ONE << 14)) != 0)
+ value14 -= value;
+
+ if ((mask & (MASK_ONE << 15)) != 0)
+ value15 -= value;
+
+ if ((mask & (MASK_ONE << 16)) != 0)
+ value16 -= value;
+
+ if ((mask & (MASK_ONE << 17)) != 0)
+ value17 -= value;
+
+ if ((mask & (MASK_ONE << 18)) != 0)
+ value18 -= value;
+
+ if ((mask & (MASK_ONE << 19)) != 0)
+ value19 -= value;
+
+ if ((mask & (MASK_ONE << 20)) != 0)
+ value20 -= value;
+
+ if ((mask & (MASK_ONE << 21)) != 0)
+ value21 -= value;
+
+ if ((mask & (MASK_ONE << 22)) != 0)
+ value22 -= value;
+
+ if ((mask & (MASK_ONE << 23)) != 0)
+ value23 -= value;
+
+ if ((mask & (MASK_ONE << 24)) != 0)
+ value24 -= value;
+
+ if ((mask & (MASK_ONE << 25)) != 0)
+ value25 -= value;
+
+ if ((mask & (MASK_ONE << 26)) != 0)
+ value26 -= value;
+
+ if ((mask & (MASK_ONE << 27)) != 0)
+ value27 -= value;
+
+ if ((mask & (MASK_ONE << 28)) != 0)
+ value28 -= value;
+
+ if ((mask & (MASK_ONE << 29)) != 0)
+ value29 -= value;
+
+ if ((mask & (MASK_ONE << 30)) != 0)
+ value30 -= value;
+
+ if ((mask & (MASK_ONE << 31)) != 0)
+ value31 -= value;
+
+ if ((mask & (MASK_ONE << 32)) != 0)
+ value32 -= value;
+
+ if ((mask & (MASK_ONE << 33)) != 0)
+ value33 -= value;
+
+ if ((mask & (MASK_ONE << 34)) != 0)
+ value34 -= value;
+
+ if ((mask & (MASK_ONE << 35)) != 0)
+ value35 -= value;
+
+ if ((mask & (MASK_ONE << 36)) != 0)
+ value36 -= value;
+
+ if ((mask & (MASK_ONE << 37)) != 0)
+ value37 -= value;
+
+ if ((mask & (MASK_ONE << 38)) != 0)
+ value38 -= value;
+
+ if ((mask & (MASK_ONE << 39)) != 0)
+ value39 -= value;
+ }
+
+ while ((mask = *mul_mask++) != 0)
+ {
+ value = *mul_values++;
+
+ __asm__ (" #reg %0" : "+d" (value));
+
+ if ((mask & (MASK_ONE << 0)) != 0)
+ value00 *= value;
+
+ if ((mask & (MASK_ONE << 1)) != 0)
+ value01 *= value;
+
+ if ((mask & (MASK_ONE << 2)) != 0)
+ value02 *= value;
+
+ if ((mask & (MASK_ONE << 3)) != 0)
+ value03 *= value;
+
+ if ((mask & (MASK_ONE << 4)) != 0)
+ value04 *= value;
+
+ if ((mask & (MASK_ONE << 5)) != 0)
+ value05 *= value;
+
+ if ((mask & (MASK_ONE << 6)) != 0)
+ value06 *= value;
+
+ if ((mask & (MASK_ONE << 7)) != 0)
+ value07 *= value;
+
+ if ((mask & (MASK_ONE << 8)) != 0)
+ value08 *= value;
+
+ if ((mask & (MASK_ONE << 9)) != 0)
+ value09 *= value;
+
+ if ((mask & (MASK_ONE << 10)) != 0)
+ value10 *= value;
+
+ if ((mask & (MASK_ONE << 11)) != 0)
+ value11 *= value;
+
+ if ((mask & (MASK_ONE << 12)) != 0)
+ value12 *= value;
+
+ if ((mask & (MASK_ONE << 13)) != 0)
+ value13 *= value;
+
+ if ((mask & (MASK_ONE << 14)) != 0)
+ value14 *= value;
+
+ if ((mask & (MASK_ONE << 15)) != 0)
+ value15 *= value;
+
+ if ((mask & (MASK_ONE << 16)) != 0)
+ value16 *= value;
+
+ if ((mask & (MASK_ONE << 17)) != 0)
+ value17 *= value;
+
+ if ((mask & (MASK_ONE << 18)) != 0)
+ value18 *= value;
+
+ if ((mask & (MASK_ONE << 19)) != 0)
+ value19 *= value;
+
+ if ((mask & (MASK_ONE << 20)) != 0)
+ value20 *= value;
+
+ if ((mask & (MASK_ONE << 21)) != 0)
+ value21 *= value;
+
+ if ((mask & (MASK_ONE << 22)) != 0)
+ value22 *= value;
+
+ if ((mask & (MASK_ONE << 23)) != 0)
+ value23 *= value;
+
+ if ((mask & (MASK_ONE << 24)) != 0)
+ value24 *= value;
+
+ if ((mask & (MASK_ONE << 25)) != 0)
+ value25 *= value;
+
+ if ((mask & (MASK_ONE << 26)) != 0)
+ value26 *= value;
+
+ if ((mask & (MASK_ONE << 27)) != 0)
+ value27 *= value;
+
+ if ((mask & (MASK_ONE << 28)) != 0)
+ value28 *= value;
+
+ if ((mask & (MASK_ONE << 29)) != 0)
+ value29 *= value;
+
+ if ((mask & (MASK_ONE << 30)) != 0)
+ value30 *= value;
+
+ if ((mask & (MASK_ONE << 31)) != 0)
+ value31 *= value;
+
+ if ((mask & (MASK_ONE << 32)) != 0)
+ value32 *= value;
+
+ if ((mask & (MASK_ONE << 33)) != 0)
+ value33 *= value;
+
+ if ((mask & (MASK_ONE << 34)) != 0)
+ value34 *= value;
+
+ if ((mask & (MASK_ONE << 35)) != 0)
+ value35 *= value;
+
+ if ((mask & (MASK_ONE << 36)) != 0)
+ value36 *= value;
+
+ if ((mask & (MASK_ONE << 37)) != 0)
+ value37 *= value;
+
+ if ((mask & (MASK_ONE << 38)) != 0)
+ value38 *= value;
+
+ if ((mask & (MASK_ONE << 39)) != 0)
+ value39 *= value;
+ }
+
+ while ((mask = *div_mask++) != 0)
+ {
+ value = *div_values++;
+
+ __asm__ (" #reg %0" : "+d" (value));
+
+ if ((mask & (MASK_ONE << 0)) != 0)
+ value00 /= value;
+
+ if ((mask & (MASK_ONE << 1)) != 0)
+ value01 /= value;
+
+ if ((mask & (MASK_ONE << 2)) != 0)
+ value02 /= value;
+
+ if ((mask & (MASK_ONE << 3)) != 0)
+ value03 /= value;
+
+ if ((mask & (MASK_ONE << 4)) != 0)
+ value04 /= value;
+
+ if ((mask & (MASK_ONE << 5)) != 0)
+ value05 /= value;
+
+ if ((mask & (MASK_ONE << 6)) != 0)
+ value06 /= value;
+
+ if ((mask & (MASK_ONE << 7)) != 0)
+ value07 /= value;
+
+ if ((mask & (MASK_ONE << 8)) != 0)
+ value08 /= value;
+
+ if ((mask & (MASK_ONE << 9)) != 0)
+ value09 /= value;
+
+ if ((mask & (MASK_ONE << 10)) != 0)
+ value10 /= value;
+
+ if ((mask & (MASK_ONE << 11)) != 0)
+ value11 /= value;
+
+ if ((mask & (MASK_ONE << 12)) != 0)
+ value12 /= value;
+
+ if ((mask & (MASK_ONE << 13)) != 0)
+ value13 /= value;
+
+ if ((mask & (MASK_ONE << 14)) != 0)
+ value14 /= value;
+
+ if ((mask & (MASK_ONE << 15)) != 0)
+ value15 /= value;
+
+ if ((mask & (MASK_ONE << 16)) != 0)
+ value16 /= value;
+
+ if ((mask & (MASK_ONE << 17)) != 0)
+ value17 /= value;
+
+ if ((mask & (MASK_ONE << 18)) != 0)
+ value18 /= value;
+
+ if ((mask & (MASK_ONE << 19)) != 0)
+ value19 /= value;
+
+ if ((mask & (MASK_ONE << 20)) != 0)
+ value20 /= value;
+
+ if ((mask & (MASK_ONE << 21)) != 0)
+ value21 /= value;
+
+ if ((mask & (MASK_ONE << 22)) != 0)
+ value22 /= value;
+
+ if ((mask & (MASK_ONE << 23)) != 0)
+ value23 /= value;
+
+ if ((mask & (MASK_ONE << 24)) != 0)
+ value24 /= value;
+
+ if ((mask & (MASK_ONE << 25)) != 0)
+ value25 /= value;
+
+ if ((mask & (MASK_ONE << 26)) != 0)
+ value26 /= value;
+
+ if ((mask & (MASK_ONE << 27)) != 0)
+ value27 /= value;
+
+ if ((mask & (MASK_ONE << 28)) != 0)
+ value28 /= value;
+
+ if ((mask & (MASK_ONE << 29)) != 0)
+ value29 /= value;
+
+ if ((mask & (MASK_ONE << 30)) != 0)
+ value30 /= value;
+
+ if ((mask & (MASK_ONE << 31)) != 0)
+ value31 /= value;
+
+ if ((mask & (MASK_ONE << 32)) != 0)
+ value32 /= value;
+
+ if ((mask & (MASK_ONE << 33)) != 0)
+ value33 /= value;
+
+ if ((mask & (MASK_ONE << 34)) != 0)
+ value34 /= value;
+
+ if ((mask & (MASK_ONE << 35)) != 0)
+ value35 /= value;
+
+ if ((mask & (MASK_ONE << 36)) != 0)
+ value36 /= value;
+
+ if ((mask & (MASK_ONE << 37)) != 0)
+ value37 /= value;
+
+ if ((mask & (MASK_ONE << 38)) != 0)
+ value38 /= value;
+
+ if ((mask & (MASK_ONE << 39)) != 0)
+ value39 /= value;
+ }
+
+ while ((mask = *eq0_mask++) != 0)
+ {
+ eq0 = 0;
+
+ if ((mask & (MASK_ONE << 0)) != 0)
+ eq0 |= (value00 == ZERO);
+
+ if ((mask & (MASK_ONE << 1)) != 0)
+ eq0 |= (value01 == ZERO);
+
+ if ((mask & (MASK_ONE << 2)) != 0)
+ eq0 |= (value02 == ZERO);
+
+ if ((mask & (MASK_ONE << 3)) != 0)
+ eq0 |= (value03 == ZERO);
+
+ if ((mask & (MASK_ONE << 4)) != 0)
+ eq0 |= (value04 == ZERO);
+
+ if ((mask & (MASK_ONE << 5)) != 0)
+ eq0 |= (value05 == ZERO);
+
+ if ((mask & (MASK_ONE << 6)) != 0)
+ eq0 |= (value06 == ZERO);
+
+ if ((mask & (MASK_ONE << 7)) != 0)
+ eq0 |= (value07 == ZERO);
+
+ if ((mask & (MASK_ONE << 8)) != 0)
+ eq0 |= (value08 == ZERO);
+
+ if ((mask & (MASK_ONE << 9)) != 0)
+ eq0 |= (value09 == ZERO);
+
+ if ((mask & (MASK_ONE << 10)) != 0)
+ eq0 |= (value10 == ZERO);
+
+ if ((mask & (MASK_ONE << 11)) != 0)
+ eq0 |= (value11 == ZERO);
+
+ if ((mask & (MASK_ONE << 12)) != 0)
+ eq0 |= (value12 == ZERO);
+
+ if ((mask & (MASK_ONE << 13)) != 0)
+ eq0 |= (value13 == ZERO);
+
+ if ((mask & (MASK_ONE << 14)) != 0)
+ eq0 |= (value14 == ZERO);
+
+ if ((mask & (MASK_ONE << 15)) != 0)
+ eq0 |= (value15 == ZERO);
+
+ if ((mask & (MASK_ONE << 16)) != 0)
+ eq0 |= (value16 == ZERO);
+
+ if ((mask & (MASK_ONE << 17)) != 0)
+ eq0 |= (value17 == ZERO);
+
+ if ((mask & (MASK_ONE << 18)) != 0)
+ eq0 |= (value18 == ZERO);
+
+ if ((mask & (MASK_ONE << 19)) != 0)
+ eq0 |= (value19 == ZERO);
+
+ if ((mask & (MASK_ONE << 20)) != 0)
+ eq0 |= (value20 == ZERO);
+
+ if ((mask & (MASK_ONE << 21)) != 0)
+ eq0 |= (value21 == ZERO);
+
+ if ((mask & (MASK_ONE << 22)) != 0)
+ eq0 |= (value22 == ZERO);
+
+ if ((mask & (MASK_ONE << 23)) != 0)
+ eq0 |= (value23 == ZERO);
+
+ if ((mask & (MASK_ONE << 24)) != 0)
+ eq0 |= (value24 == ZERO);
+
+ if ((mask & (MASK_ONE << 25)) != 0)
+ eq0 |= (value25 == ZERO);
+
+ if ((mask & (MASK_ONE << 26)) != 0)
+ eq0 |= (value26 == ZERO);
+
+ if ((mask & (MASK_ONE << 27)) != 0)
+ eq0 |= (value27 == ZERO);
+
+ if ((mask & (MASK_ONE << 28)) != 0)
+ eq0 |= (value28 == ZERO);
+
+ if ((mask & (MASK_ONE << 29)) != 0)
+ eq0 |= (value29 == ZERO);
+
+ if ((mask & (MASK_ONE << 30)) != 0)
+ eq0 |= (value30 == ZERO);
+
+ if ((mask & (MASK_ONE << 31)) != 0)
+ eq0 |= (value31 == ZERO);
+
+ if ((mask & (MASK_ONE << 32)) != 0)
+ eq0 |= (value32 == ZERO);
+
+ if ((mask & (MASK_ONE << 33)) != 0)
+ eq0 |= (value33 == ZERO);
+
+ if ((mask & (MASK_ONE << 34)) != 0)
+ eq0 |= (value34 == ZERO);
+
+ if ((mask & (MASK_ONE << 35)) != 0)
+ eq0 |= (value35 == ZERO);
+
+ if ((mask & (MASK_ONE << 36)) != 0)
+ eq0 |= (value36 == ZERO);
+
+ if ((mask & (MASK_ONE << 37)) != 0)
+ eq0 |= (value37 == ZERO);
+
+ if ((mask & (MASK_ONE << 38)) != 0)
+ eq0 |= (value38 == ZERO);
+
+ if ((mask & (MASK_ONE << 39)) != 0)
+ eq0 |= (value39 == ZERO);
+
+ *eq0_ptr++ = eq0;
+ }
+
+ return ( value00 + value01 + value02 + value03 + value04
+ + value05 + value06 + value07 + value08 + value09
+ + value10 + value11 + value12 + value13 + value14
+ + value15 + value16 + value17 + value18 + value19
+ + value20 + value21 + value22 + value23 + value24
+ + value25 + value26 + value27 + value28 + value29
+ + value30 + value31 + value32 + value33 + value34
+ + value35 + value36 + value37 + value38 + value39);
+}
+
+/* { dg-final { scan-assembler "fadds" } } */
+/* { dg-final { scan-assembler "fsubs" } } */
+/* { dg-final { scan-assembler "fmuls" } } */
+/* { dg-final { scan-assembler "fdivs" } } */
+/* { dg-final { scan-assembler "fcmpu" } } */
+/* { dg-final { scan-assembler "xsaddsp" } } */
+/* { dg-final { scan-assembler "xssubsp" } } */
+/* { dg-final { scan-assembler "xsmulsp" } } */
+/* { dg-final { scan-assembler "xsdivsp" } } */
+/* { dg-final { scan-assembler "xscmpudp" } } */
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] PR target/65849 -- Add additional options to powerpc #pragma/attribute target support
2015-04-23 19:25 [PATCH] PR target/65849 -- Add additional options to powerpc #pragma/attribute target support Michael Meissner
@ 2015-04-24 13:51 ` David Edelsohn
0 siblings, 0 replies; 2+ messages in thread
From: David Edelsohn @ 2015-04-24 13:51 UTC (permalink / raw)
To: Michael Meissner, GCC Patches, Steve Munroe
On Thu, Apr 23, 2015 at 3:25 PM, Michael Meissner
<meissner@linux.vnet.ibm.com> wrote:
> Steve Munroe was tuning an application on PowerPC, and needed to set the
> -msave-toc-indirect option for only one function, and it wasn't available via
> the #praga/attribute target options. This patch adds support for the
> additional options that don't involve an ABI change to the list of options that
> can be set via the #pragma GCC target or attribute((target(...))) support.
>
> I have bootstrapped the compiler on a power7 (big endian) and power8 (little
> endian) with no regressions. Is this patch ok to install? I would like to
> backport this patch to the current branches (5.x, 4.9, 4.8, maybe 4.7). Is
> this ok?
>
> [gcc]
> 2015-04-23 Michael Meissner <meissner@linux.vnet.ibm.com>
>
> PR target/65849
> * config/rs6000/rs6000.opt (-mvsx-align-128): Make options that
> save to independent variables use the Save attribute. This will
> allow these options to be modified with the #pragma/attribute
> target support.
> (-mallow-movmisalign): Likewise.
> (-mallow-df-permute): Likewise.
> (-msched-groups): Likewise.
> (-malways-hint): Likewise.
> (-malign-branch-targets): Likewise.
> (-mvectorize-builtins): Likewise.
> (-msave-toc-indirect): Likewise.
>
> * config/rs6000/rs6000.c (rs6000_opt_masks): Add more options that
> can be set via the #pragma/attribute target support.
> (rs6000_opt_vars): Likewise.
> (rs6000_inner_target_options): If VSX was set, also set
> -mno-avoid-indexed-addresses.
>
> [gcc/testsuite]
> 2015-04-23 Michael Meissner <meissner@linux.vnet.ibm.com>
>
> PR target/65849
> * gcc.target/powerpc/pr65849-1.c: New test to verify being able to
> set new options.
> * gcc.target/powerpc/pr65849-2.c: Likewise.
Okay.
Thanks, David
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2015-04-24 13:51 UTC | newest]
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2015-04-23 19:25 [PATCH] PR target/65849 -- Add additional options to powerpc #pragma/attribute target support Michael Meissner
2015-04-24 13:51 ` David Edelsohn
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