From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 101182 invoked by alias); 19 May 2015 11:19:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 101171 invoked by uid 89); 19 May 2015 11:18:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: cam-smtp0.cambridge.arm.com Received: from fw-tnat.cambridge.arm.com (HELO cam-smtp0.cambridge.arm.com) (217.140.96.140) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Tue, 19 May 2015 11:18:58 +0000 Received: from arm.com (e106375-lin.cambridge.arm.com [10.2.207.23]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id t4JBIsWj024411; Tue, 19 May 2015 12:18:54 +0100 Date: Tue, 19 May 2015 11:21:00 -0000 From: James Greenhalgh To: Kyrylo Tkachov Cc: "gcc-patches@gcc.gnu.org" , Marcus Shawcroft , Richard Earnshaw Subject: Re: [PATCH][AArch64] PR target/65491: Classify V1TF vectors as AAPCS64 short vectors rather than composite types Message-ID: <20150519111854.GA31361@arm.com> References: <000001d07b53$012f1830$038d4890$@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <000001d07b53$012f1830$038d4890$@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes X-SW-Source: 2015-05/txt/msg01684.txt.bz2 On Mon, Apr 20, 2015 at 11:16:02AM +0100, Kyrylo Tkachov wrote: > Hi all, > > The ICE in the PR happens when we pass a 1x(128-bit float) vector as an > argument. > The aarch64 backend erroneously classifies it as a composite type when in > fact it > is a short vector according to AAPCS64 > (section 4.1.2 from > http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.p > df). Agreed. > > The solution in this patch is to check aarch64_composite_type_p for a short > vector with > aarch64_short_vector_p rather than the other way around (check for > aarch64_short_vector_p > in aarch64_composite_type_p). I think I understand what you are saying, but your patch does the opposite (ADDS a check for aarch64_short_vector_p in aarch64_composite_type_p, REMOVES a check for aarch64_composite_type_p, in aarch64_short_vector_p)... This logic is pretty hairy, and I'm struggling to convince myself that your change only hits the bug you described above. I think I've worked it through and it does, but if you can find any additional ABI tests which stress the Vector/Floating-Point passing rules that would help settle my nerves. The patch is OK. I wouldn't think we would want to backport it to release branches as there is no regression to fix. Thanks, James > 2015-04-20 Kyrylo Tkachov > > PR target/65491 > * config/aarch64/aarch64.c (aarch64_short_vector_p): Move above > aarch64_composite_type_p. Remove check for aarch64_composite_type_p. > (aarch64_composite_type_p): Return false if given type and mode are > for a short vector. > > 2015-04-20 Kyrylo Tkachov > > PR target/65491 > * gcc.target/aarch64/pr65491_1.c: New test. > * gcc.target/aarch64/aapcs64/type-def.h (vlf1_t): New typedef. > * gcc.target/aarch64/aapcs64/func-ret-1.c: Add test for vlf1_t.