From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 50422 invoked by alias); 20 May 2015 14:10:06 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 49924 invoked by uid 89); 20 May 2015 14:10:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.3 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RDNS_DYNAMIC,TVD_RCVD_IP autolearn=no version=3.3.2 X-HELO: brightrain.aerifal.cx Received: from 216-12-86-13.cv.mvl.ntelos.net (HELO brightrain.aerifal.cx) (216.12.86.13) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 20 May 2015 14:10:05 +0000 Received: from dalias by brightrain.aerifal.cx with local (Exim 3.15 #2) id 1Yv4gs-00013K-00; Wed, 20 May 2015 14:09:46 +0000 Date: Wed, 20 May 2015 14:17:00 -0000 From: Rich Felker To: Michael Matz Cc: Richard Henderson , "H.J. Lu" , Jan Hubicka , Alexander Monakov , GCC Patches , Uros Bizjak Subject: Re: [PATCH i386] Allow sibcalls in no-PLT PIC Message-ID: <20150520140946.GU17573@brightrain.aerifal.cx> References: <20150515204237.GF17573@brightrain.aerifal.cx> <20150515230810.GA73210@kam.mff.cuni.cz> <20150515234403.GG17573@brightrain.aerifal.cx> <20150519180659.GG17573@brightrain.aerifal.cx> <555B87F4.30908@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-SW-Source: 2015-05/txt/msg01839.txt.bz2 On Wed, May 20, 2015 at 02:10:41PM +0200, Michael Matz wrote: > Hi, > > On Tue, 19 May 2015, Richard Henderson wrote: > > > It is. The relaxation that HJ is working on requires that the reads > > from the got not be hoisted. I'm not especially convinced that what > > he's working on is a win. > > > > With LTO, the compiler can do the same job that he's attempting in the > > linker, without an extra nop. Without LTO, leaving it to the linker > > means that you can't hoist the load and hide the memory latency. > > Well, hoisting always needs a register, and if hoisted out of a loop > (which you all seem to be after) that register is live through the whole > loop body. You need a register for each different called function in such > loop, trading the one GOT pointer with N other registers. For > register-starved machines this is a real problem, even x86-64 doesn't have > that many. I.e. I'm not convinced that this hoisting will really be much > of a win that often, outside toy examples. Sure, the compiler can hoist > function addresses trivially, but I think it will lead to spilling more > often than not, or alternatively the hoisting will be undone by the > register allocators rematerialization. Of course, this would have to be > measured for real not hand-waved, but, well, I'd be surprised if it's not > so. The obvious example where it's useful on x86_64 is a major class: anything where the majority of the callee's data is floating point and thus kept in xmm registers. In that case register pressure is a lot lower, and there's also an obvious class of cross-DSO functions calls you'd be making over and over again: anything from libm. Rich