[PATCH 1/2] Add mask to specify which LEON3 targets support CASA

[PATCH 1/2] Add mask to specify which LEON3 targets support CASA

[Daniel Cederman]

Not all LEON3 support the CASA instruction. This patch provides a mask
that can be used to specify which LEON3 targets that support CASA.

gcc/ChangeLog:

2015-06-22  Daniel Cederman  <cederman@gaisler.com>

	* config/sparc/sparc.c (sparc_option_override): Mark CPU targets
	  leon3 and leon3v7 as supporting the CASA instruction
	* config/sparc/sparc.opt: Add mask specifying that the LEON3
          supports the CASA instruction (MASK_LEON3_CASA)
	* config/sparc/sync.md: Only generate CASA for V9 and targets
	  with the MASK_LEON3_CASA mask
---
 gcc/config/sparc/sparc.c   | 4 ++--
 gcc/config/sparc/sparc.opt | 3 +++
 gcc/config/sparc/sync.md   | 6 +++---
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 995a769..205e3cb 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -1280,8 +1280,8 @@ sparc_option_override (void)
     { "supersparc",	MASK_ISA, MASK_V8 },
     { "hypersparc",	MASK_ISA, MASK_V8|MASK_FPU },
     { "leon",		MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU },
-    { "leon3",		MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU },
-    { "leon3v7",	MASK_ISA, MASK_LEON3|MASK_FPU },
+    { "leon3",		MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU|MASK_LEON_CASA },
+    { "leon3v7",	MASK_ISA, MASK_LEON3|MASK_FPU|MASK_LEON_CASA },
     { "sparclite",	MASK_ISA, MASK_SPARCLITE },
     /* The Fujitsu MB86930 is the original sparclite chip, with no FPU.  */
     { "f930",		MASK_ISA|MASK_FPU, MASK_SPARCLITE },
diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index 5c7f546..e6caa95 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -228,6 +228,9 @@ Mask(LEON)
 Mask(LEON3)
 ;; Generate code for LEON3
 
+Mask(LEON_CASA)
+;; Generate CAS instruction for LEON
+
 Mask(SPARCLITE)
 ;; Generate code for SPARClite
 
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md
index 2fabff5..8e1baee 100644
--- a/gcc/config/sparc/sync.md
+++ b/gcc/config/sparc/sync.md
@@ -181,7 +181,7 @@
    (match_operand:SI 5 "const_int_operand" "")		;; is_weak
    (match_operand:SI 6 "const_int_operand" "")		;; mod_s
    (match_operand:SI 7 "const_int_operand" "")]		;; mod_f
-  "(TARGET_V9 || TARGET_LEON3)
+  "(TARGET_V9 || TARGET_LEON_CASA)
    && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"
 {
   sparc_expand_compare_and_swap (operands);
@@ -197,7 +197,7 @@
 	     [(match_operand:I48MODE 2 "register_operand" "")
 	      (match_operand:I48MODE 3 "register_operand" "")]
 	     UNSPECV_CAS))])]
-  "TARGET_V9 || TARGET_LEON3"
+  "TARGET_V9 || TARGET_LEON_CASA"
   "")
 
 (define_insn "*atomic_compare_and_swap<mode>_1"
@@ -220,7 +220,7 @@
 	  [(match_operand:SI 2 "register_operand" "r")
 	   (match_operand:SI 3 "register_operand" "0")]
 	  UNSPECV_CAS))]
-  "TARGET_LEON3"
+  "TARGET_LEON_CASA"
 {
   if (TARGET_SV_MODE)
     return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space.  */
-- 
2.4.3

[PATCH 2/2] Add leon3r0 and leon3r0v7 CPU targets

[Daniel Cederman]

Early variants of LEON3, revision 0, do not support the CASA instruction.
This patch adds two new targets, leon3r0 and leon3r0v7, that are equivalent
to leon3 and leon3v7, except that they do not support CASA.

gcc/ChangeLog:

2015-06-22  Daniel Cederman  <cederman@gaisler.com>

	* config.gcc: Add leon3r0[v7] targets
	* config/sparc/leon.md: Add leon3r0[v7] to FPU timing
	* config/sparc/sparc-opts.h (enum processor_type): Add leon3r0[v7] targets
	* config/sparc/sparc.c (sparc_option_override): Add leon3r0[v7] as targets
	  without CASA support
	* config/sparc/sparc.h: Add leon3r0[v7] targets
	* config/sparc/sparc.md: Add leon3r0[v7] targets
	* config/sparc/sparc.opt: Add leon3r0[v7] targets
	* doc/invoke.texi: Add leon3r0[v7] targets
---
 gcc/config.gcc                |  6 ++----
 gcc/config/sparc/leon.md      | 14 +++++++-------
 gcc/config/sparc/sparc-opts.h |  2 ++
 gcc/config/sparc/sparc.c      |  4 ++++
 gcc/config/sparc/sparc.h      | 44 ++++++++++++++++++++++++-------------------
 gcc/config/sparc/sparc.md     |  2 ++
 gcc/config/sparc/sparc.opt    |  6 ++++++
 gcc/doc/invoke.texi           | 22 +++++++++++-----------
 8 files changed, 59 insertions(+), 41 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 805638d..b10a1c9 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -3322,10 +3322,7 @@ if test x$with_cpu = x ; then
 	  with_cpu=leon
 	  ;;
 	*-leon[3-9]*)
-	  with_cpu=leon3
-	  ;;
-	*-leon[3-9]v7*)
-	  with_cpu=leon3v7
+	  with_cpu="`echo ${target} | sed 's/.*-\(leon[a-z0-9]*\).*$/\1/'`"
 	  ;;
 	*)
 	  with_cpu="`echo ${target} | sed 's/-.*$//'`"
@@ -4198,6 +4195,7 @@ case "${target}" in
 			"" | sparc | sparcv9 | sparc64 \
 			| v7 | cypress \
 			| v8 | supersparc | hypersparc | leon | leon3 | leon3v7 \
+			| leon3r0 | leon3r0v7 \
 			| sparclite | f930 | f934 | sparclite86x \
 			| sparclet | tsc701 \
 			| v9 | ultrasparc | ultrasparc3 | niagara | niagara2 \
diff --git a/gcc/config/sparc/leon.md b/gcc/config/sparc/leon.md
index aca92fc..3441a74 100644
--- a/gcc/config/sparc/leon.md
+++ b/gcc/config/sparc/leon.md
@@ -29,11 +29,11 @@
 
 ;; Use a double reservation to work around the load pipeline hazard on UT699.
 (define_insn_reservation "leon3_load" 1
-  (and (eq_attr "cpu" "leon3,leon3v7") (eq_attr "type" "load,sload"))
+  (and (eq_attr "cpu" "leon3,leon3v7,leon3r0,leon3r0v7") (eq_attr "type" "load,sload"))
   "leon_memory*2")
 
 (define_insn_reservation "leon_store" 2
-  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "store"))
+  (and (eq_attr "cpu" "leon,leon3,leon3v7,leon3r0,leon3r0v7") (eq_attr "type" "store"))
   "leon_memory*2")
 
 ;; This describes Gaisler Research's FPU
@@ -44,21 +44,21 @@
 (define_cpu_unit "grfpu_ds" "grfpu")
 
 (define_insn_reservation "leon_fp_alu" 4
-  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fp,fpcmp,fpmul"))
+  (and (eq_attr "cpu" "leon,leon3,leon3v7,leon3r0,leon3r0v7") (eq_attr "type" "fp,fpcmp,fpmul"))
   "grfpu_alu, nothing*3")
 
 (define_insn_reservation "leon_fp_divs" 16
-  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpdivs"))
+  (and (eq_attr "cpu" "leon,leon3,leon3v7,leon3r0,leon3r0v7") (eq_attr "type" "fpdivs"))
   "grfpu_ds*14, nothing*2")
 
 (define_insn_reservation "leon_fp_divd" 17
-  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpdivd"))
+  (and (eq_attr "cpu" "leon,leon3,leon3v7,leon3r0,leon3r0v7") (eq_attr "type" "fpdivd"))
   "grfpu_ds*15, nothing*2")
 
 (define_insn_reservation "leon_fp_sqrts" 24
-  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpsqrts"))
+  (and (eq_attr "cpu" "leon,leon3,leon3v7,leon3r0,leon3r0v7") (eq_attr "type" "fpsqrts"))
   "grfpu_ds*22, nothing*2")
 
 (define_insn_reservation "leon_fp_sqrtd" 25
-  (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpsqrtd"))
+  (and (eq_attr "cpu" "leon,leon3,leon3v7,leon3r0,leon3r0v7") (eq_attr "type" "fpsqrtd"))
   "grfpu_ds*23, nothing*2")
diff --git a/gcc/config/sparc/sparc-opts.h b/gcc/config/sparc/sparc-opts.h
index 7679d0d..24a2b64 100644
--- a/gcc/config/sparc/sparc-opts.h
+++ b/gcc/config/sparc/sparc-opts.h
@@ -30,6 +30,8 @@ enum processor_type {
   PROCESSOR_SUPERSPARC,
   PROCESSOR_HYPERSPARC,
   PROCESSOR_LEON,
+  PROCESSOR_LEON3R0,
+  PROCESSOR_LEON3R0V7,
   PROCESSOR_LEON3,
   PROCESSOR_LEON3V7,
   PROCESSOR_SPARCLITE,
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 205e3cb..862e88d 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -1280,6 +1280,8 @@ sparc_option_override (void)
     { "supersparc",	MASK_ISA, MASK_V8 },
     { "hypersparc",	MASK_ISA, MASK_V8|MASK_FPU },
     { "leon",		MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU },
+    { "leon3r0",	MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU },
+    { "leon3r0v7",	MASK_ISA, MASK_LEON3|MASK_FPU },
     { "leon3",		MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU|MASK_LEON_CASA },
     { "leon3v7",	MASK_ISA, MASK_LEON3|MASK_FPU|MASK_LEON_CASA },
     { "sparclite",	MASK_ISA, MASK_SPARCLITE },
@@ -1533,6 +1535,8 @@ sparc_option_override (void)
     case PROCESSOR_LEON:
       sparc_costs = &leon_costs;
       break;
+    case PROCESSOR_LEON3R0:
+    case PROCESSOR_LEON3R0V7:
     case PROCESSOR_LEON3:
     case PROCESSOR_LEON3V7:
       sparc_costs = &leon3_costs;
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 72dd18b..2e4c03a 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -125,23 +125,25 @@ extern enum cmodel sparc_cmodel;
 #define TARGET_CPU_supersparc	2
 #define TARGET_CPU_hypersparc	3
 #define TARGET_CPU_leon		4
-#define TARGET_CPU_leon3	5
-#define TARGET_CPU_leon3v7	6
-#define TARGET_CPU_sparclite	7
-#define TARGET_CPU_f930		7       /* alias */
-#define TARGET_CPU_f934		7       /* alias */
-#define TARGET_CPU_sparclite86x	8
-#define TARGET_CPU_sparclet	9
-#define TARGET_CPU_tsc701	9       /* alias */
-#define TARGET_CPU_v9		10	/* generic v9 implementation */
-#define TARGET_CPU_sparcv9	10	/* alias */
-#define TARGET_CPU_sparc64	10	/* alias */
-#define TARGET_CPU_ultrasparc	11
-#define TARGET_CPU_ultrasparc3	12
-#define TARGET_CPU_niagara	13
-#define TARGET_CPU_niagara2	14
-#define TARGET_CPU_niagara3	15
-#define TARGET_CPU_niagara4	16
+#define TARGET_CPU_leon3r0	5
+#define TARGET_CPU_leon3r0v7	6
+#define TARGET_CPU_leon3	7
+#define TARGET_CPU_leon3v7	8
+#define TARGET_CPU_sparclite	9
+#define TARGET_CPU_f930		9       /* alias */
+#define TARGET_CPU_f934		9       /* alias */
+#define TARGET_CPU_sparclite86x	10
+#define TARGET_CPU_sparclet	11
+#define TARGET_CPU_tsc701	11      /* alias */
+#define TARGET_CPU_v9		12	/* generic v9 implementation */
+#define TARGET_CPU_sparcv9	12	/* alias */
+#define TARGET_CPU_sparc64	12	/* alias */
+#define TARGET_CPU_ultrasparc	13
+#define TARGET_CPU_ultrasparc3	14
+#define TARGET_CPU_niagara	15
+#define TARGET_CPU_niagara2	16
+#define TARGET_CPU_niagara3	17
+#define TARGET_CPU_niagara4	18
 
 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
  || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
@@ -224,12 +226,14 @@ extern enum cmodel sparc_cmodel;
 #endif
 
 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon \
- || TARGET_CPU_DEFAULT == TARGET_CPU_leon3
+ || TARGET_CPU_DEFAULT == TARGET_CPU_leon3 \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_leon3r0
 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__"
 #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG
 #endif
 
-#if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7
+#if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7 \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_leon3r0v7
 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__"
 #define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG
 #endif
@@ -279,6 +283,8 @@ extern enum cmodel sparc_cmodel;
 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
 %{mcpu=leon:-D__leon__ -D__sparc_v8__} \
+%{mcpu=leon3r0:-D__leon__ -D__sparc_v8__} \
+%{mcpu=leon3r0v7:-D__leon__} \
 %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \
 %{mcpu=leon3v7:-D__leon__} \
 %{mcpu=v9:-D__sparc_v9__} \
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index a561877..672248e 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -220,6 +220,8 @@
    supersparc,
    hypersparc,
    leon,
+   leon3r0,
+   leon3r0v7,
    leon3,
    leon3v7,
    sparclite,
diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index e6caa95..6cd1e09 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -154,6 +154,12 @@ EnumValue
 Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON)
 
 EnumValue
+Enum(sparc_processor_type) String(leon3r0) Value(PROCESSOR_LEON3R0)
+
+EnumValue
+Enum(sparc_processor_type) String(leon3r0v7) Value(PROCESSOR_LEON3R0V7)
+
+EnumValue
 Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3)
 
 EnumValue
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 211e8e9..2110bf8 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21329,10 +21329,10 @@ the rules of the ABI@.
 Set the instruction set, register set, and instruction scheduling parameters
 for machine type @var{cpu_type}.  Supported values for @var{cpu_type} are
 @samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{hypersparc},
-@samp{leon}, @samp{leon3}, @samp{leon3v7}, @samp{sparclite}, @samp{f930},
-@samp{f934}, @samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9},
-@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2},
-@samp{niagara3} and @samp{niagara4}.
+@samp{leon}, @samp{leon3r0}, @samp{leon3r0v7}, @samp{leon3}, @samp{leon3v7},
+@samp{sparclite}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, @samp{sparclet},
+@samp{tsc701}, @samp{v9}, @samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara},
+@samp{niagara2}, @samp{niagara3} and @samp{niagara4}.
 
 Native Solaris and GNU/Linux toolchains also support the value @samp{native},
 which selects the best architecture option for the host processor.
@@ -21348,10 +21348,10 @@ implementations.
 
 @table @asis
 @item v7
-cypress, leon3v7
+cypress, leon3r0v7, leon3v7
 
 @item v8
-supersparc, hypersparc, leon, leon3
+supersparc, hypersparc, leon, leon3r0, leon3
 
 @item sparclite
 f930, f934, sparclite86x
@@ -21413,11 +21413,11 @@ option @option{-mcpu=@var{cpu_type}} does.
 The same values for @option{-mcpu=@var{cpu_type}} can be used for
 @option{-mtune=@var{cpu_type}}, but the only useful values are those
 that select a particular CPU implementation.  Those are @samp{cypress},
-@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3},
-@samp{leon3v7}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, @samp{tsc701},
-@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2},
-@samp{niagara3} and @samp{niagara4}.  With native Solaris and GNU/Linux
-toolchains, @samp{native} can also be used.
+@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3r0},
+@samp{leon3r0v7}, @samp{leon3}, @samp{leon3v7}, @samp{f930}, @samp{f934},
+@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, @samp{ultrasparc3},
+@samp{niagara}, @samp{niagara2}, @samp{niagara3} and @samp{niagara4}.
+With native Solaris and GNU/Linux toolchains, @samp{native} can also be used.
 
 @item -mv8plus
 @itemx -mno-v8plus
-- 
2.4.3

[PATCH] Use leon3 target for native LEON on Linux

[Daniel Cederman]

Linux requires LEON version 3 or above with CASA support.

gcc/ChangeLog:

2015-06-23  Daniel Cederman  <cederman@gaisler.com>

	* config/sparc/driver-sparc.c: map /proc/cpuinfo with CPU LEON
	  to leon3
---
 gcc/config/sparc/driver-sparc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/config/sparc/driver-sparc.c b/gcc/config/sparc/driver-sparc.c
index 778de2c..5969735 100644
--- a/gcc/config/sparc/driver-sparc.c
+++ b/gcc/config/sparc/driver-sparc.c
@@ -73,6 +73,7 @@ static const struct cpu_names {
   { "UltraSparc T2",	"niagara2" },
   { "UltraSparc T3",	"niagara3" },
   { "UltraSparc T4",	"niagara4" },
+  { "LEON",		"leon3" },
 #endif
   { NULL,	NULL }
   };
-- 
2.4.3

[PATCH] Make muser-mode the default for LEON3

[Daniel Cederman]

The muser-mode flag causes the CASA instruction for LEON3 to use the
user mode ASI. This is the correct behavior for almost all LEON3 targets.
For this reason it makes sense to make user mode the default. This patch
adds a flag for supervisor mode that can be used on the very few LEON3 targets
that requires CASA to use the supervisor ASI.

gcc/ChangeLog:

2015-06-22  Daniel Cederman  <cederman@gaisler.com>

	* config/sparc/sparc.opt: Add supervisor mode flag (-msv-mode) and
	  make user mode the default
	* config/sparc/sync.md: Only use supervisor ASI for CASA when in
	  supervisor mode
	* doc/invoke.texi: Document msv-mode flag
---
 gcc/config/sparc/sparc.opt |  8 ++++++--
 gcc/config/sparc/sync.md   |  6 +++---
 gcc/doc/invoke.texi        | 13 ++++++++-----
 3 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index 93d24a6..5c7f546 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -113,9 +113,13 @@ mrelax
 Target
 Optimize tail call instructions in assembler and linker
 
+msv-mode
+Target RejectNegative Report Mask(SV_MODE)
+Generate code that can only run in supervisor mode
+
 muser-mode
-Target Report Mask(USER_MODE)
-Do not generate code that can only run in supervisor mode
+Target RejectNegative Report InverseMask(SV_MODE)
+Do not generate code that can only run in supervisor mode (default)
 
 mcpu=
 Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7)
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md
index 7d00b10..2fabff5 100644
--- a/gcc/config/sparc/sync.md
+++ b/gcc/config/sparc/sync.md
@@ -222,10 +222,10 @@
 	  UNSPECV_CAS))]
   "TARGET_LEON3"
 {
-  if (TARGET_USER_MODE)
-    return "casa\t%1 0xa, %2, %0"; /* ASI for user data space.  */
-  else
+  if (TARGET_SV_MODE)
     return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space.  */
+  else
+    return "casa\t%1 0xa, %2, %0"; /* ASI for user data space.  */
 }
   [(set_attr "type" "multi")])
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b99ab1c..211e8e9 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1008,7 +1008,7 @@ See RS/6000 and PowerPC Options.
 -mhard-quad-float  -msoft-quad-float @gol
 -mstack-bias  -mno-stack-bias @gol
 -munaligned-doubles  -mno-unaligned-doubles @gol
--muser-mode  -mno-user-mode @gol
+-muser-mode  -msv-mode @gol
 -mv8plus  -mno-v8plus  -mvis  -mno-vis @gol
 -mvis2  -mno-vis2  -mvis3  -mno-vis3 @gol
 -mcbcond -mno-cbcond @gol
@@ -21300,13 +21300,16 @@ Specifying this option avoids some rare compatibility problems with code
 generated by other compilers.  It is not the default because it results
 in a performance loss, especially for floating-point code.
 
+@item -msv-mode
+@opindex msv-mode
+Generate code that can only run in supervisor mode.  This is relevant
+only for the @code{casa} instruction emitted for the LEON3 processor.
+
 @item -muser-mode
-@itemx -mno-user-mode
 @opindex muser-mode
-@opindex mno-user-mode
 Do not generate code that can only run in supervisor mode.  This is relevant
-only for the @code{casa} instruction emitted for the LEON3 processor.  The
-default is @option{-mno-user-mode}.
+only for the @code{casa} instruction emitted for the LEON3 processor.  This
+is the default.
 
 @item -mno-faster-structs
 @itemx -mfaster-structs
-- 
2.4.3

Re: [PATCH] Make muser-mode the default for LEON3

[Sebastian Huber]

Instead of introducing a new option which may conflict with an existing 
one, is it not possible to simply use -mno-user-mode?

On 23/06/15 14:22, Daniel Cederman wrote:
> The muser-mode flag causes the CASA instruction for LEON3 to use the
> user mode ASI. This is the correct behavior for almost all LEON3 targets.
> For this reason it makes sense to make user mode the default. This patch
> adds a flag for supervisor mode that can be used on the very few LEON3 targets
> that requires CASA to use the supervisor ASI.
>
> gcc/ChangeLog:
>
> 2015-06-22  Daniel Cederman  <cederman@gaisler.com>
>
> 	* config/sparc/sparc.opt: Add supervisor mode flag (-msv-mode) and
> 	  make user mode the default
> 	* config/sparc/sync.md: Only use supervisor ASI for CASA when in
> 	  supervisor mode
> 	* doc/invoke.texi: Document msv-mode flag

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber@embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.

Re: [PATCH] Make muser-mode the default for LEON3

[Jakub Jelinek]

On Tue, Jun 23, 2015 at 02:22:34PM +0200, Daniel Cederman wrote:
> The muser-mode flag causes the CASA instruction for LEON3 to use the
> user mode ASI. This is the correct behavior for almost all LEON3 targets.
> For this reason it makes sense to make user mode the default. This patch
> adds a flag for supervisor mode that can be used on the very few LEON3 targets
> that requires CASA to use the supervisor ASI.

Why are you adding a new option and without deprecation removing a
previously accepted (at least since 4.8) option?
For just changing the default, you really don't need to add a new option
or remove -mno-user-mode, just change the default, which can be done
e.g. by checking if the bit has been explicitly set and if not, use the
desired default, or if you want to change the Mask() name, just
make it InverseMask, but keep the options as they are.

	Jakub

Re: [PATCH] Make muser-mode the default for LEON3

[Daniel Cederman]

On 2015-06-23 14:34, Jakub Jelinek wrote:
> On Tue, Jun 23, 2015 at 02:22:34PM +0200, Daniel Cederman wrote:
>> The muser-mode flag causes the CASA instruction for LEON3 to use the
>> user mode ASI. This is the correct behavior for almost all LEON3 targets.
>> For this reason it makes sense to make user mode the default. This patch
>> adds a flag for supervisor mode that can be used on the very few LEON3 targets
>> that requires CASA to use the supervisor ASI.
>
> Why are you adding a new option and without deprecation removing a
> previously accepted (at least since 4.8) option?
> For just changing the default, you really don't need to add a new option
> or remove -mno-user-mode, just change the default, which can be done
> e.g. by checking if the bit has been explicitly set and if not, use the
> desired default, or if you want to change the Mask() name, just
> make it InverseMask, but keep the options as they are.
>
> 	Jakub
>

How does one check if the bit has been explicitly set? It was not 
obvious to me, which is why I took a similar approach to a patch I found 
for another CPU target. If it is possible to change the default without 
adding another flag then that is obviously better and I will update my 
patch.

Best regards,
Daniel Cederman

Re: [PATCH] Make muser-mode the default for LEON3

[Jakub Jelinek]

On Tue, Jun 23, 2015 at 02:48:45PM +0200, Daniel Cederman wrote:
> How does one check if the bit has been explicitly set? It was not obvious to

if (TARGET_USER_MODE_P (target_flags_explicit))

> me, which is why I took a similar approach to a patch I found for another
> CPU target. If it is possible to change the default without adding another
> flag then that is obviously better and I will update my patch.

Or you can just change the default target_flags, supposedly with
TargetVariable
int target_flags = MASK_USER_MODE
in the opt file, there are really many possibilities.

	Jakub

Re: [PATCH] Make muser-mode the default for LEON3

[Daniel Cederman]

On 2015-06-23 14:58, Jakub Jelinek wrote:
> On Tue, Jun 23, 2015 at 02:48:45PM +0200, Daniel Cederman wrote:
>> How does one check if the bit has been explicitly set? It was not obvious to
>
> if (TARGET_USER_MODE_P (target_flags_explicit))
>
>> me, which is why I took a similar approach to a patch I found for another
>> CPU target. If it is possible to change the default without adding another
>> flag then that is obviously better and I will update my patch.
>
> Or you can just change the default target_flags, supposedly with
> TargetVariable
> int target_flags = MASK_USER_MODE
> in the opt file, there are really many possibilities.
>
> 	Jakub
>

Thanks! I went with your suggestion in the previous mail and removed the 
new -msv-mode option and inversed the user mode mask.

Best regards,
Daniel Cederman

Re: [PATCH] Use leon3 target for native LEON on Linux

[Eric Botcazou]

> 2015-06-23  Daniel Cederman  <cederman@gaisler.com>
> 
> 	* config/sparc/driver-sparc.c: map /proc/cpuinfo with CPU LEON
> 	  to leon3

OK for mainline and 5 branch (and 4.9 branch once it reopens), but the 
ChangeLog entry should be:

	* config/sparc/driver-sparc.c (cpu_names): Map LEON to leon3.


-- 
Eric Botcazou

Re: [PATCH 2/2] Add leon3r0 and leon3r0v7 CPU targets

[Eric Botcazou]

> Early variants of LEON3, revision 0, do not support the CASA instruction.
> This patch adds two new targets, leon3r0 and leon3r0v7, that are equivalent
> to leon3 and leon3v7, except that they do not support CASA.

Why not use leon instead of leon3 for them?

-- 
Eric Botcazou

Re: [PATCH 2/2] Add leon3r0 and leon3r0v7 CPU targets

[Daniel Cederman]

On 2015-06-26 09:45, Eric Botcazou wrote:
>> Early variants of LEON3, revision 0, do not support the CASA instruction.
>> This patch adds two new targets, leon3r0 and leon3r0v7, that are equivalent
>> to leon3 and leon3v7, except that they do not support CASA.
>
> Why not use leon instead of leon3 for them?
>

The UT699 is a leon3r0 system which does not support CASA. However, to 
enable the errata fixes for UT699 with -mfix-ut699 requires the CPU 
target to be leon3. This causes the CASA instruction to be generated for 
UT699.

The instruction timing also differs between leon and leon3 and they are 
represented by different targets in binutils.

-- 
Daniel Cederman

Re: [PATCH 2/2] Add leon3r0 and leon3r0v7 CPU targets

[Eric Botcazou]

> The UT699 is a leon3r0 system which does not support CASA. However, to
> enable the errata fixes for UT699 with -mfix-ut699 requires the CPU
> target to be leon3.

-mfix-ut699 itself is independent of the processor and doesn't require leon3.

> The instruction timing also differs between leon and leon3 and they are
> represented by different targets in binutils.

Yes, there is only one optimization trick for the scheduler that requires 
leon3, but it doesn't affect correctness.  We could easily change that, i.e. 
enable the trick for leon too if -mfix-ut699 is passed.

As for binutils, they don't even know about leon3, eveything is leon for them.

-- 
Eric Botcazou

Re: [PATCH 2/2] Add leon3r0 and leon3r0v7 CPU targets

[Eric Botcazou]

[-- Attachment #1: Type: text/plain, Size: 536 bytes --]

> Yes, there is only one optimization trick for the scheduler that requires
> leon3, but it doesn't affect correctness.  We could easily change that, i.e.
> enable the trick for leon too if -mfix-ut699 is passed.

Like this, applied on all branches.


2015-06-30  Eric Botcazou  <ebotcazou@adacore.com>

	* config/sparc/leon.md (leon_load): Enable for all LEON variants if
	-mfix-ut699 is not specified.
	(leon3_load): Rename into...
	(ut699_load): ...this.  Enable for all LEON variants if -mfix-ut699
	is specified.

-- 
Eric Botcazou

[-- Attachment #2: leon_sched.diff --]
[-- Type: text/x-patch, Size: 922 bytes --]

Index: config/sparc/leon.md
===================================================================
--- config/sparc/leon.md	(revision 225111)
+++ config/sparc/leon.md	(working copy)
@@ -24,12 +24,14 @@ (define_automaton "leon")
 (define_cpu_unit "leon_memory" "leon")
 
 (define_insn_reservation "leon_load" 1
-  (and (eq_attr "cpu" "leon") (eq_attr "type" "load,sload"))
+  (and (eq_attr "cpu" "leon,leon3,leon3v7")
+       (and (eq_attr "fix_ut699" "false") (eq_attr "type" "load,sload")))
   "leon_memory")
 
 ;; Use a double reservation to work around the load pipeline hazard on UT699.
-(define_insn_reservation "leon3_load" 1
-  (and (eq_attr "cpu" "leon3,leon3v7") (eq_attr "type" "load,sload"))
+(define_insn_reservation "ut699_load" 1
+  (and (eq_attr "cpu" "leon,leon3,leon3v7")
+       (and (eq_attr "fix_ut699" "true") (eq_attr "type" "load,sload")))
   "leon_memory*2")
 
 (define_insn_reservation "leon_store" 2

Re: [PATCH 2/2] Add leon3r0 and leon3r0v7 CPU targets

[Daniel Cederman]

On 2015-06-30 11:24, Eric Botcazou wrote:
>> The UT699 is a leon3r0 system which does not support CASA. However, to
>> enable the errata fixes for UT699 with -mfix-ut699 requires the CPU
>> target to be leon3.
>
> -mfix-ut699 itself is independent of the processor and doesn't require leon3.
>
>> The instruction timing also differs between leon and leon3 and they are
>> represented by different targets in binutils.
>
> Yes, there is only one optimization trick for the scheduler that requires
> leon3, but it doesn't affect correctness.  We could easily change that, i.e.
> enable the trick for leon too if -mfix-ut699 is passed.
>

Thank you for the patch in your other mail that changes this!

We were also thinking of the instruction timing information found in the 
leon_costs and leon3_costs. We took a look at the values in leon_costs 
and they seem to fit well with the UT699, except for division. We got a 
bit unsure as to what leon system they are based on, as the division 
cost was wrong also for the AT697F, which is the most common leon2 
system. Would it be ok to update the division cost values of leon_costs 
so that they match UT699 and AT697F?

In general, depending on how one instantiate a leon system and which FPU 
is selected, you will get different timing. Is there a recommended way 
of adding support for this without adding additional CPU targets?
We are considering to add support for GRFPU-lite, which only differs in 
the timing.

> As for binutils, they don't even know about leon3, eveything is leon for them.
>

Yes, that was a misunderstanding from my part.

-- 
Daniel Cederman

Re: [PATCH 2/2] Add leon3r0 and leon3r0v7 CPU targets

[Eric Botcazou]

> Thank you for the patch in your other mail that changes this!

You're welcome.

> We were also thinking of the instruction timing information found in the
> leon_costs and leon3_costs. We took a look at the values in leon_costs
> and they seem to fit well with the UT699, except for division. We got a
> bit unsure as to what leon system they are based on, as the division
> cost was wrong also for the AT697F, which is the most common leon2
> system. Would it be ok to update the division cost values of leon_costs
> so that they match UT699 and AT697F?

Sure.

> In general, depending on how one instantiate a leon system and which FPU
> is selected, you will get different timing. Is there a recommended way
> of adding support for this without adding additional CPU targets?
> We are considering to add support for GRFPU-lite, which only differs in
> the timing.

One could add a -mtune-fpu switch.  Did you look at other architectures in the 
GCC tree that would have similar requirements?

-- 
Eric Botcazou

Re: [PATCH 2/2] Add leon3r0 and leon3r0v7 CPU targets

[Daniel Cederman]

> One could add a -mtune-fpu switch.  Did you look at other architectures in the
> GCC tree that would have similar requirements?
>

Thank you for the suggestion about adding a -mtune-fpu switch. I have 
not yet looked at the other architectures, but will do so before proceeding.

-- 
Daniel Cederman

Re: [PATCH] Make muser-mode the default for LEON3

[Eric Botcazou]

> For all LEON3 (with CASA support) the CASA instruction works in
> supervisor-mode regardless of ASI used. In user-mode CASA only works
> with the user-mode ASI. So CASA with user-mode ASI works for both
> user-mode and supervisor-mode. By having user-mode ASI as default, one
> would not need to change flag when compiling user or kernel code.

Thanks, OK for mainline, 5 branch and 4.9 branch.

-- 
Eric Botcazou

Re: [PATCH] Make muser-mode the default for LEON3

[Daniel Cederman]

>
> Do they lack the CASA instruction with supervisor-mode ASI?  What happens when
> the CASA instruction with user-mode ASI is executed in supervisor mode?
>

For all LEON3 (with CASA support) the CASA instruction works in 
supervisor-mode regardless of ASI used. In user-mode CASA only works 
with the user-mode ASI. So CASA with user-mode ASI works for both 
user-mode and supervisor-mode. By having user-mode ASI as default, one 
would not need to change flag when compiling user or kernel code.

On a few old LEON3 systems the CASA instruction only works in supervisor 
mode. Using the CASA instruction with the user-mode ASI on these systems 
is not legal and will cause a trap.

-- 
Daniel Cederman

Re: [PATCH] Make muser-mode the default for LEON3

[Eric Botcazou]

> The muser-mode flag causes the CASA instruction for LEON3 to use the
> user mode ASI. This is the correct behavior for almost all LEON3 targets.

Do they lack the CASA instruction with supervisor-mode ASI?  What happens when 
the CASA instruction with user-mode ASI is executed in supervisor mode?

-- 
Eric Botcazou

[PATCH] Make muser-mode the default for LEON3

[Daniel Cederman]

The muser-mode flag causes the CASA instruction for LEON3 to use the
user mode ASI. This is the correct behavior for almost all LEON3 targets.
For this reason it makes sense to make user mode the default.

gcc/ChangeLog:

2015-06-23  Daniel Cederman  <cederman@gaisler.com>

	* config/sparc/sparc.opt: Rename mask from USER_MODE to SV_MODE
	  and make it inverse to change default
	* config/sparc/sync.md: Only use supervisor ASI for CASA when in
	  supervisor mode
	* doc/invoke.texi: Document change of default
---
 gcc/config/sparc/sparc.opt | 4 ++--
 gcc/config/sparc/sync.md   | 6 +++---
 gcc/doc/invoke.texi        | 4 ++--
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index 93d24a6..85bf0bd 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -114,8 +114,8 @@ Target
 Optimize tail call instructions in assembler and linker
 
 muser-mode
-Target Report Mask(USER_MODE)
-Do not generate code that can only run in supervisor mode
+Target Report InverseMask(SV_MODE)
+Do not generate code that can only run in supervisor mode (default)
 
 mcpu=
 Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7)
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md
index 7d00b10..2fabff5 100644
--- a/gcc/config/sparc/sync.md
+++ b/gcc/config/sparc/sync.md
@@ -222,10 +222,10 @@
 	  UNSPECV_CAS))]
   "TARGET_LEON3"
 {
-  if (TARGET_USER_MODE)
-    return "casa\t%1 0xa, %2, %0"; /* ASI for user data space.  */
-  else
+  if (TARGET_SV_MODE)
     return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space.  */
+  else
+    return "casa\t%1 0xa, %2, %0"; /* ASI for user data space.  */
 }
   [(set_attr "type" "multi")])
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b99ab1c..86b2a73 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21305,8 +21305,8 @@ in a performance loss, especially for floating-point code.
 @opindex muser-mode
 @opindex mno-user-mode
 Do not generate code that can only run in supervisor mode.  This is relevant
-only for the @code{casa} instruction emitted for the LEON3 processor.  The
-default is @option{-mno-user-mode}.
+only for the @code{casa} instruction emitted for the LEON3 processor.  This
+is the default.
 
 @item -mno-faster-structs
 @itemx -mfaster-structs
-- 
2.4.3